Lines Matching +full:0 +full:x620
42 return 0; in lan88xx_suspend()
48 int val, save_page, ret = 0; in lan88xx_TR_reg_set()
53 if (save_page < 0) { in lan88xx_TR_reg_set()
62 (data & 0xFFFF)); in lan88xx_TR_reg_set()
63 if (ret < 0) { in lan88xx_TR_reg_set()
69 (data & 0x00FF0000) >> 16); in lan88xx_TR_reg_set()
70 if (ret < 0) { in lan88xx_TR_reg_set()
76 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */ in lan88xx_TR_reg_set()
77 buf |= 0x8000; /* Set [15] to Packet transmit */ in lan88xx_TR_reg_set()
80 if (ret < 0) { in lan88xx_TR_reg_set()
87 if (!(val & 0x8000)) in lan88xx_TR_reg_set()
88 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n", in lan88xx_TR_reg_set()
98 /* Get access to Channel 0x1, Node 0xF , Register 0x01. in lan88xx_config_TR_regs()
99 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf, in lan88xx_config_TR_regs()
102 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A); in lan88xx_config_TR_regs()
103 if (err < 0) in lan88xx_config_TR_regs()
104 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n"); in lan88xx_config_TR_regs()
106 /* Get access to Channel b'10, Node b'1101, Register 0x06. in lan88xx_config_TR_regs()
107 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv, in lan88xx_config_TR_regs()
110 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F); in lan88xx_config_TR_regs()
111 if (err < 0) in lan88xx_config_TR_regs()
112 phydev_warn(phydev, "Failed to Set Register[0x168C]\n"); in lan88xx_config_TR_regs()
114 /* Get access to Channel b'10, Node b'1111, Register 0x11. in lan88xx_config_TR_regs()
115 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh in lan88xx_config_TR_regs()
118 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620); in lan88xx_config_TR_regs()
119 if (err < 0) in lan88xx_config_TR_regs()
120 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n"); in lan88xx_config_TR_regs()
122 /* Get access to Channel b'10, Node b'1101, Register 0x10. in lan88xx_config_TR_regs()
123 * Write 24-bit value 0xEEFFDD to register. Setting in lan88xx_config_TR_regs()
127 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD); in lan88xx_config_TR_regs()
128 if (err < 0) in lan88xx_config_TR_regs()
129 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n"); in lan88xx_config_TR_regs()
131 /* Get access to Channel b'10, Node b'1101, Register 0x13. in lan88xx_config_TR_regs()
132 * Write 24-bit value 0x071448 to register. Setting in lan88xx_config_TR_regs()
135 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448); in lan88xx_config_TR_regs()
136 if (err < 0) in lan88xx_config_TR_regs()
137 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n"); in lan88xx_config_TR_regs()
139 /* Get access to Channel b'10, Node b'1101, Register 0x12. in lan88xx_config_TR_regs()
140 * Write 24-bit value 0x13132F to register. Setting in lan88xx_config_TR_regs()
143 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F); in lan88xx_config_TR_regs()
144 if (err < 0) in lan88xx_config_TR_regs()
145 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n"); in lan88xx_config_TR_regs()
147 /* Get access to Channel b'10, Node b'1101, Register 0x14. in lan88xx_config_TR_regs()
148 * Write 24-bit value 0x0 to register. Setting eee_3level_delay, in lan88xx_config_TR_regs()
151 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0); in lan88xx_config_TR_regs()
152 if (err < 0) in lan88xx_config_TR_regs()
153 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n"); in lan88xx_config_TR_regs()
155 /* Get access to Channel b'01, Node b'1111, Register 0x34. in lan88xx_config_TR_regs()
156 * Write 24-bit value 0x91B06C to register. Setting in lan88xx_config_TR_regs()
160 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C); in lan88xx_config_TR_regs()
161 if (err < 0) in lan88xx_config_TR_regs()
162 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n"); in lan88xx_config_TR_regs()
164 /* Get access to Channel b'01, Node b'1111, Register 0x3E. in lan88xx_config_TR_regs()
165 * Write 24-bit value 0xC0A028 to register. Setting in lan88xx_config_TR_regs()
169 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028); in lan88xx_config_TR_regs()
170 if (err < 0) in lan88xx_config_TR_regs()
171 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n"); in lan88xx_config_TR_regs()
173 /* Get access to Channel b'01, Node b'1111, Register 0x35. in lan88xx_config_TR_regs()
174 * Write 24-bit value 0x041600 to register. Setting in lan88xx_config_TR_regs()
178 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600); in lan88xx_config_TR_regs()
179 if (err < 0) in lan88xx_config_TR_regs()
180 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n"); in lan88xx_config_TR_regs()
182 /* Get access to Channel b'10, Node b'1101, Register 0x03. in lan88xx_config_TR_regs()
183 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits. in lan88xx_config_TR_regs()
185 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004); in lan88xx_config_TR_regs()
186 if (err < 0) in lan88xx_config_TR_regs()
187 phydev_warn(phydev, "Failed to Set Register[0x1686]\n"); in lan88xx_config_TR_regs()
201 priv->wolopts = 0; in lan88xx_probe()
206 0, in lan88xx_probe()
208 if (len >= 0) { in lan88xx_probe()
209 u32 reg = 0; in lan88xx_probe()
212 for (i = 0; i < len; i++) { in lan88xx_probe()
230 return 0; in lan88xx_probe()
249 return 0; in lan88xx_set_wol()
294 return 0; in lan88xx_config_init()
337 .phy_id = 0x0007c132,
338 /* This mask (0xfffffff2) is to differentiate from
339 * LAN8742 (phy_id 0x0007c130 and 0x0007c131)
342 .phy_id_mask = 0xfffffff2,
368 { 0x0007c132, 0xfffffff2 },