net/phy/dp83640_reg.h

1 /* SPDX-License-Identifier: GPL-2.0 */
20 #define PTP_TXTS                  0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS                  0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
40 #define PTP_COC                   0x0014 /* PTP Clock Output Control Register */
47 #define PTP_CLKSRC                0x001b /* PTP Clock Source Register */
63 #define PTP_RD_CLK                (1<<5)  /* Read PTP Clock */
64 #define PTP_LOAD_CLK              (1<<4)  /* Load PTP Clock */
65 #define PTP_STEP_CLK              (1<<3)  /* Step PTP Clock */
66 #define PTP_ENABLE                (1<<2)  /* Enable PTP Clock */
67 #define PTP_DISABLE               (1<<1)  /* Disable PTP Clock */
68 #define PTP_RESET                 (1<<0)  /* Reset PTP Clock */
81 #define TRIG7_ERROR               (1<<15) /* Trigger 7 Error */
83 #define TRIG6_ERROR               (1<<13) /* Trigger 6 Error */
85 #define TRIG5_ERROR               (1<<11) /* Trigger 5 Error */
87 #define TRIG4_ERROR               (1<<9)  /* Trigger 4 Error */
89 #define TRIG3_ERROR               (1<<7)  /* Trigger 3 Error */
91 #define TRIG2_ERROR               (1<<5)  /* Trigger 2 Error */
93 #define TRIG1_ERROR               (1<<3)  /* Trigger 1 Error */
95 #define TRIG0_ERROR               (1<<1)  /* Trigger 0 Error */
101 #define PTP_RATE_HI_SHIFT         (0)     /* PTP Rate High 10-bits */
107 #define EVNT_TS_LEN_SHIFT         (6)     /* Indicates length of the Timestamp field in 16-bit word…
138 #define TRIG_GPIO_SHIFT           (8)     /* Trigger GPIO Connection, value 1-12 */
146 #define EVNT_RISE                 (1<<14) /* Event Rise Detect Enable */
147 #define EVNT_FALL                 (1<<13) /* Event Fall Detect Enable */
149 #define EVNT_GPIO_SHIFT           (8)     /* Event GPIO Connection, value 1-12 */
159 #define IGNORE_2STEP              (1<<11) /* Ignore Two_Step flag for One-Step operation */
160 #define CRC_1STEP                 (1<<10) /* Disable checking of CRC for One-Step operation */
161 #define CHK_1STEP                 (1<<9)  /* Enable UDP Checksum correction for One-Step Operation …
184 #define PSF_ERR_EN                (1<<4)  /* Error PHY Status Frame Enable */
194 #define USER_IP_EN                (1<<12) /* Enable User-programmed IP address filter */
212 #define TS_MIN_IFG_SHIFT          (12)    /* Minimum Inter-frame Gap */
214 #define ACC_UDP                   (1<<11) /* Record Timestamp if UDP Checksum Error */
215 #define ACC_CRC                   (1<<10) /* Record Timestamp if CRC Error */
232 #define PTP_CLKOUT_EN             (1<<15) /* PTP Clock Output Enable */
233 #define PTP_CLKOUT_SEL            (1<<14) /* PTP Clock Output Source Select */
234 #define PTP_CLKOUT_SPEEDSEL       (1<<13) /* PTP Clock Output I/O Speed Select */
235 #define PTP_CLKDIV_SHIFT          (0)     /* PTP Clock Divide-by Value */
249 #define TX_SFD_GPIO_SHIFT         (4)     /* TX SFD GPIO Select, value 1-12 */
251 #define RX_SFD_GPIO_SHIFT         (0)     /* RX SFD GPIO Select, value 1-12 */
259 #define CLK_SRC_SHIFT             (14)    /* PTP Clock Source Select */
261 #define CLK_SRC_PER_SHIFT         (0)     /* PTP Clock Source Period */