18 #define PHY_ID_AQ1202	0x03a1b445
19 #define PHY_ID_AQ2104	0x03a1b460
20 #define PHY_ID_AQR105	0x03a1b4a2
21 #define PHY_ID_AQR106	0x03a1b4d0
22 #define PHY_ID_AQR107	0x03a1b4e0
23 #define PHY_ID_AQCS109	0x03a1b5c2
24 #define PHY_ID_AQR405	0x03a1b4b0
25 #define PHY_ID_AQR112	0x03a1b662
26 #define PHY_ID_AQR412	0x03a1b712
27 #define PHY_ID_AQR113C	0x31c31c12
29 #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR	0
40 #define MDIO_AN_VEND_PROV			0xc400
46 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
49 #define MDIO_AN_TX_VEND_STATUS1			0xc800
51 #define MDIO_AN_TX_VEND_STATUS1_10BASET		0
57 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX	BIT(0)
59 #define MDIO_AN_TX_VEND_INT_STATUS1		0xcc00
62 #define MDIO_AN_TX_VEND_INT_STATUS2		0xcc01
63 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK	BIT(0)
65 #define MDIO_AN_TX_VEND_INT_MASK2		0xd401
66 #define MDIO_AN_TX_VEND_INT_MASK2_LINK		BIT(0)
68 #define MDIO_AN_RX_LP_STAT1			0xe820
75 #define MDIO_AN_RX_LP_STAT4			0xe823
77 #define MDIO_AN_RX_LP_STAT4_FW_MINOR		GENMASK(7, 0)
79 #define MDIO_AN_RX_VEND_STAT3			0xe832
80 #define MDIO_AN_RX_VEND_STAT3_AFR		BIT(0)
83 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES		0xd292
84 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES		0xd294
85 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER		0xd297
86 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES		0xd313
87 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES		0xd315
88 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER		0xd317
89 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS		0xd318
90 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS	0xd319
91 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
92 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
95 #define VEND1_GLOBAL_FW_ID			0x0020
97 #define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
99 #define VEND1_GLOBAL_GEN_STAT2			0xc831
103 #define VEND1_GLOBAL_CFG_10M			0x0310
104 #define VEND1_GLOBAL_CFG_100M			0x031b
105 #define VEND1_GLOBAL_CFG_1G			0x031c
106 #define VEND1_GLOBAL_CFG_2_5G			0x031d
107 #define VEND1_GLOBAL_CFG_5G			0x031e
108 #define VEND1_GLOBAL_CFG_10G			0x031f
111 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
115 #define VEND1_GLOBAL_RSVD_STAT1			0xc885
117 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
119 #define VEND1_GLOBAL_RSVD_STAT9			0xc88d
120 #define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
121 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
123 #define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
124 #define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
126 #define VEND1_GLOBAL_INT_STD_MASK		0xff00
137 #define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
139 #define VEND1_GLOBAL_INT_VEND_MASK		0xff01
147 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
189 	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)  in aqr107_get_strings()
203 	if (val < 0)  in aqr107_get_stat()
206 	ret = val & GENMASK(len_l - 1, 0);  in aqr107_get_stat()
209 		if (val < 0)  in aqr107_get_stat()
212 		ret += (val & GENMASK(len_h - 1, 0)) << 16;  in aqr107_get_stat()
225 	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {  in aqr107_get_stats()
247 	if (ret < 0)  in aqr_config_aneg()
249 	if (ret > 0)  in aqr_config_aneg()
255 	reg = 0;  in aqr_config_aneg()
278 	if (ret < 0)  in aqr_config_aneg()
280 	if (ret > 0)  in aqr_config_aneg()
294 		if (err < 0)  in aqr_config_intr()
299 			    en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);  in aqr_config_intr()
300 	if (err < 0)  in aqr_config_intr()
304 			    en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);  in aqr_config_intr()
305 	if (err < 0)  in aqr_config_intr()
310 			    VEND1_GLOBAL_INT_VEND_MASK_AN : 0);  in aqr_config_intr()
311 	if (err < 0)  in aqr_config_intr()
317 		if (err < 0)  in aqr_config_intr()
321 	return 0;  in aqr_config_intr()
330 	if (irq_status < 0) {  in aqr_handle_interrupt()
349 		if (val < 0)  in aqr_read_status()
369 	if (val < 0)  in aqr107_read_rate()
404 		return 0;  in aqr107_read_rate()
408 	if (val < 0)  in aqr107_read_rate()
417 	return 0;  in aqr107_read_rate()
429 		return 0;  in aqr107_read_status()
432 	if (val < 0)  in aqr107_read_status()
474 	if (val < 0)  in aqr107_get_downshift()
482 	return 0;  in aqr107_get_downshift()
487 	int val = 0;  in aqr107_set_downshift()
536 					 VEND1_GLOBAL_FW_ID, val, val != 0,  in aqr107_wait_reset_complete()
546 	if (val < 0)  in aqr107_chip_info()
553 	if (val < 0)  in aqr107_chip_info()
622 	if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))  in aqr107_link_change_notify()
629 	if (val < 0)  in aqr107_link_change_notify()
636 	if (val < 0)  in aqr107_link_change_notify()
648 	if (val < 0)  in aqr107_link_change_notify()
677 	return 0;  in aqr107_wait_processor_intensive_op()