80 #define RTL_W8(tp, reg, val8)	writeb((val8), tp->mmio_addr + (reg))  argument
81 #define RTL_W16(tp, reg, val16)	writew((val16), tp->mmio_addr + (reg))  argument
82 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))  argument
83 #define RTL_R8(tp, reg)		readb(tp->mmio_addr + (reg))  argument
84 #define RTL_R16(tp, reg)		readw(tp->mmio_addr + (reg))  argument
85 #define RTL_R32(tp, reg)		readl(tp->mmio_addr + (reg))  argument
669 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
696 static inline struct device *tp_to_dev(struct rtl8169_private *tp)  in tp_to_dev()  argument
698 	return &tp->pci_dev->dev;  in tp_to_dev()
701 static void rtl_lock_config_regs(struct rtl8169_private *tp)  in rtl_lock_config_regs()  argument
705 	raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);  in rtl_lock_config_regs()
706 	if (!--tp->cfg9346_usage_count)  in rtl_lock_config_regs()
707 		RTL_W8(tp, Cfg9346, Cfg9346_Lock);  in rtl_lock_config_regs()
708 	raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);  in rtl_lock_config_regs()
711 static void rtl_unlock_config_regs(struct rtl8169_private *tp)  in rtl_unlock_config_regs()  argument
715 	raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);  in rtl_unlock_config_regs()
716 	if (!tp->cfg9346_usage_count++)  in rtl_unlock_config_regs()
717 		RTL_W8(tp, Cfg9346, Cfg9346_Unlock);  in rtl_unlock_config_regs()
718 	raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);  in rtl_unlock_config_regs()
721 static void rtl_pci_commit(struct rtl8169_private *tp)  in rtl_pci_commit()  argument
724 	RTL_R8(tp, ChipCmd);  in rtl_pci_commit()
727 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)  in rtl_mod_config2()  argument
732 	raw_spin_lock_irqsave(&tp->config25_lock, flags);  in rtl_mod_config2()
733 	val = RTL_R8(tp, Config2);  in rtl_mod_config2()
734 	RTL_W8(tp, Config2, (val & ~clear) | set);  in rtl_mod_config2()
735 	raw_spin_unlock_irqrestore(&tp->config25_lock, flags);  in rtl_mod_config2()
738 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)  in rtl_mod_config5()  argument
743 	raw_spin_lock_irqsave(&tp->config25_lock, flags);  in rtl_mod_config5()
744 	val = RTL_R8(tp, Config5);  in rtl_mod_config5()
745 	RTL_W8(tp, Config5, (val & ~clear) | set);  in rtl_mod_config5()
746 	raw_spin_unlock_irqrestore(&tp->config25_lock, flags);  in rtl_mod_config5()
749 static bool rtl_is_8125(struct rtl8169_private *tp)  in rtl_is_8125()  argument
751 	return tp->mac_version >= RTL_GIGA_MAC_VER_61;  in rtl_is_8125()
754 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)  in rtl_is_8168evl_up()  argument
756 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_is_8168evl_up()
757 	       tp->mac_version != RTL_GIGA_MAC_VER_39 &&  in rtl_is_8168evl_up()
758 	       tp->mac_version <= RTL_GIGA_MAC_VER_53;  in rtl_is_8168evl_up()
761 static bool rtl_supports_eee(struct rtl8169_private *tp)  in rtl_supports_eee()  argument
763 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_supports_eee()
764 	       tp->mac_version != RTL_GIGA_MAC_VER_37 &&  in rtl_supports_eee()
765 	       tp->mac_version != RTL_GIGA_MAC_VER_39;  in rtl_supports_eee()
768 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)  in rtl_read_mac_from_reg()  argument
773 		mac[i] = RTL_R8(tp, reg + i);  in rtl_read_mac_from_reg()
781 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,  in rtl_loop_wait()  argument
787 		if (c->check(tp) == high)  in rtl_loop_wait()
793 		netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",  in rtl_loop_wait()
798 static bool rtl_loop_wait_high(struct rtl8169_private *tp,  in rtl_loop_wait_high()  argument
802 	return rtl_loop_wait(tp, c, d, n, true);  in rtl_loop_wait_high()
805 static bool rtl_loop_wait_low(struct rtl8169_private *tp,  in rtl_loop_wait_low()  argument
809 	return rtl_loop_wait(tp, c, d, n, false);  in rtl_loop_wait_low()
820 static bool name ## _check(struct rtl8169_private *tp)
822 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)  in r8168fp_adjust_ocp_cmd()  argument
826 	    (tp->mac_version == RTL_GIGA_MAC_VER_52 ||  in r8168fp_adjust_ocp_cmd()
827 	     tp->mac_version == RTL_GIGA_MAC_VER_53))  in r8168fp_adjust_ocp_cmd()
833 	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;  in DECLARE_RTL_COND()
836 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in _rtl_eri_write()  argument
844 	RTL_W32(tp, ERIDR, val);  in _rtl_eri_write()
845 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_write()
846 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_write()
848 	rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);  in _rtl_eri_write()
851 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in rtl_eri_write()  argument
854 	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);  in rtl_eri_write()
857 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)  in _rtl_eri_read()  argument
861 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_read()
862 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_read()
864 	return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?  in _rtl_eri_read()
865 		RTL_R32(tp, ERIDR) : ~0;  in _rtl_eri_read()
868 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)  in rtl_eri_read()  argument
870 	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);  in rtl_eri_read()
873 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)  in rtl_w0w1_eri()  argument
875 	u32 val = rtl_eri_read(tp, addr);  in rtl_w0w1_eri()
877 	rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);  in rtl_w0w1_eri()
880 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)  in rtl_eri_set_bits()  argument
882 	rtl_w0w1_eri(tp, addr, p, 0);  in rtl_eri_set_bits()
885 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)  in rtl_eri_clear_bits()  argument
887 	rtl_w0w1_eri(tp, addr, 0, m);  in rtl_eri_clear_bits()
897 	return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;  in DECLARE_RTL_COND()
900 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_phy_ocp_write()  argument
905 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);  in r8168_phy_ocp_write()
907 	rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);  in r8168_phy_ocp_write()
910 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_phy_ocp_read()  argument
915 	RTL_W32(tp, GPHY_OCP, reg << 15);  in r8168_phy_ocp_read()
917 	return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?  in r8168_phy_ocp_read()
918 		(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;  in r8168_phy_ocp_read()
921 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in __r8168_mac_ocp_write()  argument
926 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);  in __r8168_mac_ocp_write()
929 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_mac_ocp_write()  argument
933 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_write()
934 	__r8168_mac_ocp_write(tp, reg, data);  in r8168_mac_ocp_write()
935 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_write()
938 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)  in __r8168_mac_ocp_read()  argument
943 	RTL_W32(tp, OCPDR, reg << 15);  in __r8168_mac_ocp_read()
945 	return RTL_R32(tp, OCPDR);  in __r8168_mac_ocp_read()
948 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_mac_ocp_read()  argument
953 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_read()
954 	val = __r8168_mac_ocp_read(tp, reg);  in r8168_mac_ocp_read()
955 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_read()
960 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,  in r8168_mac_ocp_modify()  argument
966 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_modify()
967 	data = __r8168_mac_ocp_read(tp, reg);  in r8168_mac_ocp_modify()
968 	__r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);  in r8168_mac_ocp_modify()
969 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_modify()
975 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)  in rtl8168g_phy_suspend_quirk()  argument
977 	switch (tp->mac_version) {  in rtl8168g_phy_suspend_quirk()
980 			rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);  in rtl8168g_phy_suspend_quirk()
982 			rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);  in rtl8168g_phy_suspend_quirk()
989 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168g_mdio_write()  argument
992 		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;  in r8168g_mdio_write()
996 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_write()
999 	if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)  in r8168g_mdio_write()
1000 		rtl8168g_phy_suspend_quirk(tp, value);  in r8168g_mdio_write()
1002 	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);  in r8168g_mdio_write()
1005 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)  in r8168g_mdio_read()  argument
1008 		return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;  in r8168g_mdio_read()
1010 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_read()
1013 	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);  in r8168g_mdio_read()
1016 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)  in mac_mcu_write()  argument
1019 		tp->ocp_base = value << 4;  in mac_mcu_write()
1023 	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);  in mac_mcu_write()
1026 static int mac_mcu_read(struct rtl8169_private *tp, int reg)  in mac_mcu_read()  argument
1028 	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);  in mac_mcu_read()
1033 	return RTL_R32(tp, PHYAR) & 0x80000000;  in DECLARE_RTL_COND()
1036 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8169_mdio_write()  argument
1038 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));  in r8169_mdio_write()
1040 	rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);  in r8169_mdio_write()
1048 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)  in r8169_mdio_read()  argument
1052 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);  in r8169_mdio_read()
1054 	value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?  in r8169_mdio_read()
1055 		RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;  in r8169_mdio_read()
1068 	return RTL_R32(tp, OCPAR) & OCPAR_FLAG;  in DECLARE_RTL_COND()
1073 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)  in r8168dp_2_mdio_start()  argument
1075 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
1078 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)  in r8168dp_2_mdio_stop()  argument
1080 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
1083 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168dp_2_mdio_write()  argument
1085 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_write()
1087 	r8169_mdio_write(tp, reg, value);  in r8168dp_2_mdio_write()
1089 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_write()
1092 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)  in r8168dp_2_mdio_read()  argument
1100 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_read()
1102 	value = r8169_mdio_read(tp, reg);  in r8168dp_2_mdio_read()
1104 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_read()
1109 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)  in rtl_writephy()  argument
1111 	switch (tp->mac_version) {  in rtl_writephy()
1114 		r8168dp_2_mdio_write(tp, location, val);  in rtl_writephy()
1117 		r8168g_mdio_write(tp, location, val);  in rtl_writephy()
1120 		r8169_mdio_write(tp, location, val);  in rtl_writephy()
1125 static int rtl_readphy(struct rtl8169_private *tp, int location)  in rtl_readphy()  argument
1127 	switch (tp->mac_version) {  in rtl_readphy()
1130 		return r8168dp_2_mdio_read(tp, location);  in rtl_readphy()
1132 		return r8168g_mdio_read(tp, location);  in rtl_readphy()
1134 		return r8169_mdio_read(tp, location);  in rtl_readphy()
1140 	return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;  in DECLARE_RTL_COND()
1143 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)  in rtl_ephy_write()  argument
1145 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |  in rtl_ephy_write()
1148 	rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);  in rtl_ephy_write()
1153 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)  in rtl_ephy_read()  argument
1155 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);  in rtl_ephy_read()
1157 	return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?  in rtl_ephy_read()
1158 		RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;  in rtl_ephy_read()
1161 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168dp_ocp_read()  argument
1163 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));  in r8168dp_ocp_read()
1164 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?  in r8168dp_ocp_read()
1165 		RTL_R32(tp, OCPDR) : ~0;  in r8168dp_ocp_read()
1168 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168ep_ocp_read()  argument
1170 	return _rtl_eri_read(tp, reg, ERIAR_OOB);  in r8168ep_ocp_read()
1173 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168dp_ocp_write()  argument
1176 	RTL_W32(tp, OCPDR, data);  in r8168dp_ocp_write()
1177 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_write()
1178 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);  in r8168dp_ocp_write()
1181 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168ep_ocp_write()  argument
1184 	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,  in r8168ep_ocp_write()
1188 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)  in r8168dp_oob_notify()  argument
1190 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);  in r8168dp_oob_notify()
1192 	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);  in r8168dp_oob_notify()
1199 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)  in rtl8168_get_ocp_reg()  argument
1201 	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;  in rtl8168_get_ocp_reg()
1208 	reg = rtl8168_get_ocp_reg(tp);  in DECLARE_RTL_COND()
1210 	return r8168dp_ocp_read(tp, reg) & 0x00000800;  in DECLARE_RTL_COND()
1215 	return r8168ep_ocp_read(tp, 0x124) & 0x00000001;  in DECLARE_RTL_COND()
1220 	return RTL_R8(tp, IBISR0) & 0x20;  in DECLARE_RTL_COND()
1223 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)  in rtl8168ep_stop_cmac()  argument
1225 	RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);  in rtl8168ep_stop_cmac()
1226 	rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);  in rtl8168ep_stop_cmac()
1227 	RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);  in rtl8168ep_stop_cmac()
1228 	RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);  in rtl8168ep_stop_cmac()
1231 static void rtl_dash_loop_wait(struct rtl8169_private *tp,  in rtl_dash_loop_wait()  argument
1235 	if (!tp->dash_enabled)  in rtl_dash_loop_wait()
1237 	rtl_loop_wait(tp, c, usecs, n, high);  in rtl_dash_loop_wait()
1240 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp,  in rtl_dash_loop_wait_high()  argument
1244 	rtl_dash_loop_wait(tp, c, d, n, true);  in rtl_dash_loop_wait_high()
1247 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp,  in rtl_dash_loop_wait_low()  argument
1251 	rtl_dash_loop_wait(tp, c, d, n, false);  in rtl_dash_loop_wait_low()
1254 static void rtl8168dp_driver_start(struct rtl8169_private *tp)  in rtl8168dp_driver_start()  argument
1256 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);  in rtl8168dp_driver_start()
1257 	rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_start()
1260 static void rtl8168ep_driver_start(struct rtl8169_private *tp)  in rtl8168ep_driver_start()  argument
1262 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);  in rtl8168ep_driver_start()
1263 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_start()
1264 	rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);  in rtl8168ep_driver_start()
1267 static void rtl8168_driver_start(struct rtl8169_private *tp)  in rtl8168_driver_start()  argument
1269 	if (tp->dash_type == RTL_DASH_DP)  in rtl8168_driver_start()
1270 		rtl8168dp_driver_start(tp);  in rtl8168_driver_start()
1272 		rtl8168ep_driver_start(tp);  in rtl8168_driver_start()
1275 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)  in rtl8168dp_driver_stop()  argument
1277 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);  in rtl8168dp_driver_stop()
1278 	rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_stop()
1281 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)  in rtl8168ep_driver_stop()  argument
1283 	rtl8168ep_stop_cmac(tp);  in rtl8168ep_driver_stop()
1284 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);  in rtl8168ep_driver_stop()
1285 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_stop()
1286 	rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_stop()
1289 static void rtl8168_driver_stop(struct rtl8169_private *tp)  in rtl8168_driver_stop()  argument
1291 	if (tp->dash_type == RTL_DASH_DP)  in rtl8168_driver_stop()
1292 		rtl8168dp_driver_stop(tp);  in rtl8168_driver_stop()
1294 		rtl8168ep_driver_stop(tp);  in rtl8168_driver_stop()
1297 static bool r8168dp_check_dash(struct rtl8169_private *tp)  in r8168dp_check_dash()  argument
1299 	u16 reg = rtl8168_get_ocp_reg(tp);  in r8168dp_check_dash()
1301 	return r8168dp_ocp_read(tp, reg) & BIT(15);  in r8168dp_check_dash()
1304 static bool r8168ep_check_dash(struct rtl8169_private *tp)  in r8168ep_check_dash()  argument
1306 	return r8168ep_ocp_read(tp, 0x128) & BIT(0);  in r8168ep_check_dash()
1309 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)  in rtl_dash_is_enabled()  argument
1311 	switch (tp->dash_type) {  in rtl_dash_is_enabled()
1313 		return r8168dp_check_dash(tp);  in rtl_dash_is_enabled()
1315 		return r8168ep_check_dash(tp);  in rtl_dash_is_enabled()
1321 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)  in rtl_get_dash_type()  argument
1323 	switch (tp->mac_version) {  in rtl_get_dash_type()
1334 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)  in rtl_set_d3_pll_down()  argument
1336 	switch (tp->mac_version) {  in rtl_set_d3_pll_down()
1342 			RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);  in rtl_set_d3_pll_down()
1344 			RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);  in rtl_set_d3_pll_down()
1351 static void rtl_reset_packet_filter(struct rtl8169_private *tp)  in rtl_reset_packet_filter()  argument
1353 	rtl_eri_clear_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1354 	rtl_eri_set_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1359 	return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;  in DECLARE_RTL_COND()
1362 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)  in rtl8168d_efuse_read()  argument
1364 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);  in rtl8168d_efuse_read()
1366 	return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?  in rtl8168d_efuse_read()
1367 		RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;  in rtl8168d_efuse_read()
1370 static u32 rtl_get_events(struct rtl8169_private *tp)  in rtl_get_events()  argument
1372 	if (rtl_is_8125(tp))  in rtl_get_events()
1373 		return RTL_R32(tp, IntrStatus_8125);  in rtl_get_events()
1375 		return RTL_R16(tp, IntrStatus);  in rtl_get_events()
1378 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)  in rtl_ack_events()  argument
1380 	if (rtl_is_8125(tp))  in rtl_ack_events()
1381 		RTL_W32(tp, IntrStatus_8125, bits);  in rtl_ack_events()
1383 		RTL_W16(tp, IntrStatus, bits);  in rtl_ack_events()
1386 static void rtl_irq_disable(struct rtl8169_private *tp)  in rtl_irq_disable()  argument
1388 	if (rtl_is_8125(tp))  in rtl_irq_disable()
1389 		RTL_W32(tp, IntrMask_8125, 0);  in rtl_irq_disable()
1391 		RTL_W16(tp, IntrMask, 0);  in rtl_irq_disable()
1394 static void rtl_irq_enable(struct rtl8169_private *tp)  in rtl_irq_enable()  argument
1396 	if (rtl_is_8125(tp))  in rtl_irq_enable()
1397 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);  in rtl_irq_enable()
1399 		RTL_W16(tp, IntrMask, tp->irq_mask);  in rtl_irq_enable()
1402 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)  in rtl8169_irq_mask_and_ack()  argument
1404 	rtl_irq_disable(tp);  in rtl8169_irq_mask_and_ack()
1405 	rtl_ack_events(tp, 0xffffffff);  in rtl8169_irq_mask_and_ack()
1406 	rtl_pci_commit(tp);  in rtl8169_irq_mask_and_ack()
1409 static void rtl_link_chg_patch(struct rtl8169_private *tp)  in rtl_link_chg_patch()  argument
1411 	struct phy_device *phydev = tp->phydev;  in rtl_link_chg_patch()
1413 	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||  in rtl_link_chg_patch()
1414 	    tp->mac_version == RTL_GIGA_MAC_VER_38) {  in rtl_link_chg_patch()
1416 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1417 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1419 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1420 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1422 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1423 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1425 		rtl_reset_packet_filter(tp);  in rtl_link_chg_patch()
1426 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||  in rtl_link_chg_patch()
1427 		   tp->mac_version == RTL_GIGA_MAC_VER_36) {  in rtl_link_chg_patch()
1429 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1430 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1432 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1433 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1435 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {  in rtl_link_chg_patch()
1437 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);  in rtl_link_chg_patch()
1438 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);  in rtl_link_chg_patch()
1440 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_link_chg_patch()
1449 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_wol()  local
1452 	wol->wolopts = tp->saved_wolopts;  in rtl8169_get_wol()
1455 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)  in __rtl8169_set_wol()  argument
1473 	rtl_unlock_config_regs(tp);  in __rtl8169_set_wol()
1475 	if (rtl_is_8168evl_up(tp)) {  in __rtl8169_set_wol()
1478 			rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1480 			rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1481 	} else if (rtl_is_8125(tp)) {  in __rtl8169_set_wol()
1484 			r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));  in __rtl8169_set_wol()
1486 			r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);  in __rtl8169_set_wol()
1489 	raw_spin_lock_irqsave(&tp->config25_lock, flags);  in __rtl8169_set_wol()
1491 		options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;  in __rtl8169_set_wol()
1494 		RTL_W8(tp, cfg[i].reg, options);  in __rtl8169_set_wol()
1496 	raw_spin_unlock_irqrestore(&tp->config25_lock, flags);  in __rtl8169_set_wol()
1498 	switch (tp->mac_version) {  in __rtl8169_set_wol()
1500 		options = RTL_R8(tp, Config1) & ~PMEnable;  in __rtl8169_set_wol()
1503 		RTL_W8(tp, Config1, options);  in __rtl8169_set_wol()
1509 			rtl_mod_config2(tp, 0, PME_SIGNAL);  in __rtl8169_set_wol()
1511 			rtl_mod_config2(tp, PME_SIGNAL, 0);  in __rtl8169_set_wol()
1517 	rtl_lock_config_regs(tp);  in __rtl8169_set_wol()
1519 	device_set_wakeup_enable(tp_to_dev(tp), wolopts);  in __rtl8169_set_wol()
1521 	if (!tp->dash_enabled) {  in __rtl8169_set_wol()
1522 		rtl_set_d3_pll_down(tp, !wolopts);  in __rtl8169_set_wol()
1523 		tp->dev->wol_enabled = wolopts ? 1 : 0;  in __rtl8169_set_wol()
1529 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_wol()  local
1534 	tp->saved_wolopts = wol->wolopts;  in rtl8169_set_wol()
1535 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_set_wol()
1543 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_drvinfo()  local
1544 	struct rtl_fw *rtl_fw = tp->rtl_fw;  in rtl8169_get_drvinfo()
1547 	strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));  in rtl8169_get_drvinfo()
1562 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_fix_features()  local
1568 	    tp->mac_version > RTL_GIGA_MAC_VER_06)  in rtl8169_fix_features()
1574 static void rtl_set_rx_config_features(struct rtl8169_private *tp,  in rtl_set_rx_config_features()  argument
1577 	u32 rx_config = RTL_R32(tp, RxConfig);  in rtl_set_rx_config_features()
1584 	if (rtl_is_8125(tp)) {  in rtl_set_rx_config_features()
1591 	RTL_W32(tp, RxConfig, rx_config);  in rtl_set_rx_config_features()
1597 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_features()  local
1599 	rtl_set_rx_config_features(tp, features);  in rtl8169_set_features()
1602 		tp->cp_cmd |= RxChkSum;  in rtl8169_set_features()
1604 		tp->cp_cmd &= ~RxChkSum;  in rtl8169_set_features()
1606 	if (!rtl_is_8125(tp)) {  in rtl8169_set_features()
1608 			tp->cp_cmd |= RxVlan;  in rtl8169_set_features()
1610 			tp->cp_cmd &= ~RxVlan;  in rtl8169_set_features()
1613 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl8169_set_features()
1614 	rtl_pci_commit(tp);  in rtl8169_set_features()
1636 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_regs()  local
1637 	u32 __iomem *data = tp->mmio_addr;  in rtl8169_get_regs()
1673 	return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);  in DECLARE_RTL_COND()
1676 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)  in rtl8169_do_counters()  argument
1678 	u32 cmd = lower_32_bits(tp->counters_phys_addr);  in rtl8169_do_counters()
1680 	RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));  in rtl8169_do_counters()
1681 	rtl_pci_commit(tp);  in rtl8169_do_counters()
1682 	RTL_W32(tp, CounterAddrLow, cmd);  in rtl8169_do_counters()
1683 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);  in rtl8169_do_counters()
1685 	rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);  in rtl8169_do_counters()
1688 static void rtl8169_update_counters(struct rtl8169_private *tp)  in rtl8169_update_counters()  argument
1690 	u8 val = RTL_R8(tp, ChipCmd);  in rtl8169_update_counters()
1697 		rtl8169_do_counters(tp, CounterDump);  in rtl8169_update_counters()
1700 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)  in rtl8169_init_counter_offsets()  argument
1702 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_init_counter_offsets()
1719 	if (tp->tc_offset.inited)  in rtl8169_init_counter_offsets()
1722 	if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {  in rtl8169_init_counter_offsets()
1723 		rtl8169_do_counters(tp, CounterReset);  in rtl8169_init_counter_offsets()
1725 		rtl8169_update_counters(tp);  in rtl8169_init_counter_offsets()
1726 		tp->tc_offset.tx_errors = counters->tx_errors;  in rtl8169_init_counter_offsets()
1727 		tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;  in rtl8169_init_counter_offsets()
1728 		tp->tc_offset.tx_aborted = counters->tx_aborted;  in rtl8169_init_counter_offsets()
1729 		tp->tc_offset.rx_missed = counters->rx_missed;  in rtl8169_init_counter_offsets()
1732 	tp->tc_offset.inited = true;  in rtl8169_init_counter_offsets()
1738 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_ethtool_stats()  local
1741 	counters = tp->counters;  in rtl8169_get_ethtool_stats()
1742 	rtl8169_update_counters(tp);  in rtl8169_get_ethtool_stats()
1822 rtl_coalesce_info(struct rtl8169_private *tp)  in rtl_coalesce_info()  argument
1826 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_coalesce_info()
1832 	if (tp->phydev->speed == SPEED_UNKNOWN)  in rtl_coalesce_info()
1836 		if (tp->phydev->speed == ci->speed)  in rtl_coalesce_info()
1848 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_get_coalesce()  local
1853 	if (rtl_is_8125(tp))  in rtl_get_coalesce()
1859 	ci = rtl_coalesce_info(tp);  in rtl_get_coalesce()
1863 	scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];  in rtl_get_coalesce()
1865 	intrmit = RTL_R16(tp, IntrMitigate);  in rtl_get_coalesce()
1884 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,  in rtl_coalesce_choose_scale()  argument
1890 	ci = rtl_coalesce_info(tp);  in rtl_coalesce_choose_scale()
1909 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_coalesce()  local
1916 	if (rtl_is_8125(tp))  in rtl_set_coalesce()
1923 	scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);  in rtl_set_coalesce()
1955 	RTL_W16(tp, IntrMitigate, w);  in rtl_set_coalesce()
1958 	if (rtl_is_8168evl_up(tp)) {  in rtl_set_coalesce()
1961 			tp->cp_cmd |= PktCntrDisable;  in rtl_set_coalesce()
1963 			tp->cp_cmd &= ~PktCntrDisable;  in rtl_set_coalesce()
1966 	tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;  in rtl_set_coalesce()
1967 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_set_coalesce()
1968 	rtl_pci_commit(tp);  in rtl_set_coalesce()
1975 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_eee()  local
1977 	if (!rtl_supports_eee(tp))  in rtl8169_get_eee()
1980 	return phy_ethtool_get_eee(tp->phydev, data);  in rtl8169_get_eee()
1985 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_eee()  local
1988 	if (!rtl_supports_eee(tp))  in rtl8169_set_eee()
1991 	ret = phy_ethtool_set_eee(tp->phydev, data);  in rtl8169_set_eee()
1994 		tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,  in rtl8169_set_eee()
2013 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_pauseparam()  local
2016 	phy_get_pause(tp->phydev, &tx_pause, &rx_pause);  in rtl8169_get_pauseparam()
2018 	data->autoneg = tp->phydev->autoneg;  in rtl8169_get_pauseparam()
2026 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_pauseparam()  local
2031 	phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);  in rtl8169_set_pauseparam()
2061 static void rtl_enable_eee(struct rtl8169_private *tp)  in rtl_enable_eee()  argument
2063 	struct phy_device *phydev = tp->phydev;  in rtl_enable_eee()
2067 	if (tp->eee_adv >= 0)  in rtl_enable_eee()
2068 		adv = tp->eee_adv;  in rtl_enable_eee()
2208 static void rtl_release_firmware(struct rtl8169_private *tp)  in rtl_release_firmware()  argument
2210 	if (tp->rtl_fw) {  in rtl_release_firmware()
2211 		rtl_fw_release_firmware(tp->rtl_fw);  in rtl_release_firmware()
2212 		kfree(tp->rtl_fw);  in rtl_release_firmware()
2213 		tp->rtl_fw = NULL;  in rtl_release_firmware()
2217 void r8169_apply_firmware(struct rtl8169_private *tp)  in r8169_apply_firmware()  argument
2222 	if (tp->rtl_fw) {  in r8169_apply_firmware()
2223 		rtl_fw_write_firmware(tp, tp->rtl_fw);  in r8169_apply_firmware()
2225 		tp->ocp_base = OCP_STD_PHY_BASE;  in r8169_apply_firmware()
2228 		phy_read_poll_timeout(tp->phydev, MII_BMCR, val,  in r8169_apply_firmware()
2234 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)  in rtl8168_config_eee_mac()  argument
2237 	if (tp->mac_version != RTL_GIGA_MAC_VER_38)  in rtl8168_config_eee_mac()
2238 		RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);  in rtl8168_config_eee_mac()
2240 	rtl_eri_set_bits(tp, 0x1b0, 0x0003);  in rtl8168_config_eee_mac()
2243 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)  in rtl8125a_config_eee_mac()  argument
2245 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125a_config_eee_mac()
2246 	r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));  in rtl8125a_config_eee_mac()
2249 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)  in rtl8125_set_eee_txidle_timer()  argument
2251 	RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);  in rtl8125_set_eee_txidle_timer()
2254 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)  in rtl8125b_config_eee_mac()  argument
2256 	rtl8125_set_eee_txidle_timer(tp);  in rtl8125b_config_eee_mac()
2257 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125b_config_eee_mac()
2260 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)  in rtl_rar_exgmac_set()  argument
2262 	rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));  in rtl_rar_exgmac_set()
2263 	rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));  in rtl_rar_exgmac_set()
2264 	rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);  in rtl_rar_exgmac_set()
2265 	rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));  in rtl_rar_exgmac_set()
2268 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)  in rtl8168h_2_get_adc_bias_ioffset()  argument
2272 	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);  in rtl8168h_2_get_adc_bias_ioffset()
2273 	data1 = r8168_mac_ocp_read(tp, 0xdd02);  in rtl8168h_2_get_adc_bias_ioffset()
2274 	data2 = r8168_mac_ocp_read(tp, 0xdd00);  in rtl8168h_2_get_adc_bias_ioffset()
2284 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)  in rtl_schedule_task()  argument
2286 	set_bit(flag, tp->wk.flags);  in rtl_schedule_task()
2287 	schedule_work(&tp->wk.work);  in rtl_schedule_task()
2290 static void rtl8169_init_phy(struct rtl8169_private *tp)  in rtl8169_init_phy()  argument
2292 	r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);  in rtl8169_init_phy()
2294 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {  in rtl8169_init_phy()
2295 		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);  in rtl8169_init_phy()
2296 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);  in rtl8169_init_phy()
2298 		RTL_W8(tp, 0x82, 0x01);  in rtl8169_init_phy()
2301 	if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&  in rtl8169_init_phy()
2302 	    tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&  in rtl8169_init_phy()
2303 	    tp->pci_dev->subsystem_device == 0xe000)  in rtl8169_init_phy()
2304 		phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);  in rtl8169_init_phy()
2307 	phy_speed_up(tp->phydev);  in rtl8169_init_phy()
2309 	if (rtl_supports_eee(tp))  in rtl8169_init_phy()
2310 		rtl_enable_eee(tp);  in rtl8169_init_phy()
2312 	genphy_soft_reset(tp->phydev);  in rtl8169_init_phy()
2315 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)  in rtl_rar_set()  argument
2317 	rtl_unlock_config_regs(tp);  in rtl_rar_set()
2319 	RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));  in rtl_rar_set()
2320 	rtl_pci_commit(tp);  in rtl_rar_set()
2322 	RTL_W32(tp, MAC0, get_unaligned_le32(addr));  in rtl_rar_set()
2323 	rtl_pci_commit(tp);  in rtl_rar_set()
2325 	if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl_rar_set()
2326 		rtl_rar_exgmac_set(tp, addr);  in rtl_rar_set()
2328 	rtl_lock_config_regs(tp);  in rtl_rar_set()
2333 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_mac_address()  local
2340 	rtl_rar_set(tp, dev->dev_addr);  in rtl_set_mac_address()
2345 static void rtl_init_rxcfg(struct rtl8169_private *tp)  in rtl_init_rxcfg()  argument
2347 	switch (tp->mac_version) {  in rtl_init_rxcfg()
2350 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);  in rtl_init_rxcfg()
2355 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2358 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
2361 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);  in rtl_init_rxcfg()
2364 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |  in rtl_init_rxcfg()
2368 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2373 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)  in rtl8169_init_ring_indexes()  argument
2375 	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;  in rtl8169_init_ring_indexes()
2378 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_enable()  argument
2380 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168c_hw_jumbo_enable()
2381 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);  in r8168c_hw_jumbo_enable()
2384 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_disable()  argument
2386 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168c_hw_jumbo_disable()
2387 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);  in r8168c_hw_jumbo_disable()
2390 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_enable()  argument
2392 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168dp_hw_jumbo_enable()
2395 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_disable()  argument
2397 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168dp_hw_jumbo_disable()
2400 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_enable()  argument
2402 	RTL_W8(tp, MaxTxPacketSize, 0x24);  in r8168e_hw_jumbo_enable()
2403 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168e_hw_jumbo_enable()
2404 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);  in r8168e_hw_jumbo_enable()
2407 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_disable()  argument
2409 	RTL_W8(tp, MaxTxPacketSize, 0x3f);  in r8168e_hw_jumbo_disable()
2410 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168e_hw_jumbo_disable()
2411 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);  in r8168e_hw_jumbo_disable()
2414 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_enable()  argument
2416 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));  in r8168b_1_hw_jumbo_enable()
2419 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_disable()  argument
2421 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));  in r8168b_1_hw_jumbo_disable()
2424 static void rtl_jumbo_config(struct rtl8169_private *tp)  in rtl_jumbo_config()  argument
2426 	bool jumbo = tp->dev->mtu > ETH_DATA_LEN;  in rtl_jumbo_config()
2429 	rtl_unlock_config_regs(tp);  in rtl_jumbo_config()
2430 	switch (tp->mac_version) {  in rtl_jumbo_config()
2434 			r8168b_1_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2436 			r8168b_1_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2442 			r8168c_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2444 			r8168c_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2449 			r8168dp_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2451 			r8168dp_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2455 			r8168e_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2457 			r8168e_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2462 	rtl_lock_config_regs(tp);  in rtl_jumbo_config()
2464 	if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)  in rtl_jumbo_config()
2465 		pcie_set_readrq(tp->pci_dev, readrq);  in rtl_jumbo_config()
2470 				   tp->phydev->advertising);  in rtl_jumbo_config()
2472 				   tp->phydev->advertising);  in rtl_jumbo_config()
2473 		phy_start_aneg(tp->phydev);  in rtl_jumbo_config()
2479 	return RTL_R8(tp, ChipCmd) & CmdReset;  in DECLARE_RTL_COND()
2482 static void rtl_hw_reset(struct rtl8169_private *tp)  in rtl_hw_reset()  argument
2484 	RTL_W8(tp, ChipCmd, CmdReset);  in rtl_hw_reset()
2486 	rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);  in rtl_hw_reset()
2489 static void rtl_request_firmware(struct rtl8169_private *tp)  in rtl_request_firmware()  argument
2494 	if (tp->rtl_fw || !tp->fw_name)  in rtl_request_firmware()
2505 	rtl_fw->fw_name = tp->fw_name;  in rtl_request_firmware()
2506 	rtl_fw->dev = tp_to_dev(tp);  in rtl_request_firmware()
2511 		tp->rtl_fw = rtl_fw;  in rtl_request_firmware()
2514 static void rtl_rx_close(struct rtl8169_private *tp)  in rtl_rx_close()  argument
2516 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
2521 	return RTL_R8(tp, TxPoll) & NPQ;  in DECLARE_RTL_COND()
2526 	return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;  in DECLARE_RTL_COND()
2531 	return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;  in DECLARE_RTL_COND()
2537 	return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;  in DECLARE_RTL_COND()
2540 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)  in rtl_wait_txrx_fifo_empty()  argument
2542 	switch (tp->mac_version) {  in rtl_wait_txrx_fifo_empty()
2544 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2545 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2548 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2551 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl_wait_txrx_fifo_empty()
2552 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2553 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);  in rtl_wait_txrx_fifo_empty()
2560 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)  in rtl_disable_rxdvgate()  argument
2562 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_disable_rxdvgate()
2565 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)  in rtl_enable_rxdvgate()  argument
2567 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);  in rtl_enable_rxdvgate()
2569 	rtl_wait_txrx_fifo_empty(tp);  in rtl_enable_rxdvgate()
2572 static void rtl_wol_enable_rx(struct rtl8169_private *tp)  in rtl_wol_enable_rx()  argument
2574 	if (tp->mac_version >= RTL_GIGA_MAC_VER_25)  in rtl_wol_enable_rx()
2575 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |  in rtl_wol_enable_rx()
2578 	if (tp->mac_version >= RTL_GIGA_MAC_VER_40)  in rtl_wol_enable_rx()
2579 		rtl_disable_rxdvgate(tp);  in rtl_wol_enable_rx()
2582 static void rtl_prepare_power_down(struct rtl8169_private *tp)  in rtl_prepare_power_down()  argument
2584 	if (tp->dash_enabled)  in rtl_prepare_power_down()
2587 	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||  in rtl_prepare_power_down()
2588 	    tp->mac_version == RTL_GIGA_MAC_VER_33)  in rtl_prepare_power_down()
2589 		rtl_ephy_write(tp, 0x19, 0xff64);  in rtl_prepare_power_down()
2591 	if (device_may_wakeup(tp_to_dev(tp))) {  in rtl_prepare_power_down()
2592 		phy_speed_down(tp->phydev, false);  in rtl_prepare_power_down()
2593 		rtl_wol_enable_rx(tp);  in rtl_prepare_power_down()
2597 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)  in rtl_set_tx_config_registers()  argument
2602 	if (rtl_is_8168evl_up(tp))  in rtl_set_tx_config_registers()
2605 	RTL_W32(tp, TxConfig, val);  in rtl_set_tx_config_registers()
2608 static void rtl_set_rx_max_size(struct rtl8169_private *tp)  in rtl_set_rx_max_size()  argument
2611 	RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);  in rtl_set_rx_max_size()
2614 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)  in rtl_set_rx_tx_desc_registers()  argument
2621 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2622 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2623 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2624 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2627 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)  in rtl8169_set_magic_reg()  argument
2631 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl8169_set_magic_reg()
2633 	else if (tp->mac_version == RTL_GIGA_MAC_VER_06)  in rtl8169_set_magic_reg()
2638 	if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)  in rtl8169_set_magic_reg()
2641 	RTL_W32(tp, 0x7c, val);  in rtl8169_set_magic_reg()
2649 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_rx_mode()  local
2658 		   tp->mac_version == RTL_GIGA_MAC_VER_35) {  in rtl_set_rx_mode()
2671 		if (tp->mac_version > RTL_GIGA_MAC_VER_06) {  in rtl_set_rx_mode()
2678 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);  in rtl_set_rx_mode()
2679 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);  in rtl_set_rx_mode()
2681 	tmp = RTL_R32(tp, RxConfig);  in rtl_set_rx_mode()
2682 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);  in rtl_set_rx_mode()
2687 	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;  in DECLARE_RTL_COND()
2690 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)  in rtl_csi_write()  argument
2692 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_write()
2694 	RTL_W32(tp, CSIDR, value);  in rtl_csi_write()
2695 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in rtl_csi_write()
2698 	rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);  in rtl_csi_write()
2701 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)  in rtl_csi_read()  argument
2703 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_read()
2705 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |  in rtl_csi_read()
2708 	return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?  in rtl_csi_read()
2709 		RTL_R32(tp, CSIDR) : ~0;  in rtl_csi_read()
2712 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)  in rtl_set_aspm_entry_latency()  argument
2714 	struct pci_dev *pdev = tp->pci_dev;  in rtl_set_aspm_entry_latency()
2727 	netdev_notice_once(tp->dev,  in rtl_set_aspm_entry_latency()
2729 	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;  in rtl_set_aspm_entry_latency()
2730 	rtl_csi_write(tp, 0x070c, csi | val << 24);  in rtl_set_aspm_entry_latency()
2733 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)  in rtl_set_def_aspm_entry_latency()  argument
2736 	rtl_set_aspm_entry_latency(tp, 0x27);  in rtl_set_def_aspm_entry_latency()
2745 static void __rtl_ephy_init(struct rtl8169_private *tp,  in __rtl_ephy_init()  argument
2751 		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;  in __rtl_ephy_init()
2752 		rtl_ephy_write(tp, e->offset, w);  in __rtl_ephy_init()
2757 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))  argument
2759 static void rtl_disable_clock_request(struct rtl8169_private *tp)  in rtl_disable_clock_request()  argument
2761 	pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_disable_clock_request()
2765 static void rtl_enable_clock_request(struct rtl8169_private *tp)  in rtl_enable_clock_request()  argument
2767 	pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_enable_clock_request()
2771 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)  in rtl_pcie_state_l2l3_disable()  argument
2774 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);  in rtl_pcie_state_l2l3_disable()
2777 static void rtl_enable_exit_l1(struct rtl8169_private *tp)  in rtl_enable_exit_l1()  argument
2787 	switch (tp->mac_version) {  in rtl_enable_exit_l1()
2789 		rtl_eri_set_bits(tp, 0xd4, 0x1f00);  in rtl_enable_exit_l1()
2792 		rtl_eri_set_bits(tp, 0xd4, 0x0c00);  in rtl_enable_exit_l1()
2795 		r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);  in rtl_enable_exit_l1()
2802 static void rtl_disable_exit_l1(struct rtl8169_private *tp)  in rtl_disable_exit_l1()  argument
2804 	switch (tp->mac_version) {  in rtl_disable_exit_l1()
2806 		rtl_eri_clear_bits(tp, 0xd4, 0x1f00);  in rtl_disable_exit_l1()
2809 		r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);  in rtl_disable_exit_l1()
2816 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)  in rtl_hw_aspm_clkreq_enable()  argument
2818 	if (tp->mac_version < RTL_GIGA_MAC_VER_32)  in rtl_hw_aspm_clkreq_enable()
2822 	if (enable && tp->aspm_manageable) {  in rtl_hw_aspm_clkreq_enable()
2826 		if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||  in rtl_hw_aspm_clkreq_enable()
2827 		    tp->mac_version == RTL_GIGA_MAC_VER_43)  in rtl_hw_aspm_clkreq_enable()
2830 		rtl_mod_config5(tp, 0, ASPM_en);  in rtl_hw_aspm_clkreq_enable()
2831 		rtl_mod_config2(tp, 0, ClkReqEn);  in rtl_hw_aspm_clkreq_enable()
2833 		switch (tp->mac_version) {  in rtl_hw_aspm_clkreq_enable()
2837 			r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);  in rtl_hw_aspm_clkreq_enable()
2839 			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));  in rtl_hw_aspm_clkreq_enable()
2845 		switch (tp->mac_version) {  in rtl_hw_aspm_clkreq_enable()
2848 			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);  in rtl_hw_aspm_clkreq_enable()
2854 		rtl_mod_config2(tp, ClkReqEn, 0);  in rtl_hw_aspm_clkreq_enable()
2855 		rtl_mod_config5(tp, ASPM_en, 0);  in rtl_hw_aspm_clkreq_enable()
2859 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,  in rtl_set_fifo_size()  argument
2865 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);  in rtl_set_fifo_size()
2866 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);  in rtl_set_fifo_size()
2869 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,  in rtl8168g_set_pause_thresholds()  argument
2873 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);  in rtl8168g_set_pause_thresholds()
2874 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);  in rtl8168g_set_pause_thresholds()
2877 static void rtl_hw_start_8168b(struct rtl8169_private *tp)  in rtl_hw_start_8168b()  argument
2879 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168b()
2882 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)  in __rtl_hw_start_8168cp()  argument
2884 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);  in __rtl_hw_start_8168cp()
2886 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in __rtl_hw_start_8168cp()
2888 	rtl_disable_clock_request(tp);  in __rtl_hw_start_8168cp()
2891 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_1()  argument
2901 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_1()
2903 	rtl_ephy_init(tp, e_info_8168cp);  in rtl_hw_start_8168cp_1()
2905 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168cp_1()
2908 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_2()  argument
2910 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_2()
2912 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_2()
2915 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_3()  argument
2917 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_3()
2919 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_3()
2922 	RTL_W8(tp, DBG_REG, 0x20);  in rtl_hw_start_8168cp_3()
2925 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)  in rtl_hw_start_8168c_1()  argument
2933 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_1()
2935 	RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);  in rtl_hw_start_8168c_1()
2937 	rtl_ephy_init(tp, e_info_8168c_1);  in rtl_hw_start_8168c_1()
2939 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_1()
2942 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)  in rtl_hw_start_8168c_2()  argument
2949 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_2()
2951 	rtl_ephy_init(tp, e_info_8168c_2);  in rtl_hw_start_8168c_2()
2953 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_2()
2956 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)  in rtl_hw_start_8168c_4()  argument
2958 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_4()
2960 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_4()
2963 static void rtl_hw_start_8168d(struct rtl8169_private *tp)  in rtl_hw_start_8168d()  argument
2965 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d()
2967 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168d()
2970 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)  in rtl_hw_start_8168d_4()  argument
2979 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d_4()
2981 	rtl_ephy_init(tp, e_info_8168d_4);  in rtl_hw_start_8168d_4()
2983 	rtl_enable_clock_request(tp);  in rtl_hw_start_8168d_4()
2986 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)  in rtl_hw_start_8168e_1()  argument
3004 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_1()
3006 	rtl_ephy_init(tp, e_info_8168e_1);  in rtl_hw_start_8168e_1()
3008 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_1()
3011 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
3012 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
3014 	rtl_mod_config5(tp, Spi_en, 0);  in rtl_hw_start_8168e_1()
3017 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)  in rtl_hw_start_8168e_2()  argument
3026 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_2()
3028 	rtl_ephy_init(tp, e_info_8168e_2);  in rtl_hw_start_8168e_2()
3030 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168e_2()
3031 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168e_2()
3032 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168e_2()
3033 	rtl_eri_set_bits(tp, 0x1d0, BIT(1));  in rtl_hw_start_8168e_2()
3034 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168e_2()
3035 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168e_2()
3036 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168e_2()
3037 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);  in rtl_hw_start_8168e_2()
3039 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_2()
3041 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168e_2()
3043 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168e_2()
3045 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168e_2()
3046 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
3047 	rtl_mod_config5(tp, Spi_en, 0);  in rtl_hw_start_8168e_2()
3050 static void rtl_hw_start_8168f(struct rtl8169_private *tp)  in rtl_hw_start_8168f()  argument
3052 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168f()
3054 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168f()
3055 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168f()
3056 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168f()
3057 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168f()
3058 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168f()
3059 	rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));  in rtl_hw_start_8168f()
3060 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168f()
3061 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);  in rtl_hw_start_8168f()
3063 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168f()
3065 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168f()
3066 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168f()
3067 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168f()
3068 	rtl_mod_config5(tp, Spi_en, 0);  in rtl_hw_start_8168f()
3070 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168f()
3073 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)  in rtl_hw_start_8168f_1()  argument
3084 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8168f_1()
3086 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8168f_1()
3089 static void rtl_hw_start_8411(struct rtl8169_private *tp)  in rtl_hw_start_8411()  argument
3099 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8411()
3100 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8411()
3102 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8411()
3105 static void rtl_hw_start_8168g(struct rtl8169_private *tp)  in rtl_hw_start_8168g()  argument
3107 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168g()
3108 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168g()
3110 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168g()
3112 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168g()
3113 	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);  in rtl_hw_start_8168g()
3115 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8168g()
3117 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
3118 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
3120 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168g()
3122 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168g()
3123 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168g()
3125 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168g()
3128 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)  in rtl_hw_start_8168g_1()  argument
3137 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_1()
3138 	rtl_ephy_init(tp, e_info_8168g_1);  in rtl_hw_start_8168g_1()
3141 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)  in rtl_hw_start_8168g_2()  argument
3155 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_2()
3156 	rtl_ephy_init(tp, e_info_8168g_2);  in rtl_hw_start_8168g_2()
3159 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)  in rtl_hw_start_8411_2()  argument
3174 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8411_2()
3176 	rtl_ephy_init(tp, e_info_8411_2);  in rtl_hw_start_8411_2()
3181 	r8168_mac_ocp_write(tp, 0xFC28, 0x0000);  in rtl_hw_start_8411_2()
3182 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);  in rtl_hw_start_8411_2()
3183 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);  in rtl_hw_start_8411_2()
3184 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);  in rtl_hw_start_8411_2()
3185 	r8168_mac_ocp_write(tp, 0xFC30, 0x0000);  in rtl_hw_start_8411_2()
3186 	r8168_mac_ocp_write(tp, 0xFC32, 0x0000);  in rtl_hw_start_8411_2()
3187 	r8168_mac_ocp_write(tp, 0xFC34, 0x0000);  in rtl_hw_start_8411_2()
3188 	r8168_mac_ocp_write(tp, 0xFC36, 0x0000);  in rtl_hw_start_8411_2()
3190 	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);  in rtl_hw_start_8411_2()
3192 	r8168_mac_ocp_write(tp, 0xF800, 0xE008);  in rtl_hw_start_8411_2()
3193 	r8168_mac_ocp_write(tp, 0xF802, 0xE00A);  in rtl_hw_start_8411_2()
3194 	r8168_mac_ocp_write(tp, 0xF804, 0xE00C);  in rtl_hw_start_8411_2()
3195 	r8168_mac_ocp_write(tp, 0xF806, 0xE00E);  in rtl_hw_start_8411_2()
3196 	r8168_mac_ocp_write(tp, 0xF808, 0xE027);  in rtl_hw_start_8411_2()
3197 	r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);  in rtl_hw_start_8411_2()
3198 	r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);  in rtl_hw_start_8411_2()
3199 	r8168_mac_ocp_write(tp, 0xF80E, 0xE065);  in rtl_hw_start_8411_2()
3200 	r8168_mac_ocp_write(tp, 0xF810, 0xC602);  in rtl_hw_start_8411_2()
3201 	r8168_mac_ocp_write(tp, 0xF812, 0xBE00);  in rtl_hw_start_8411_2()
3202 	r8168_mac_ocp_write(tp, 0xF814, 0x0000);  in rtl_hw_start_8411_2()
3203 	r8168_mac_ocp_write(tp, 0xF816, 0xC502);  in rtl_hw_start_8411_2()
3204 	r8168_mac_ocp_write(tp, 0xF818, 0xBD00);  in rtl_hw_start_8411_2()
3205 	r8168_mac_ocp_write(tp, 0xF81A, 0x074C);  in rtl_hw_start_8411_2()
3206 	r8168_mac_ocp_write(tp, 0xF81C, 0xC302);  in rtl_hw_start_8411_2()
3207 	r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);  in rtl_hw_start_8411_2()
3208 	r8168_mac_ocp_write(tp, 0xF820, 0x080A);  in rtl_hw_start_8411_2()
3209 	r8168_mac_ocp_write(tp, 0xF822, 0x6420);  in rtl_hw_start_8411_2()
3210 	r8168_mac_ocp_write(tp, 0xF824, 0x48C2);  in rtl_hw_start_8411_2()
3211 	r8168_mac_ocp_write(tp, 0xF826, 0x8C20);  in rtl_hw_start_8411_2()
3212 	r8168_mac_ocp_write(tp, 0xF828, 0xC516);  in rtl_hw_start_8411_2()
3213 	r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);  in rtl_hw_start_8411_2()
3214 	r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);  in rtl_hw_start_8411_2()
3215 	r8168_mac_ocp_write(tp, 0xF82E, 0xF009);  in rtl_hw_start_8411_2()
3216 	r8168_mac_ocp_write(tp, 0xF830, 0x74A2);  in rtl_hw_start_8411_2()
3217 	r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);  in rtl_hw_start_8411_2()
3218 	r8168_mac_ocp_write(tp, 0xF834, 0x74A0);  in rtl_hw_start_8411_2()
3219 	r8168_mac_ocp_write(tp, 0xF836, 0xC50E);  in rtl_hw_start_8411_2()
3220 	r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);  in rtl_hw_start_8411_2()
3221 	r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);  in rtl_hw_start_8411_2()
3222 	r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);  in rtl_hw_start_8411_2()
3223 	r8168_mac_ocp_write(tp, 0xF83E, 0xE006);  in rtl_hw_start_8411_2()
3224 	r8168_mac_ocp_write(tp, 0xF840, 0x74F8);  in rtl_hw_start_8411_2()
3225 	r8168_mac_ocp_write(tp, 0xF842, 0x48C4);  in rtl_hw_start_8411_2()
3226 	r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);  in rtl_hw_start_8411_2()
3227 	r8168_mac_ocp_write(tp, 0xF846, 0xC404);  in rtl_hw_start_8411_2()
3228 	r8168_mac_ocp_write(tp, 0xF848, 0xBC00);  in rtl_hw_start_8411_2()
3229 	r8168_mac_ocp_write(tp, 0xF84A, 0xC403);  in rtl_hw_start_8411_2()
3230 	r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);  in rtl_hw_start_8411_2()
3231 	r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);  in rtl_hw_start_8411_2()
3232 	r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);  in rtl_hw_start_8411_2()
3233 	r8168_mac_ocp_write(tp, 0xF852, 0xE434);  in rtl_hw_start_8411_2()
3234 	r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);  in rtl_hw_start_8411_2()
3235 	r8168_mac_ocp_write(tp, 0xF856, 0x49D9);  in rtl_hw_start_8411_2()
3236 	r8168_mac_ocp_write(tp, 0xF858, 0xF01F);  in rtl_hw_start_8411_2()
3237 	r8168_mac_ocp_write(tp, 0xF85A, 0xC526);  in rtl_hw_start_8411_2()
3238 	r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);  in rtl_hw_start_8411_2()
3239 	r8168_mac_ocp_write(tp, 0xF85E, 0x1400);  in rtl_hw_start_8411_2()
3240 	r8168_mac_ocp_write(tp, 0xF860, 0xF007);  in rtl_hw_start_8411_2()
3241 	r8168_mac_ocp_write(tp, 0xF862, 0x0C01);  in rtl_hw_start_8411_2()
3242 	r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);  in rtl_hw_start_8411_2()
3243 	r8168_mac_ocp_write(tp, 0xF866, 0x1C15);  in rtl_hw_start_8411_2()
3244 	r8168_mac_ocp_write(tp, 0xF868, 0xC51B);  in rtl_hw_start_8411_2()
3245 	r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);  in rtl_hw_start_8411_2()
3246 	r8168_mac_ocp_write(tp, 0xF86C, 0xE013);  in rtl_hw_start_8411_2()
3247 	r8168_mac_ocp_write(tp, 0xF86E, 0xC519);  in rtl_hw_start_8411_2()
3248 	r8168_mac_ocp_write(tp, 0xF870, 0x74A0);  in rtl_hw_start_8411_2()
3249 	r8168_mac_ocp_write(tp, 0xF872, 0x48C4);  in rtl_hw_start_8411_2()
3250 	r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);  in rtl_hw_start_8411_2()
3251 	r8168_mac_ocp_write(tp, 0xF876, 0xC516);  in rtl_hw_start_8411_2()
3252 	r8168_mac_ocp_write(tp, 0xF878, 0x74A4);  in rtl_hw_start_8411_2()
3253 	r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);  in rtl_hw_start_8411_2()
3254 	r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);  in rtl_hw_start_8411_2()
3255 	r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);  in rtl_hw_start_8411_2()
3256 	r8168_mac_ocp_write(tp, 0xF880, 0xC512);  in rtl_hw_start_8411_2()
3257 	r8168_mac_ocp_write(tp, 0xF882, 0x1B00);  in rtl_hw_start_8411_2()
3258 	r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);  in rtl_hw_start_8411_2()
3259 	r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);  in rtl_hw_start_8411_2()
3260 	r8168_mac_ocp_write(tp, 0xF888, 0x483F);  in rtl_hw_start_8411_2()
3261 	r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);  in rtl_hw_start_8411_2()
3262 	r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);  in rtl_hw_start_8411_2()
3263 	r8168_mac_ocp_write(tp, 0xF88E, 0xC508);  in rtl_hw_start_8411_2()
3264 	r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);  in rtl_hw_start_8411_2()
3265 	r8168_mac_ocp_write(tp, 0xF892, 0xC505);  in rtl_hw_start_8411_2()
3266 	r8168_mac_ocp_write(tp, 0xF894, 0xBD00);  in rtl_hw_start_8411_2()
3267 	r8168_mac_ocp_write(tp, 0xF896, 0xC502);  in rtl_hw_start_8411_2()
3268 	r8168_mac_ocp_write(tp, 0xF898, 0xBD00);  in rtl_hw_start_8411_2()
3269 	r8168_mac_ocp_write(tp, 0xF89A, 0x0300);  in rtl_hw_start_8411_2()
3270 	r8168_mac_ocp_write(tp, 0xF89C, 0x051E);  in rtl_hw_start_8411_2()
3271 	r8168_mac_ocp_write(tp, 0xF89E, 0xE434);  in rtl_hw_start_8411_2()
3272 	r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);  in rtl_hw_start_8411_2()
3273 	r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);  in rtl_hw_start_8411_2()
3274 	r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);  in rtl_hw_start_8411_2()
3275 	r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);  in rtl_hw_start_8411_2()
3276 	r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);  in rtl_hw_start_8411_2()
3277 	r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);  in rtl_hw_start_8411_2()
3278 	r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);  in rtl_hw_start_8411_2()
3279 	r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);  in rtl_hw_start_8411_2()
3280 	r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);  in rtl_hw_start_8411_2()
3281 	r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);  in rtl_hw_start_8411_2()
3282 	r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);  in rtl_hw_start_8411_2()
3283 	r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);  in rtl_hw_start_8411_2()
3284 	r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);  in rtl_hw_start_8411_2()
3285 	r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);  in rtl_hw_start_8411_2()
3286 	r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);  in rtl_hw_start_8411_2()
3287 	r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);  in rtl_hw_start_8411_2()
3288 	r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);  in rtl_hw_start_8411_2()
3289 	r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);  in rtl_hw_start_8411_2()
3290 	r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);  in rtl_hw_start_8411_2()
3291 	r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);  in rtl_hw_start_8411_2()
3292 	r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);  in rtl_hw_start_8411_2()
3293 	r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);  in rtl_hw_start_8411_2()
3294 	r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);  in rtl_hw_start_8411_2()
3295 	r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);  in rtl_hw_start_8411_2()
3296 	r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);  in rtl_hw_start_8411_2()
3297 	r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);  in rtl_hw_start_8411_2()
3298 	r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);  in rtl_hw_start_8411_2()
3299 	r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);  in rtl_hw_start_8411_2()
3300 	r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);  in rtl_hw_start_8411_2()
3301 	r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);  in rtl_hw_start_8411_2()
3302 	r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);  in rtl_hw_start_8411_2()
3304 	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);  in rtl_hw_start_8411_2()
3306 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);  in rtl_hw_start_8411_2()
3307 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);  in rtl_hw_start_8411_2()
3308 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);  in rtl_hw_start_8411_2()
3309 	r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);  in rtl_hw_start_8411_2()
3310 	r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);  in rtl_hw_start_8411_2()
3311 	r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);  in rtl_hw_start_8411_2()
3312 	r8168_mac_ocp_write(tp, 0xFC36, 0x012D);  in rtl_hw_start_8411_2()
3315 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)  in rtl_hw_start_8168h_1()  argument
3327 	rtl_ephy_init(tp, e_info_8168h_1);  in rtl_hw_start_8168h_1()
3329 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168h_1()
3330 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168h_1()
3332 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168h_1()
3334 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168h_1()
3336 	rtl_eri_set_bits(tp, 0xdc, 0x001c);  in rtl_hw_start_8168h_1()
3338 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168h_1()
3340 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8168h_1()
3342 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3343 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3345 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168h_1()
3347 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168h_1()
3348 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168h_1()
3350 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168h_1()
3352 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168h_1()
3354 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168h_1()
3356 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8168h_1()
3362 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8168h_1()
3365 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8168h_1()
3366 	r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);  in rtl_hw_start_8168h_1()
3367 	r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);  in rtl_hw_start_8168h_1()
3368 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8168h_1()
3370 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8168h_1()
3371 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8168h_1()
3372 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8168h_1()
3373 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8168h_1()
3376 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)  in rtl_hw_start_8168ep()  argument
3378 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8168ep()
3380 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168ep()
3381 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8168ep()
3383 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168ep()
3385 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168ep()
3387 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168ep()
3389 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8168ep()
3391 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3392 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3394 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168ep()
3396 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168ep()
3398 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168ep()
3400 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168ep()
3403 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_3()  argument
3412 	rtl_ephy_init(tp, e_info_8168ep_3);  in rtl_hw_start_8168ep_3()
3414 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_3()
3416 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168ep_3()
3417 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168ep_3()
3419 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);  in rtl_hw_start_8168ep_3()
3420 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8168ep_3()
3421 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8168ep_3()
3424 static void rtl_hw_start_8117(struct rtl8169_private *tp)  in rtl_hw_start_8117()  argument
3432 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8117()
3433 	rtl_ephy_init(tp, e_info_8117);  in rtl_hw_start_8117()
3435 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8117()
3436 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8117()
3438 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8117()
3440 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8117()
3442 	rtl_eri_set_bits(tp, 0xd4, 0x0010);  in rtl_hw_start_8117()
3444 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8117()
3446 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8117()
3448 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3449 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3451 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8117()
3453 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8117()
3454 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8117()
3456 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8117()
3458 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8117()
3460 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8117()
3462 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8117()
3467 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8117()
3470 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8117()
3471 	r8168_mac_ocp_write(tp, 0xea80, 0x0003);  in rtl_hw_start_8117()
3472 	r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);  in rtl_hw_start_8117()
3473 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8117()
3475 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8117()
3476 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8117()
3477 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8117()
3478 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8117()
3481 	r8169_apply_firmware(tp);  in rtl_hw_start_8117()
3484 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)  in rtl_hw_start_8102e_1()  argument
3498 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_1()
3500 	RTL_W8(tp, DBG_REG, FIX_NAK_1);  in rtl_hw_start_8102e_1()
3502 	RTL_W8(tp, Config1,  in rtl_hw_start_8102e_1()
3504 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_1()
3506 	cfg1 = RTL_R8(tp, Config1);  in rtl_hw_start_8102e_1()
3508 		RTL_W8(tp, Config1, cfg1 & ~LEDS0);  in rtl_hw_start_8102e_1()
3510 	rtl_ephy_init(tp, e_info_8102e_1);  in rtl_hw_start_8102e_1()
3513 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)  in rtl_hw_start_8102e_2()  argument
3515 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_2()
3517 	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);  in rtl_hw_start_8102e_2()
3518 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_2()
3521 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)  in rtl_hw_start_8102e_3()  argument
3523 	rtl_hw_start_8102e_2(tp);  in rtl_hw_start_8102e_3()
3525 	rtl_ephy_write(tp, 0x03, 0xc2f9);  in rtl_hw_start_8102e_3()
3528 static void rtl_hw_start_8401(struct rtl8169_private *tp)  in rtl_hw_start_8401()  argument
3537 	rtl_ephy_init(tp, e_info_8401);  in rtl_hw_start_8401()
3538 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8401()
3541 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)  in rtl_hw_start_8105e_1()  argument
3555 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
3558 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
3560 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8105e_1()
3561 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8105e_1()
3563 	rtl_ephy_init(tp, e_info_8105e_1);  in rtl_hw_start_8105e_1()
3565 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8105e_1()
3568 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)  in rtl_hw_start_8105e_2()  argument
3570 	rtl_hw_start_8105e_1(tp);  in rtl_hw_start_8105e_2()
3571 	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);  in rtl_hw_start_8105e_2()
3574 static void rtl_hw_start_8402(struct rtl8169_private *tp)  in rtl_hw_start_8402()  argument
3581 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8402()
3584 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8402()
3586 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8402()
3588 	rtl_ephy_init(tp, e_info_8402);  in rtl_hw_start_8402()
3590 	rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);  in rtl_hw_start_8402()
3591 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8402()
3592 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3593 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3594 	rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);  in rtl_hw_start_8402()
3597 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3599 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8402()
3602 static void rtl_hw_start_8106(struct rtl8169_private *tp)  in rtl_hw_start_8106()  argument
3605 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8106()
3607 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
3608 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8106()
3609 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8106()
3612 	rtl_set_aspm_entry_latency(tp, 0x2f);  in rtl_hw_start_8106()
3614 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3617 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3619 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8106()
3624 	return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);  in DECLARE_RTL_COND()
3627 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)  in rtl_hw_start_8125_common()  argument
3629 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8125_common()
3631 	RTL_W16(tp, 0x382, 0x221b);  in rtl_hw_start_8125_common()
3632 	RTL_W8(tp, 0x4500, 0);  in rtl_hw_start_8125_common()
3633 	RTL_W16(tp, 0x4800, 0);  in rtl_hw_start_8125_common()
3636 	r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);  in rtl_hw_start_8125_common()
3638 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);  in rtl_hw_start_8125_common()
3640 	r8168_mac_ocp_write(tp, 0xc140, 0xffff);  in rtl_hw_start_8125_common()
3641 	r8168_mac_ocp_write(tp, 0xc142, 0xffff);  in rtl_hw_start_8125_common()
3643 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);  in rtl_hw_start_8125_common()
3644 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8125_common()
3645 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8125_common()
3648 	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3650 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3651 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);  in rtl_hw_start_8125_common()
3653 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);  in rtl_hw_start_8125_common()
3655 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3656 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);  in rtl_hw_start_8125_common()
3658 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);  in rtl_hw_start_8125_common()
3660 	r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);  in rtl_hw_start_8125_common()
3661 	r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);  in rtl_hw_start_8125_common()
3662 	r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);  in rtl_hw_start_8125_common()
3663 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);  in rtl_hw_start_8125_common()
3664 	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);  in rtl_hw_start_8125_common()
3665 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);  in rtl_hw_start_8125_common()
3666 	r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);  in rtl_hw_start_8125_common()
3667 	r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);  in rtl_hw_start_8125_common()
3668 	r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);  in rtl_hw_start_8125_common()
3670 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);  in rtl_hw_start_8125_common()
3671 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);  in rtl_hw_start_8125_common()
3673 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3674 	RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);  in rtl_hw_start_8125_common()
3676 	r8168_mac_ocp_write(tp, 0xe098, 0xc302);  in rtl_hw_start_8125_common()
3678 	rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);  in rtl_hw_start_8125_common()
3680 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3681 		rtl8125b_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3683 		rtl8125a_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3685 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8125_common()
3688 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)  in rtl_hw_start_8125a_2()  argument
3706 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125a_2()
3707 	rtl_ephy_init(tp, e_info_8125a_2);  in rtl_hw_start_8125a_2()
3708 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125a_2()
3711 static void rtl_hw_start_8125b(struct rtl8169_private *tp)  in rtl_hw_start_8125b()  argument
3722 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125b()
3723 	rtl_ephy_init(tp, e_info_8125b);  in rtl_hw_start_8125b()
3724 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125b()
3727 static void rtl_hw_config(struct rtl8169_private *tp)  in rtl_hw_config()  argument
3771 	if (hw_configs[tp->mac_version])  in rtl_hw_config()
3772 		hw_configs[tp->mac_version](tp);  in rtl_hw_config()
3775 static void rtl_hw_start_8125(struct rtl8169_private *tp)  in rtl_hw_start_8125()  argument
3781 		RTL_W32(tp, i, 0);  in rtl_hw_start_8125()
3783 	rtl_hw_config(tp);  in rtl_hw_start_8125()
3786 static void rtl_hw_start_8168(struct rtl8169_private *tp)  in rtl_hw_start_8168()  argument
3788 	if (rtl_is_8168evl_up(tp))  in rtl_hw_start_8168()
3789 		RTL_W8(tp, MaxTxPacketSize, EarlySize);  in rtl_hw_start_8168()
3791 		RTL_W8(tp, MaxTxPacketSize, TxPacketMax);  in rtl_hw_start_8168()
3793 	rtl_hw_config(tp);  in rtl_hw_start_8168()
3796 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8168()
3799 static void rtl_hw_start_8169(struct rtl8169_private *tp)  in rtl_hw_start_8169()  argument
3801 	RTL_W8(tp, EarlyTxThres, NoEarlyTx);  in rtl_hw_start_8169()
3803 	tp->cp_cmd |= PCIMulRW;  in rtl_hw_start_8169()
3805 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||  in rtl_hw_start_8169()
3806 	    tp->mac_version == RTL_GIGA_MAC_VER_03)  in rtl_hw_start_8169()
3807 		tp->cp_cmd |= EnAnaPLL;  in rtl_hw_start_8169()
3809 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start_8169()
3811 	rtl8169_set_magic_reg(tp);  in rtl_hw_start_8169()
3814 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8169()
3817 static void rtl_hw_start(struct  rtl8169_private *tp)  in rtl_hw_start()  argument
3819 	rtl_unlock_config_regs(tp);  in rtl_hw_start()
3821 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start()
3822 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start()
3824 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_hw_start()
3825 		rtl_hw_start_8169(tp);  in rtl_hw_start()
3826 	else if (rtl_is_8125(tp))  in rtl_hw_start()
3827 		rtl_hw_start_8125(tp);  in rtl_hw_start()
3829 		rtl_hw_start_8168(tp);  in rtl_hw_start()
3831 	rtl_enable_exit_l1(tp);  in rtl_hw_start()
3832 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start()
3833 	rtl_set_rx_max_size(tp);  in rtl_hw_start()
3834 	rtl_set_rx_tx_desc_registers(tp);  in rtl_hw_start()
3835 	rtl_lock_config_regs(tp);  in rtl_hw_start()
3837 	rtl_jumbo_config(tp);  in rtl_hw_start()
3840 	rtl_pci_commit(tp);  in rtl_hw_start()
3842 	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);  in rtl_hw_start()
3843 	rtl_init_rxcfg(tp);  in rtl_hw_start()
3844 	rtl_set_tx_config_registers(tp);  in rtl_hw_start()
3845 	rtl_set_rx_config_features(tp, tp->dev->features);  in rtl_hw_start()
3846 	rtl_set_rx_mode(tp->dev);  in rtl_hw_start()
3847 	rtl_irq_enable(tp);  in rtl_hw_start()
3852 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_change_mtu()  local
3856 	rtl_jumbo_config(tp);  in rtl8169_change_mtu()
3858 	switch (tp->mac_version) {  in rtl8169_change_mtu()
3861 		rtl8125_set_eee_txidle_timer(tp);  in rtl8169_change_mtu()
3880 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,  in rtl8169_alloc_rx_data()  argument
3883 	struct device *d = tp_to_dev(tp);  in rtl8169_alloc_rx_data()
3894 		netdev_err(tp->dev, "Failed to map RX DMA!\n");  in rtl8169_alloc_rx_data()
3905 static void rtl8169_rx_clear(struct rtl8169_private *tp)  in rtl8169_rx_clear()  argument
3909 	for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {  in rtl8169_rx_clear()
3910 		dma_unmap_page(tp_to_dev(tp),  in rtl8169_rx_clear()
3911 			       le64_to_cpu(tp->RxDescArray[i].addr),  in rtl8169_rx_clear()
3913 		__free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));  in rtl8169_rx_clear()
3914 		tp->Rx_databuff[i] = NULL;  in rtl8169_rx_clear()
3915 		tp->RxDescArray[i].addr = 0;  in rtl8169_rx_clear()
3916 		tp->RxDescArray[i].opts1 = 0;  in rtl8169_rx_clear()
3920 static int rtl8169_rx_fill(struct rtl8169_private *tp)  in rtl8169_rx_fill()  argument
3927 		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);  in rtl8169_rx_fill()
3929 			rtl8169_rx_clear(tp);  in rtl8169_rx_fill()
3932 		tp->Rx_databuff[i] = data;  in rtl8169_rx_fill()
3936 	tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);  in rtl8169_rx_fill()
3941 static int rtl8169_init_ring(struct rtl8169_private *tp)  in rtl8169_init_ring()  argument
3943 	rtl8169_init_ring_indexes(tp);  in rtl8169_init_ring()
3945 	memset(tp->tx_skb, 0, sizeof(tp->tx_skb));  in rtl8169_init_ring()
3946 	memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));  in rtl8169_init_ring()
3948 	return rtl8169_rx_fill(tp);  in rtl8169_init_ring()
3951 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)  in rtl8169_unmap_tx_skb()  argument
3953 	struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_unmap_tx_skb()
3954 	struct TxDesc *desc = tp->TxDescArray + entry;  in rtl8169_unmap_tx_skb()
3956 	dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,  in rtl8169_unmap_tx_skb()
3962 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,  in rtl8169_tx_clear_range()  argument
3969 		struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_tx_clear_range()
3975 			rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_tx_clear_range()
3982 static void rtl8169_tx_clear(struct rtl8169_private *tp)  in rtl8169_tx_clear()  argument
3984 	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);  in rtl8169_tx_clear()
3985 	netdev_reset_queue(tp->dev);  in rtl8169_tx_clear()
3988 static void rtl8169_cleanup(struct rtl8169_private *tp)  in rtl8169_cleanup()  argument
3990 	napi_disable(&tp->napi);  in rtl8169_cleanup()
3996 	rtl8169_irq_mask_and_ack(tp);  in rtl8169_cleanup()
3998 	rtl_rx_close(tp);  in rtl8169_cleanup()
4000 	switch (tp->mac_version) {  in rtl8169_cleanup()
4003 		rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);  in rtl8169_cleanup()
4006 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
4007 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);  in rtl8169_cleanup()
4010 		rtl_enable_rxdvgate(tp);  in rtl8169_cleanup()
4014 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
4019 	rtl_hw_reset(tp);  in rtl8169_cleanup()
4021 	rtl8169_tx_clear(tp);  in rtl8169_cleanup()
4022 	rtl8169_init_ring_indexes(tp);  in rtl8169_cleanup()
4025 static void rtl_reset_work(struct rtl8169_private *tp)  in rtl_reset_work()  argument
4029 	netif_stop_queue(tp->dev);  in rtl_reset_work()
4031 	rtl8169_cleanup(tp);  in rtl_reset_work()
4034 		rtl8169_mark_to_asic(tp->RxDescArray + i);  in rtl_reset_work()
4036 	napi_enable(&tp->napi);  in rtl_reset_work()
4037 	rtl_hw_start(tp);  in rtl_reset_work()
4042 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_tx_timeout()  local
4044 	rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);  in rtl8169_tx_timeout()
4047 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,  in rtl8169_tx_map()  argument
4050 	struct TxDesc *txd = tp->TxDescArray + entry;  in rtl8169_tx_map()
4051 	struct device *d = tp_to_dev(tp);  in rtl8169_tx_map()
4060 			netdev_err(tp->dev, "Failed to map TX data!\n");  in rtl8169_tx_map()
4074 	tp->tx_skb[entry].len = len;  in rtl8169_tx_map()
4079 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,  in rtl8169_xmit_frags()  argument
4092 		if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))  in rtl8169_xmit_frags()
4099 	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);  in rtl8169_xmit_frags()
4124 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,  in rtl8125_quirk_udp_padto()  argument
4151 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,  in rtl_quirk_packet_padto()  argument
4156 	switch (tp->mac_version) {  in rtl_quirk_packet_padto()
4158 		padto = rtl8125_quirk_udp_padto(tp, skb);  in rtl_quirk_packet_padto()
4164 	switch (tp->mac_version) {  in rtl_quirk_packet_padto()
4196 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,  in rtl8169_tso_csum_v2()  argument
4245 		unsigned int padto = rtl_quirk_packet_padto(tp, skb);  in rtl8169_tso_csum_v2()
4254 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)  in rtl_tx_slots_avail()  argument
4256 	return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);  in rtl_tx_slots_avail()
4260 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)  in rtl_chip_supports_csum_v2()  argument
4262 	switch (tp->mac_version) {  in rtl_chip_supports_csum_v2()
4271 static void rtl8169_doorbell(struct rtl8169_private *tp)  in rtl8169_doorbell()  argument
4273 	if (rtl_is_8125(tp))  in rtl8169_doorbell()
4274 		RTL_W16(tp, TxPoll_8125, BIT(0));  in rtl8169_doorbell()
4276 		RTL_W8(tp, TxPoll, NPQ);  in rtl8169_doorbell()
4282 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_start_xmit()  local
4283 	unsigned int entry = tp->cur_tx % NUM_TX_DESC;  in rtl8169_start_xmit()
4289 	if (unlikely(!rtl_tx_slots_avail(tp))) {  in rtl8169_start_xmit()
4299 	if (!rtl_chip_supports_csum_v2(tp))  in rtl8169_start_xmit()
4301 	else if (!rtl8169_tso_csum_v2(tp, skb, opts))  in rtl8169_start_xmit()
4304 	if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,  in rtl8169_start_xmit()
4308 	txd_first = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4312 		if (rtl8169_xmit_frags(tp, skb, opts, entry))  in rtl8169_start_xmit()
4317 	txd_last = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4319 	tp->tx_skb[entry].skb = skb;  in rtl8169_start_xmit()
4333 	WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);  in rtl8169_start_xmit()
4335 	stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),  in rtl8169_start_xmit()
4339 		rtl8169_doorbell(tp);  in rtl8169_start_xmit()
4344 	rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_start_xmit()
4386 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_features_check()  local
4389 		if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl8169_features_check()
4393 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4400 		if (rtl_quirk_packet_padto(tp, skb))  in rtl8169_features_check()
4404 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4413 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_pcierr_interrupt()  local
4414 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_pcierr_interrupt()
4426 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_pcierr_interrupt()
4429 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,  in rtl_tx()  argument
4435 	dirty_tx = tp->dirty_tx;  in rtl_tx()
4437 	while (READ_ONCE(tp->cur_tx) != dirty_tx) {  in rtl_tx()
4441 		status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));  in rtl_tx()
4445 		skb = tp->tx_skb[entry].skb;  in rtl_tx()
4446 		rtl8169_unmap_tx_skb(tp, entry);  in rtl_tx()
4456 	if (tp->dirty_tx != dirty_tx) {  in rtl_tx()
4458 		WRITE_ONCE(tp->dirty_tx, dirty_tx);  in rtl_tx()
4461 					      rtl_tx_slots_avail(tp),  in rtl_tx()
4471 		if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)  in rtl_tx()
4472 			rtl8169_doorbell(tp);  in rtl_tx()
4491 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)  in rtl_rx()  argument
4493 	struct device *d = tp_to_dev(tp);  in rtl_rx()
4496 	for (count = 0; count < budget; count++, tp->cur_rx++) {  in rtl_rx()
4497 		unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;  in rtl_rx()
4498 		struct RxDesc *desc = tp->RxDescArray + entry;  in rtl_rx()
4543 		skb = napi_alloc_skb(&tp->napi, pkt_size);  in rtl_rx()
4550 		rx_buf = page_address(tp->Rx_databuff[entry]);  in rtl_rx()
4567 		napi_gro_receive(&tp->napi, skb);  in rtl_rx()
4579 	struct rtl8169_private *tp = dev_instance;  in rtl8169_interrupt()  local
4580 	u32 status = rtl_get_events(tp);  in rtl8169_interrupt()
4582 	if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))  in rtl8169_interrupt()
4587 	    tp->mac_version <= RTL_GIGA_MAC_VER_06)) {  in rtl8169_interrupt()
4588 		rtl8169_pcierr_interrupt(tp->dev);  in rtl8169_interrupt()
4593 		phy_mac_interrupt(tp->phydev);  in rtl8169_interrupt()
4596 	    tp->mac_version == RTL_GIGA_MAC_VER_11)) {  in rtl8169_interrupt()
4597 		netif_stop_queue(tp->dev);  in rtl8169_interrupt()
4598 		rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_interrupt()
4601 	rtl_irq_disable(tp);  in rtl8169_interrupt()
4602 	napi_schedule(&tp->napi);  in rtl8169_interrupt()
4604 	rtl_ack_events(tp, status);  in rtl8169_interrupt()
4611 	struct rtl8169_private *tp =  in rtl_task()  local
4617 	if (!netif_running(tp->dev) ||  in rtl_task()
4618 	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))  in rtl_task()
4621 	if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {  in rtl_task()
4623 		if (RTL_R32(tp, TxConfig) == ~0) {  in rtl_task()
4624 			ret = pci_reset_bus(tp->pci_dev);  in rtl_task()
4626 				netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");  in rtl_task()
4627 				netif_device_detach(tp->dev);  in rtl_task()
4633 		ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |  in rtl_task()
4636 			netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");  in rtl_task()
4640 	if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {  in rtl_task()
4642 		rtl_reset_work(tp);  in rtl_task()
4643 		netif_wake_queue(tp->dev);  in rtl_task()
4644 	} else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {  in rtl_task()
4645 		rtl_reset_work(tp);  in rtl_task()
4653 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);  in rtl8169_poll()  local
4654 	struct net_device *dev = tp->dev;  in rtl8169_poll()
4657 	rtl_tx(dev, tp, budget);  in rtl8169_poll()
4659 	work_done = rtl_rx(dev, tp, budget);  in rtl8169_poll()
4662 		rtl_irq_enable(tp);  in rtl8169_poll()
4669 	struct rtl8169_private *tp = netdev_priv(ndev);  in r8169_phylink_handler()  local
4670 	struct device *d = tp_to_dev(tp);  in r8169_phylink_handler()
4673 		rtl_link_chg_patch(tp);  in r8169_phylink_handler()
4675 		netif_wake_queue(tp->dev);  in r8169_phylink_handler()
4678 		if (rtl_is_8125(tp))  in r8169_phylink_handler()
4679 			rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);  in r8169_phylink_handler()
4683 	phy_print_status(tp->phydev);  in r8169_phylink_handler()
4686 static int r8169_phy_connect(struct rtl8169_private *tp)  in r8169_phy_connect()  argument
4688 	struct phy_device *phydev = tp->phydev;  in r8169_phy_connect()
4692 	phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :  in r8169_phy_connect()
4695 	ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,  in r8169_phy_connect()
4700 	if (!tp->supports_gmii)  in r8169_phy_connect()
4708 static void rtl8169_down(struct rtl8169_private *tp)  in rtl8169_down()  argument
4711 	bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);  in rtl8169_down()
4713 	phy_stop(tp->phydev);  in rtl8169_down()
4715 	rtl8169_update_counters(tp);  in rtl8169_down()
4717 	pci_clear_master(tp->pci_dev);  in rtl8169_down()
4718 	rtl_pci_commit(tp);  in rtl8169_down()
4720 	rtl8169_cleanup(tp);  in rtl8169_down()
4721 	rtl_disable_exit_l1(tp);  in rtl8169_down()
4722 	rtl_prepare_power_down(tp);  in rtl8169_down()
4724 	if (tp->dash_type != RTL_DASH_NONE)  in rtl8169_down()
4725 		rtl8168_driver_stop(tp);  in rtl8169_down()
4728 static void rtl8169_up(struct rtl8169_private *tp)  in rtl8169_up()  argument
4730 	if (tp->dash_type != RTL_DASH_NONE)  in rtl8169_up()
4731 		rtl8168_driver_start(tp);  in rtl8169_up()
4733 	pci_set_master(tp->pci_dev);  in rtl8169_up()
4734 	phy_init_hw(tp->phydev);  in rtl8169_up()
4735 	phy_resume(tp->phydev);  in rtl8169_up()
4736 	rtl8169_init_phy(tp);  in rtl8169_up()
4737 	napi_enable(&tp->napi);  in rtl8169_up()
4738 	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);  in rtl8169_up()
4739 	rtl_reset_work(tp);  in rtl8169_up()
4741 	phy_start(tp->phydev);  in rtl8169_up()
4746 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_close()  local
4747 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_close()
4752 	rtl8169_down(tp);  in rtl8169_close()
4753 	rtl8169_rx_clear(tp);  in rtl8169_close()
4755 	cancel_work(&tp->wk.work);  in rtl8169_close()
4757 	free_irq(tp->irq, tp);  in rtl8169_close()
4759 	phy_disconnect(tp->phydev);  in rtl8169_close()
4761 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl8169_close()
4762 			  tp->RxPhyAddr);  in rtl8169_close()
4763 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl8169_close()
4764 			  tp->TxPhyAddr);  in rtl8169_close()
4765 	tp->TxDescArray = NULL;  in rtl8169_close()
4766 	tp->RxDescArray = NULL;  in rtl8169_close()
4776 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_netpoll()  local
4778 	rtl8169_interrupt(tp->irq, tp);  in rtl8169_netpoll()
4784 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_open()  local
4785 	struct pci_dev *pdev = tp->pci_dev;  in rtl_open()
4795 	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,  in rtl_open()
4796 					     &tp->TxPhyAddr, GFP_KERNEL);  in rtl_open()
4797 	if (!tp->TxDescArray)  in rtl_open()
4800 	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,  in rtl_open()
4801 					     &tp->RxPhyAddr, GFP_KERNEL);  in rtl_open()
4802 	if (!tp->RxDescArray)  in rtl_open()
4805 	retval = rtl8169_init_ring(tp);  in rtl_open()
4809 	rtl_request_firmware(tp);  in rtl_open()
4812 	retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);  in rtl_open()
4816 	retval = r8169_phy_connect(tp);  in rtl_open()
4820 	rtl8169_up(tp);  in rtl_open()
4821 	rtl8169_init_counter_offsets(tp);  in rtl_open()
4829 	free_irq(tp->irq, tp);  in rtl_open()
4831 	rtl_release_firmware(tp);  in rtl_open()
4832 	rtl8169_rx_clear(tp);  in rtl_open()
4834 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl_open()
4835 			  tp->RxPhyAddr);  in rtl_open()
4836 	tp->RxDescArray = NULL;  in rtl_open()
4838 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl_open()
4839 			  tp->TxPhyAddr);  in rtl_open()
4840 	tp->TxDescArray = NULL;  in rtl_open()
4847 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_stats64()  local
4848 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_get_stats64()
4849 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_get_stats64()
4861 		rtl8169_update_counters(tp);  in rtl8169_get_stats64()
4868 		le64_to_cpu(tp->tc_offset.tx_errors);  in rtl8169_get_stats64()
4870 		le32_to_cpu(tp->tc_offset.tx_multi_collision);  in rtl8169_get_stats64()
4872 		le16_to_cpu(tp->tc_offset.tx_aborted);  in rtl8169_get_stats64()
4874 		le16_to_cpu(tp->tc_offset.rx_missed);  in rtl8169_get_stats64()
4879 static void rtl8169_net_suspend(struct rtl8169_private *tp)  in rtl8169_net_suspend()  argument
4881 	netif_device_detach(tp->dev);  in rtl8169_net_suspend()
4883 	if (netif_running(tp->dev))  in rtl8169_net_suspend()
4884 		rtl8169_down(tp);  in rtl8169_net_suspend()
4889 	struct rtl8169_private *tp = dev_get_drvdata(dev);  in rtl8169_runtime_resume()  local
4891 	rtl_rar_set(tp, tp->dev->dev_addr);  in rtl8169_runtime_resume()
4892 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_runtime_resume()
4894 	if (tp->TxDescArray)  in rtl8169_runtime_resume()
4895 		rtl8169_up(tp);  in rtl8169_runtime_resume()
4897 	netif_device_attach(tp->dev);  in rtl8169_runtime_resume()
4904 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_suspend()  local
4907 	rtl8169_net_suspend(tp);  in rtl8169_suspend()
4908 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_suspend()
4909 		clk_disable_unprepare(tp->clk);  in rtl8169_suspend()
4917 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_resume()  local
4919 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_resume()
4920 		clk_prepare_enable(tp->clk);  in rtl8169_resume()
4923 	if (tp->mac_version == RTL_GIGA_MAC_VER_37)  in rtl8169_resume()
4924 		rtl_init_rxcfg(tp);  in rtl8169_resume()
4931 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_suspend()  local
4933 	if (!tp->TxDescArray) {  in rtl8169_runtime_suspend()
4934 		netif_device_detach(tp->dev);  in rtl8169_runtime_suspend()
4939 	__rtl8169_set_wol(tp, WAKE_PHY);  in rtl8169_runtime_suspend()
4940 	rtl8169_net_suspend(tp);  in rtl8169_runtime_suspend()
4948 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_idle()  local
4950 	if (tp->dash_enabled)  in rtl8169_runtime_idle()
4953 	if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))  in rtl8169_runtime_idle()
4967 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_shutdown()  local
4970 	rtl8169_net_suspend(tp);  in rtl_shutdown()
4974 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_shutdown()
4976 	if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {  in rtl_shutdown()
4977 		pci_wake_from_d3(pdev, tp->saved_wolopts);  in rtl_shutdown()
4984 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_remove_one()  local
4989 	cancel_work_sync(&tp->wk.work);  in rtl_remove_one()
4991 	unregister_netdev(tp->dev);  in rtl_remove_one()
4993 	if (tp->dash_type != RTL_DASH_NONE)  in rtl_remove_one()
4994 		rtl8168_driver_stop(tp);  in rtl_remove_one()
4996 	rtl_release_firmware(tp);  in rtl_remove_one()
4999 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_remove_one()
5022 static void rtl_set_irq_mask(struct rtl8169_private *tp)  in rtl_set_irq_mask()  argument
5024 	tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;  in rtl_set_irq_mask()
5026 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_set_irq_mask()
5027 		tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;  in rtl_set_irq_mask()
5028 	else if (tp->mac_version == RTL_GIGA_MAC_VER_11)  in rtl_set_irq_mask()
5030 		tp->irq_mask |= RxFIFOOver;  in rtl_set_irq_mask()
5032 		tp->irq_mask |= RxOverflow;  in rtl_set_irq_mask()
5035 static int rtl_alloc_irq(struct rtl8169_private *tp)  in rtl_alloc_irq()  argument
5039 	switch (tp->mac_version) {  in rtl_alloc_irq()
5041 		rtl_unlock_config_regs(tp);  in rtl_alloc_irq()
5042 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);  in rtl_alloc_irq()
5043 		rtl_lock_config_regs(tp);  in rtl_alloc_irq()
5053 	return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);  in rtl_alloc_irq()
5056 static void rtl_read_mac_address(struct rtl8169_private *tp,  in rtl_read_mac_address()  argument
5060 	if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {  in rtl_read_mac_address()
5063 		value = rtl_eri_read(tp, 0xe0);  in rtl_read_mac_address()
5065 		value = rtl_eri_read(tp, 0xe4);  in rtl_read_mac_address()
5067 	} else if (rtl_is_8125(tp)) {  in rtl_read_mac_address()
5068 		rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);  in rtl_read_mac_address()
5074 	return RTL_R8(tp, MCU) & LINK_LIST_RDY;  in DECLARE_RTL_COND()
5077 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)  in r8168g_wait_ll_share_fifo_ready()  argument
5079 	rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);  in r8168g_wait_ll_share_fifo_ready()
5084 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_read_reg()  local
5089 	return rtl_readphy(tp, phyreg);  in r8169_mdio_read_reg()
5095 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_write_reg()  local
5100 	rtl_writephy(tp, phyreg, val);  in r8169_mdio_write_reg()
5105 static int r8169_mdio_register(struct rtl8169_private *tp)  in r8169_mdio_register()  argument
5107 	struct pci_dev *pdev = tp->pci_dev;  in r8169_mdio_register()
5116 	if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||  in r8169_mdio_register()
5117 	    tp->mac_version == RTL_GIGA_MAC_VER_26)  in r8169_mdio_register()
5118 		r8169_mdio_write(tp, 0x1f, 0);  in r8169_mdio_register()
5125 	new_bus->priv = tp;  in r8169_mdio_register()
5138 	tp->phydev = mdiobus_get_phy(new_bus, 0);  in r8169_mdio_register()
5139 	if (!tp->phydev) {  in r8169_mdio_register()
5141 	} else if (!tp->phydev->drv) {  in r8169_mdio_register()
5146 			tp->phydev->phy_id);  in r8169_mdio_register()
5150 	tp->phydev->mac_managed_pm = true;  in r8169_mdio_register()
5152 	phy_support_asym_pause(tp->phydev);  in r8169_mdio_register()
5155 	phy_suspend(tp->phydev);  in r8169_mdio_register()
5160 static void rtl_hw_init_8168g(struct rtl8169_private *tp)  in rtl_hw_init_8168g()  argument
5162 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8168g()
5164 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8168g()
5166 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8168g()
5168 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8168g()
5169 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5171 	r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));  in rtl_hw_init_8168g()
5172 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5175 static void rtl_hw_init_8125(struct rtl8169_private *tp)  in rtl_hw_init_8125()  argument
5177 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8125()
5179 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8125()
5181 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8125()
5183 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8125()
5184 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5186 	r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);  in rtl_hw_init_8125()
5187 	r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);  in rtl_hw_init_8125()
5188 	r8168_mac_ocp_write(tp, 0xc01e, 0x5555);  in rtl_hw_init_8125()
5189 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5192 static void rtl_hw_initialize(struct rtl8169_private *tp)  in rtl_hw_initialize()  argument
5194 	switch (tp->mac_version) {  in rtl_hw_initialize()
5196 		rtl8168ep_stop_cmac(tp);  in rtl_hw_initialize()
5199 		rtl_hw_init_8168g(tp);  in rtl_hw_initialize()
5202 		rtl_hw_init_8125(tp);  in rtl_hw_initialize()
5209 static int rtl_jumbo_max(struct rtl8169_private *tp)  in rtl_jumbo_max()  argument
5212 	if (!tp->supports_gmii)  in rtl_jumbo_max()
5215 	switch (tp->mac_version) {  in rtl_jumbo_max()
5231 static void rtl_init_mac_address(struct rtl8169_private *tp)  in rtl_init_mac_address()  argument
5234 	struct net_device *dev = tp->dev;  in rtl_init_mac_address()
5237 	rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);  in rtl_init_mac_address()
5241 	rtl_read_mac_address(tp, mac_addr);  in rtl_init_mac_address()
5245 	rtl_read_mac_from_reg(tp, mac_addr, MAC0);  in rtl_init_mac_address()
5251 	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");  in rtl_init_mac_address()
5254 	rtl_rar_set(tp, mac_addr);  in rtl_init_mac_address()
5258 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)  in rtl_aspm_is_safe()  argument
5260 	if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&  in rtl_aspm_is_safe()
5261 	    r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)  in rtl_aspm_is_safe()
5269 	struct rtl8169_private *tp;  in rtl_init_one()  local
5276 	dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));  in rtl_init_one()
5282 	tp = netdev_priv(dev);  in rtl_init_one()
5283 	tp->dev = dev;  in rtl_init_one()
5284 	tp->pci_dev = pdev;  in rtl_init_one()
5285 	tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;  in rtl_init_one()
5286 	tp->eee_adv = -1;  in rtl_init_one()
5287 	tp->ocp_base = OCP_STD_PHY_BASE;  in rtl_init_one()
5289 	raw_spin_lock_init(&tp->cfg9346_usage_lock);  in rtl_init_one()
5290 	raw_spin_lock_init(&tp->config25_lock);  in rtl_init_one()
5291 	raw_spin_lock_init(&tp->mac_ocp_lock);  in rtl_init_one()
5299 	tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");  in rtl_init_one()
5300 	if (IS_ERR(tp->clk))  in rtl_init_one()
5301 		return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");  in rtl_init_one()
5320 	tp->mmio_addr = pcim_iomap_table(pdev)[region];  in rtl_init_one()
5322 	txconfig = RTL_R32(tp, TxConfig);  in rtl_init_one()
5329 	chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);  in rtl_init_one()
5334 	tp->mac_version = chipset;  in rtl_init_one()
5339 	if (rtl_aspm_is_safe(tp))  in rtl_init_one()
5343 	tp->aspm_manageable = !rc;  in rtl_init_one()
5345 	tp->dash_type = rtl_get_dash_type(tp);  in rtl_init_one()
5346 	tp->dash_enabled = rtl_dash_is_enabled(tp);  in rtl_init_one()
5348 	tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;  in rtl_init_one()
5350 	if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&  in rtl_init_one()
5354 	rtl_init_rxcfg(tp);  in rtl_init_one()
5356 	rtl8169_irq_mask_and_ack(tp);  in rtl_init_one()
5358 	rtl_hw_initialize(tp);  in rtl_init_one()
5360 	rtl_hw_reset(tp);  in rtl_init_one()
5362 	rc = rtl_alloc_irq(tp);  in rtl_init_one()
5366 	tp->irq = pci_irq_vector(pdev, 0);  in rtl_init_one()
5368 	INIT_WORK(&tp->wk.work, rtl_task);  in rtl_init_one()
5370 	rtl_init_mac_address(tp);  in rtl_init_one()
5374 	netif_napi_add(dev, &tp->napi, rtl8169_poll);  in rtl_init_one()
5385 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl_init_one()
5389 	if (rtl_chip_supports_csum_v2(tp))  in rtl_init_one()
5399 	if (rtl_chip_supports_csum_v2(tp)) {  in rtl_init_one()
5417 	if (!tp->dash_enabled) {  in rtl_init_one()
5418 		rtl_set_d3_pll_down(tp, true);  in rtl_init_one()
5420 		rtl_set_d3_pll_down(tp, false);  in rtl_init_one()
5424 	jumbo_max = rtl_jumbo_max(tp);  in rtl_init_one()
5428 	rtl_set_irq_mask(tp);  in rtl_init_one()
5430 	tp->fw_name = rtl_chip_infos[chipset].fw_name;  in rtl_init_one()
5432 	tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),  in rtl_init_one()
5433 					    &tp->counters_phys_addr,  in rtl_init_one()
5435 	if (!tp->counters)  in rtl_init_one()
5438 	pci_set_drvdata(pdev, tp);  in rtl_init_one()
5440 	rc = r8169_mdio_register(tp);  in rtl_init_one()
5449 		    rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);  in rtl_init_one()
5453 			    jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?  in rtl_init_one()
5456 	if (tp->dash_type != RTL_DASH_NONE) {  in rtl_init_one()
5458 			    tp->dash_enabled ? "enabled" : "disabled");  in rtl_init_one()
5459 		rtl8168_driver_start(tp);  in rtl_init_one()