Lines Matching refs:mcs
27 void mcs_get_tx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id) in mcs_get_tx_secy_stats() argument
32 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
35 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
38 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
41 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
44 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
47 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
50 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
53 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
56 stats->octet_encrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
59 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
62 stats->pkt_noactivesa_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
65 stats->pkt_toolong_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
68 stats->pkt_untagged_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
71 void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id) in mcs_get_rx_secy_stats() argument
76 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
79 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
82 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
85 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
88 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
91 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
94 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
97 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
100 stats->octet_decrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
103 stats->octet_validated_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
106 stats->pkt_port_disabled_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
109 stats->pkt_badtag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
112 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
115 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
118 stats->pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
121 stats->pkt_untaged_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
124 stats->pkt_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
126 if (mcs->hw->mcs_blks > 1) { in mcs_get_rx_secy_stats()
128 stats->pkt_notag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
132 void mcs_get_flowid_stats(struct mcs *mcs, struct mcs_flowid_stats *stats, in mcs_get_flowid_stats() argument
142 stats->tcam_hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_flowid_stats()
145 void mcs_get_port_stats(struct mcs *mcs, struct mcs_port_stats *stats, in mcs_get_port_stats() argument
152 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
155 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
156 if (mcs->hw->mcs_blks > 1) { in mcs_get_port_stats()
158 stats->preempt_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
162 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
165 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
168 stats->sectag_insert_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
172 void mcs_get_sa_stats(struct mcs *mcs, struct mcs_sa_stats *stats, int id, int dir) in mcs_get_sa_stats() argument
178 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
181 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
184 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
187 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
190 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
193 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
196 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
200 void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats, in mcs_get_sc_stats() argument
207 stats->hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
210 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
213 stats->pkt_late_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
216 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
219 stats->pkt_unchecked_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
221 if (mcs->hw->mcs_blks > 1) { in mcs_get_sc_stats()
223 stats->pkt_delay_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
226 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
228 if (mcs->hw->mcs_blks == 1) { in mcs_get_sc_stats()
230 stats->octet_decrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
233 stats->octet_validate_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
237 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
240 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
242 if (mcs->hw->mcs_blks == 1) { in mcs_get_sc_stats()
244 stats->octet_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
247 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
252 void mcs_clear_stats(struct mcs *mcs, u8 type, u8 id, int dir) in mcs_clear_stats() argument
266 mcs_reg_write(mcs, reg, BIT_ULL(0)); in mcs_clear_stats()
270 mcs_get_flowid_stats(mcs, &flowid_st, id, dir); in mcs_clear_stats()
274 mcs_get_rx_secy_stats(mcs, &secy_st, id); in mcs_clear_stats()
276 mcs_get_tx_secy_stats(mcs, &secy_st, id); in mcs_clear_stats()
279 mcs_get_sc_stats(mcs, &sc_st, id, dir); in mcs_clear_stats()
282 mcs_get_sa_stats(mcs, &sa_st, id, dir); in mcs_clear_stats()
285 mcs_get_port_stats(mcs, &port_st, id, dir); in mcs_clear_stats()
289 mcs_reg_write(mcs, reg, 0x0); in mcs_clear_stats()
292 int mcs_clear_all_stats(struct mcs *mcs, u16 pcifunc, int dir) in mcs_clear_all_stats() argument
298 map = &mcs->rx; in mcs_clear_all_stats()
300 map = &mcs->tx; in mcs_clear_all_stats()
306 mcs_clear_stats(mcs, MCS_FLOWID_STATS, id, dir); in mcs_clear_all_stats()
313 mcs_clear_stats(mcs, MCS_SECY_STATS, id, dir); in mcs_clear_all_stats()
320 mcs_clear_stats(mcs, MCS_SC_STATS, id, dir); in mcs_clear_all_stats()
327 mcs_clear_stats(mcs, MCS_SA_STATS, id, dir); in mcs_clear_all_stats()
332 void mcs_pn_table_write(struct mcs *mcs, u8 pn_id, u64 next_pn, u8 dir) in mcs_pn_table_write() argument
340 mcs_reg_write(mcs, reg, next_pn); in mcs_pn_table_write()
343 void cn10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map) in cn10kb_mcs_tx_sa_mem_map_write() argument
355 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
362 void cn10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map) in cn10kb_mcs_rx_sa_mem_map_write() argument
369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_rx_sa_mem_map_write()
372 void mcs_sa_plcy_write(struct mcs *mcs, u64 *plcy, int sa_id, int dir) in mcs_sa_plcy_write() argument
380 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
385 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
390 void mcs_ena_dis_sc_cam_entry(struct mcs *mcs, int sc_id, int ena) in mcs_ena_dis_sc_cam_entry() argument
399 val = mcs_reg_read(mcs, reg) | BIT_ULL(sc_id); in mcs_ena_dis_sc_cam_entry()
401 val = mcs_reg_read(mcs, reg) & ~BIT_ULL(sc_id); in mcs_ena_dis_sc_cam_entry()
403 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_sc_cam_entry()
406 void mcs_rx_sc_cam_write(struct mcs *mcs, u64 sci, u64 secy, int sc_id) in mcs_rx_sc_cam_write() argument
408 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(0, sc_id), sci); in mcs_rx_sc_cam_write()
409 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(1, sc_id), secy); in mcs_rx_sc_cam_write()
411 mcs_ena_dis_sc_cam_entry(mcs, sc_id, true); in mcs_rx_sc_cam_write()
414 void mcs_secy_plcy_write(struct mcs *mcs, u64 plcy, int secy_id, int dir) in mcs_secy_plcy_write() argument
423 mcs_reg_write(mcs, reg, plcy); in mcs_secy_plcy_write()
425 if (mcs->hw->mcs_blks == 1 && dir == MCS_RX) in mcs_secy_plcy_write()
426 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(secy_id), 0x0ull); in mcs_secy_plcy_write()
429 void cn10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir) in cn10kb_mcs_flowid_secy_map() argument
441 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_flowid_secy_map()
444 void mcs_ena_dis_flowid_entry(struct mcs *mcs, int flow_id, int dir, int ena) in mcs_ena_dis_flowid_entry() argument
460 val = mcs_reg_read(mcs, reg) | BIT_ULL(flow_id); in mcs_ena_dis_flowid_entry()
462 val = mcs_reg_read(mcs, reg) & ~BIT_ULL(flow_id); in mcs_ena_dis_flowid_entry()
464 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_flowid_entry()
467 void mcs_flowid_entry_write(struct mcs *mcs, u64 *data, u64 *mask, int flow_id, int dir) in mcs_flowid_entry_write() argument
475 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
479 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
484 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
488 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
493 int mcs_install_flowid_bypass_entry(struct mcs *mcs) in mcs_install_flowid_bypass_entry() argument
500 flow_id = mcs->hw->tcam_entries - MCS_RSRC_RSVD_CNT; in mcs_install_flowid_bypass_entry()
501 __set_bit(flow_id, mcs->rx.flow_ids.bmap); in mcs_install_flowid_bypass_entry()
502 __set_bit(flow_id, mcs->tx.flow_ids.bmap); in mcs_install_flowid_bypass_entry()
506 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
510 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
513 secy_id = mcs->hw->secy_entries - MCS_RSRC_RSVD_CNT; in mcs_install_flowid_bypass_entry()
514 __set_bit(secy_id, mcs->rx.secy.bmap); in mcs_install_flowid_bypass_entry()
515 __set_bit(secy_id, mcs->tx.secy.bmap); in mcs_install_flowid_bypass_entry()
519 if (mcs->hw->mcs_blks > 1) in mcs_install_flowid_bypass_entry()
521 mcs_secy_plcy_write(mcs, plcy, secy_id, MCS_RX); in mcs_install_flowid_bypass_entry()
525 if (mcs->hw->mcs_blks > 1) in mcs_install_flowid_bypass_entry()
527 mcs_secy_plcy_write(mcs, plcy, secy_id, MCS_TX); in mcs_install_flowid_bypass_entry()
533 mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, MCS_RX); in mcs_install_flowid_bypass_entry()
535 mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, MCS_TX); in mcs_install_flowid_bypass_entry()
538 mcs_ena_dis_flowid_entry(mcs, flow_id, MCS_RX, true); in mcs_install_flowid_bypass_entry()
539 mcs_ena_dis_flowid_entry(mcs, flow_id, MCS_TX, true); in mcs_install_flowid_bypass_entry()
544 void mcs_clear_secy_plcy(struct mcs *mcs, int secy_id, int dir) in mcs_clear_secy_plcy() argument
550 map = &mcs->rx; in mcs_clear_secy_plcy()
552 map = &mcs->tx; in mcs_clear_secy_plcy()
555 mcs_secy_plcy_write(mcs, 0, secy_id, dir); in mcs_clear_secy_plcy()
561 mcs_ena_dis_flowid_entry(mcs, flow_id, dir, false); in mcs_clear_secy_plcy()
582 int mcs_free_ctrlpktrule(struct mcs *mcs, struct mcs_free_ctrl_pkt_rule_req *req) in mcs_free_ctrlpktrule() argument
590 map = (req->dir == MCS_RX) ? &mcs->rx : &mcs->tx; in mcs_free_ctrlpktrule()
597 dis = mcs_reg_read(mcs, reg); in mcs_free_ctrlpktrule()
599 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
605 dis = mcs_reg_read(mcs, reg); in mcs_free_ctrlpktrule()
607 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
612 int mcs_ctrlpktrule_write(struct mcs *mcs, struct mcs_ctrl_pkt_rule_write_req *req) in mcs_ctrlpktrule_write() argument
627 mcs_reg_write(mcs, reg, req->data0); in mcs_ctrlpktrule_write()
637 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
646 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
648 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
651 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
653 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
665 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
667 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
669 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
672 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
674 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
676 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
687 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
693 enb = mcs_reg_read(mcs, reg); in mcs_ctrlpktrule_write()
695 mcs_reg_write(mcs, reg, enb); in mcs_ctrlpktrule_write()
712 int mcs_free_all_rsrc(struct mcs *mcs, int dir, u16 pcifunc) in mcs_free_all_rsrc() argument
718 map = &mcs->rx; in mcs_free_all_rsrc()
720 map = &mcs->tx; in mcs_free_all_rsrc()
728 mcs_ena_dis_flowid_entry(mcs, id, dir, false); in mcs_free_all_rsrc()
737 mcs_clear_secy_plcy(mcs, id, dir); in mcs_free_all_rsrc()
748 mcs_ena_dis_sc_cam_entry(mcs, id, false); in mcs_free_all_rsrc()
771 int mcs_alloc_all_rsrc(struct mcs *mcs, u8 *flow_id, u8 *secy_id, in mcs_alloc_all_rsrc() argument
778 map = &mcs->rx; in mcs_alloc_all_rsrc()
780 map = &mcs->tx; in mcs_alloc_all_rsrc()
810 static void cn10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs) in cn10kb_mcs_tx_pn_wrapped_handler() argument
817 sc_bmap = &mcs->tx.sc; in cn10kb_mcs_tx_pn_wrapped_handler()
819 event.mcs_id = mcs->mcs_id; in cn10kb_mcs_tx_pn_wrapped_handler()
822 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cn10kb_mcs_tx_pn_wrapped_handler()
823 val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc)); in cn10kb_mcs_tx_pn_wrapped_handler()
825 if (mcs->tx_sa_active[sc]) in cn10kb_mcs_tx_pn_wrapped_handler()
832 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cn10kb_mcs_tx_pn_wrapped_handler()
833 mcs_add_intr_wq_entry(mcs, &event); in cn10kb_mcs_tx_pn_wrapped_handler()
837 static void cn10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs) in cn10kb_mcs_tx_pn_thresh_reached_handler() argument
844 sc_bmap = &mcs->tx.sc; in cn10kb_mcs_tx_pn_thresh_reached_handler()
846 event.mcs_id = mcs->mcs_id; in cn10kb_mcs_tx_pn_thresh_reached_handler()
854 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cn10kb_mcs_tx_pn_thresh_reached_handler()
855 val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc)); in cn10kb_mcs_tx_pn_thresh_reached_handler()
863 if (status == mcs->tx_sa_active[sc]) in cn10kb_mcs_tx_pn_thresh_reached_handler()
871 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cn10kb_mcs_tx_pn_thresh_reached_handler()
872 mcs_add_intr_wq_entry(mcs, &event); in cn10kb_mcs_tx_pn_thresh_reached_handler()
876 static void mcs_rx_pn_thresh_reached_handler(struct mcs *mcs) in mcs_rx_pn_thresh_reached_handler() argument
883 for (reg = 0; reg < (mcs->hw->sa_entries / 64); reg++) { in mcs_rx_pn_thresh_reached_handler()
887 intr = mcs_reg_read(mcs, MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(reg)); in mcs_rx_pn_thresh_reached_handler()
892 event.mcs_id = mcs->mcs_id; in mcs_rx_pn_thresh_reached_handler()
895 event.pcifunc = mcs->rx.sa2pf_map[event.sa_id]; in mcs_rx_pn_thresh_reached_handler()
896 mcs_add_intr_wq_entry(mcs, &event); in mcs_rx_pn_thresh_reached_handler()
901 static void mcs_rx_misc_intr_handler(struct mcs *mcs, u64 intr) in mcs_rx_misc_intr_handler() argument
905 event.mcs_id = mcs->mcs_id; in mcs_rx_misc_intr_handler()
906 event.pcifunc = mcs->pf_map[0]; in mcs_rx_misc_intr_handler()
921 mcs_add_intr_wq_entry(mcs, &event); in mcs_rx_misc_intr_handler()
924 static void mcs_tx_misc_intr_handler(struct mcs *mcs, u64 intr) in mcs_tx_misc_intr_handler() argument
931 event.mcs_id = mcs->mcs_id; in mcs_tx_misc_intr_handler()
932 event.pcifunc = mcs->pf_map[0]; in mcs_tx_misc_intr_handler()
936 mcs_add_intr_wq_entry(mcs, &event); in mcs_tx_misc_intr_handler()
939 void cn10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, in cn10kb_mcs_bbe_intr_handler() argument
954 val = mcs_reg_read(mcs, reg); in cn10kb_mcs_bbe_intr_handler()
957 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in cn10kb_mcs_bbe_intr_handler()
960 dev_warn(mcs->dev, "BEE:Policy or data overflow occurred on lmac:%d\n", lmac); in cn10kb_mcs_bbe_intr_handler()
964 void cn10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, in cn10kb_mcs_pab_intr_handler() argument
972 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in cn10kb_mcs_pab_intr_handler()
974 dev_warn(mcs->dev, "PAB: overflow occurred on lmac:%d\n", lmac); in cn10kb_mcs_pab_intr_handler()
980 struct mcs *mcs = (struct mcs *)mcs_irq; in mcs_ip_intr_handler() local
984 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1C, BIT_ULL(0)); in mcs_ip_intr_handler()
987 intr = mcs_reg_read(mcs, MCSX_TOP_SLAVE_INT_SUM); in mcs_ip_intr_handler()
992 cpm_intr = mcs_reg_read(mcs, MCSX_CPM_RX_SLAVE_RX_INT); in mcs_ip_intr_handler()
995 mcs_rx_pn_thresh_reached_handler(mcs); in mcs_ip_intr_handler()
998 mcs_rx_misc_intr_handler(mcs, cpm_intr); in mcs_ip_intr_handler()
1001 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT, cpm_intr); in mcs_ip_intr_handler()
1006 cpm_intr = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_TX_INT); in mcs_ip_intr_handler()
1009 if (mcs->hw->mcs_blks > 1) in mcs_ip_intr_handler()
1010 cnf10kb_mcs_tx_pn_thresh_reached_handler(mcs); in mcs_ip_intr_handler()
1012 cn10kb_mcs_tx_pn_thresh_reached_handler(mcs); in mcs_ip_intr_handler()
1016 mcs_tx_misc_intr_handler(mcs, cpm_intr); in mcs_ip_intr_handler()
1019 if (mcs->hw->mcs_blks > 1) in mcs_ip_intr_handler()
1020 cnf10kb_mcs_tx_pn_wrapped_handler(mcs); in mcs_ip_intr_handler()
1022 cn10kb_mcs_tx_pn_wrapped_handler(mcs); in mcs_ip_intr_handler()
1025 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT, cpm_intr); in mcs_ip_intr_handler()
1030 bbe_intr = mcs_reg_read(mcs, MCSX_BBE_RX_SLAVE_BBE_INT); in mcs_ip_intr_handler()
1031 mcs->mcs_ops->mcs_bbe_intr_handler(mcs, bbe_intr, MCS_RX); in mcs_ip_intr_handler()
1034 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1035 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1040 bbe_intr = mcs_reg_read(mcs, MCSX_BBE_TX_SLAVE_BBE_INT); in mcs_ip_intr_handler()
1041 mcs->mcs_ops->mcs_bbe_intr_handler(mcs, bbe_intr, MCS_TX); in mcs_ip_intr_handler()
1044 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1045 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1050 pab_intr = mcs_reg_read(mcs, MCSX_PAB_RX_SLAVE_PAB_INT); in mcs_ip_intr_handler()
1051 mcs->mcs_ops->mcs_pab_intr_handler(mcs, pab_intr, MCS_RX); in mcs_ip_intr_handler()
1054 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1055 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1060 pab_intr = mcs_reg_read(mcs, MCSX_PAB_TX_SLAVE_PAB_INT); in mcs_ip_intr_handler()
1061 mcs->mcs_ops->mcs_pab_intr_handler(mcs, pab_intr, MCS_TX); in mcs_ip_intr_handler()
1064 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1065 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1069 mcs_reg_write(mcs, MCSX_IP_INT, BIT_ULL(0)); in mcs_ip_intr_handler()
1070 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_ip_intr_handler()
1075 static void *alloc_mem(struct mcs *mcs, int n) in alloc_mem() argument
1077 return devm_kcalloc(mcs->dev, n, sizeof(u16), GFP_KERNEL); in alloc_mem()
1080 static int mcs_alloc_struct_mem(struct mcs *mcs, struct mcs_rsrc_map *res) in mcs_alloc_struct_mem() argument
1082 struct hwinfo *hw = mcs->hw; in mcs_alloc_struct_mem()
1085 res->flowid2pf_map = alloc_mem(mcs, hw->tcam_entries); in mcs_alloc_struct_mem()
1089 res->secy2pf_map = alloc_mem(mcs, hw->secy_entries); in mcs_alloc_struct_mem()
1093 res->sc2pf_map = alloc_mem(mcs, hw->sc_entries); in mcs_alloc_struct_mem()
1097 res->sa2pf_map = alloc_mem(mcs, hw->sa_entries); in mcs_alloc_struct_mem()
1101 res->flowid2secy_map = alloc_mem(mcs, hw->tcam_entries); in mcs_alloc_struct_mem()
1105 res->ctrlpktrule2pf_map = alloc_mem(mcs, MCS_MAX_CTRLPKT_RULES); in mcs_alloc_struct_mem()
1137 static int mcs_register_interrupts(struct mcs *mcs) in mcs_register_interrupts() argument
1141 mcs->num_vec = pci_msix_vec_count(mcs->pdev); in mcs_register_interrupts()
1143 ret = pci_alloc_irq_vectors(mcs->pdev, mcs->num_vec, in mcs_register_interrupts()
1144 mcs->num_vec, PCI_IRQ_MSIX); in mcs_register_interrupts()
1146 dev_err(mcs->dev, "MCS Request for %d msix vector failed err:%d\n", in mcs_register_interrupts()
1147 mcs->num_vec, ret); in mcs_register_interrupts()
1151 ret = request_irq(pci_irq_vector(mcs->pdev, mcs->hw->ip_vec), in mcs_register_interrupts()
1152 mcs_ip_intr_handler, 0, "MCS_IP", mcs); in mcs_register_interrupts()
1154 dev_err(mcs->dev, "MCS IP irq registration failed\n"); in mcs_register_interrupts()
1159 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_register_interrupts()
1162 mcs_reg_write(mcs, MCSX_TOP_SLAVE_INT_SUM_ENB, in mcs_register_interrupts()
1167 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT_ENB, 0x7ULL); in mcs_register_interrupts()
1168 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT_ENB, 0x7FULL); in mcs_register_interrupts()
1170 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_ENB, 0xFFULL); in mcs_register_interrupts()
1171 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_ENB, 0xFFULL); in mcs_register_interrupts()
1173 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_ENB, 0xFFFFFULL); in mcs_register_interrupts()
1174 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_ENB, 0xFFFFFULL); in mcs_register_interrupts()
1176 mcs->tx_sa_active = alloc_mem(mcs, mcs->hw->sc_entries); in mcs_register_interrupts()
1177 if (!mcs->tx_sa_active) { in mcs_register_interrupts()
1185 free_irq(pci_irq_vector(mcs->pdev, mcs->hw->ip_vec), mcs); in mcs_register_interrupts()
1187 pci_free_irq_vectors(mcs->pdev); in mcs_register_interrupts()
1188 mcs->num_vec = 0; in mcs_register_interrupts()
1194 struct mcs *mcs; in mcs_get_blkcnt() local
1201 list_for_each_entry(mcs, &mcs_list, mcs_list) in mcs_get_blkcnt()
1202 if (mcs->mcs_id > idmax) in mcs_get_blkcnt()
1203 idmax = mcs->mcs_id; in mcs_get_blkcnt()
1211 struct mcs *mcs_get_pdata(int mcs_id) in mcs_get_pdata()
1213 struct mcs *mcs_dev; in mcs_get_pdata()
1224 struct mcs *mcs_dev; in is_mcs_bypass()
1233 void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req) in mcs_set_port_cfg() argument
1237 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id), in mcs_set_port_cfg()
1242 if (mcs->hw->mcs_blks > 1) { in mcs_set_port_cfg()
1246 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val); in mcs_set_port_cfg()
1247 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id), in mcs_set_port_cfg()
1249 val = mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION); in mcs_set_port_cfg()
1256 mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, val); in mcs_set_port_cfg()
1258 val = mcs_reg_read(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id)); in mcs_set_port_cfg()
1260 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val); in mcs_set_port_cfg()
1264 void mcs_get_port_cfg(struct mcs *mcs, struct mcs_port_cfg_get_req *req, in mcs_get_port_cfg() argument
1269 rsp->port_mode = mcs_reg_read(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id)) & in mcs_get_port_cfg()
1272 if (mcs->hw->mcs_blks > 1) { in mcs_get_port_cfg()
1274 rsp->fifo_skid = mcs_reg_read(mcs, reg) & MCS_PORT_FIFO_SKID_MASK; in mcs_get_port_cfg()
1276 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) & 0x3; in mcs_get_port_cfg()
1277 if (mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION) & BIT_ULL(req->port_id)) in mcs_get_port_cfg()
1281 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) >> 2; in mcs_get_port_cfg()
1288 void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *req, in mcs_get_custom_tag_cfg() argument
1295 if (mcs->hw->mcs_blks > 1) in mcs_get_custom_tag_cfg()
1302 val = mcs_reg_read(mcs, reg); in mcs_get_custom_tag_cfg()
1303 if (mcs->hw->mcs_blks > 1) { in mcs_get_custom_tag_cfg()
1308 rsp->cstm_etype_en = mcs_reg_read(mcs, reg) & 0xFF; in mcs_get_custom_tag_cfg()
1320 void mcs_reset_port(struct mcs *mcs, u8 port_id, u8 reset) in mcs_reset_port() argument
1324 mcs_reg_write(mcs, reg, reset & 0x1); in mcs_reset_port()
1328 void mcs_set_lmac_mode(struct mcs *mcs, int lmac_id, u8 mode) in mcs_set_lmac_mode() argument
1334 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1336 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1339 void mcs_pn_threshold_set(struct mcs *mcs, struct mcs_set_pn_threshold *pn) in mcs_pn_threshold_set() argument
1348 mcs_reg_write(mcs, reg, pn->threshold); in mcs_pn_threshold_set()
1351 void cn10kb_mcs_parser_cfg(struct mcs *mcs) in cn10kb_mcs_parser_cfg() argument
1359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1363 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1373 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1376 static void mcs_lmac_init(struct mcs *mcs, int lmac_id) in mcs_lmac_init() argument
1382 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1384 if (mcs->hw->mcs_blks > 1) { in mcs_lmac_init()
1386 mcs_reg_write(mcs, reg, 0xe000e); in mcs_lmac_init()
1391 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1396 struct mcs *mcs; in mcs_set_lmac_channels() local
1400 mcs = mcs_get_pdata(mcs_id); in mcs_set_lmac_channels()
1401 if (!mcs) in mcs_set_lmac_channels()
1403 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in mcs_set_lmac_channels()
1404 cfg = mcs_reg_read(mcs, MCSX_LINK_LMACX_CFG(lmac)); in mcs_set_lmac_channels()
1408 mcs_reg_write(mcs, MCSX_LINK_LMACX_CFG(lmac), cfg); in mcs_set_lmac_channels()
1414 static int mcs_x2p_calibration(struct mcs *mcs) in mcs_x2p_calibration() argument
1421 val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL); in mcs_x2p_calibration()
1423 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_x2p_calibration()
1426 while (!(mcs_reg_read(mcs, MCSX_MIL_RX_GBL_STATUS) & BIT_ULL(0))) { in mcs_x2p_calibration()
1432 dev_err(mcs->dev, "MCS X2P calibration failed..ignoring\n"); in mcs_x2p_calibration()
1437 val = mcs_reg_read(mcs, MCSX_MIL_RX_GBL_STATUS); in mcs_x2p_calibration()
1438 for (i = 0; i < mcs->hw->mcs_x2p_intf; i++) { in mcs_x2p_calibration()
1442 dev_err(mcs->dev, "MCS:%d didn't respond to X2P calibration\n", i); in mcs_x2p_calibration()
1445 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, mcs_reg_read(mcs, MCSX_MIL_GLOBAL) & ~BIT_ULL(5)); in mcs_x2p_calibration()
1450 static void mcs_set_external_bypass(struct mcs *mcs, bool bypass) in mcs_set_external_bypass() argument
1455 val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL); in mcs_set_external_bypass()
1460 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_set_external_bypass()
1461 mcs->bypass = bypass; in mcs_set_external_bypass()
1464 static void mcs_global_cfg(struct mcs *mcs) in mcs_global_cfg() argument
1467 mcs_set_external_bypass(mcs, false); in mcs_global_cfg()
1470 mcs_reg_write(mcs, MCSX_CSE_RX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1471 mcs_reg_write(mcs, MCSX_CSE_TX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1474 if (mcs->hw->mcs_blks == 1) { in mcs_global_cfg()
1475 mcs_reg_write(mcs, MCSX_IP_MODE, BIT_ULL(3)); in mcs_global_cfg()
1479 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_ENTRY, 0xe4); in mcs_global_cfg()
1480 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_LEN, 4); in mcs_global_cfg()
1483 void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs) in cn10kb_mcs_set_hw_capabilities() argument
1485 struct hwinfo *hw = mcs->hw; in cn10kb_mcs_set_hw_capabilities()
1511 struct mcs *mcs; in mcs_probe() local
1513 mcs = devm_kzalloc(dev, sizeof(*mcs), GFP_KERNEL); in mcs_probe()
1514 if (!mcs) in mcs_probe()
1517 mcs->hw = devm_kzalloc(dev, sizeof(struct hwinfo), GFP_KERNEL); in mcs_probe()
1518 if (!mcs->hw) in mcs_probe()
1534 mcs->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); in mcs_probe()
1535 if (!mcs->reg_base) { in mcs_probe()
1541 pci_set_drvdata(pdev, mcs); in mcs_probe()
1542 mcs->pdev = pdev; in mcs_probe()
1543 mcs->dev = &pdev->dev; in mcs_probe()
1546 mcs->mcs_ops = &cn10kb_mcs_ops; in mcs_probe()
1548 mcs->mcs_ops = cnf10kb_get_mac_ops(); in mcs_probe()
1551 mcs->mcs_ops->mcs_set_hw_capabilities(mcs); in mcs_probe()
1553 mcs_global_cfg(mcs); in mcs_probe()
1556 err = mcs_x2p_calibration(mcs); in mcs_probe()
1560 mcs->mcs_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) in mcs_probe()
1564 err = mcs_alloc_struct_mem(mcs, &mcs->tx); in mcs_probe()
1569 err = mcs_alloc_struct_mem(mcs, &mcs->rx); in mcs_probe()
1574 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) in mcs_probe()
1575 mcs_lmac_init(mcs, lmac); in mcs_probe()
1578 mcs->mcs_ops->mcs_parser_cfg(mcs); in mcs_probe()
1580 err = mcs_register_interrupts(mcs); in mcs_probe()
1584 list_add(&mcs->mcs_list, &mcs_list); in mcs_probe()
1585 mutex_init(&mcs->stats_lock); in mcs_probe()
1591 mcs_set_external_bypass(mcs, true); in mcs_probe()
1601 struct mcs *mcs = pci_get_drvdata(pdev); in mcs_remove() local
1604 mcs_set_external_bypass(mcs, true); in mcs_remove()
1605 free_irq(pci_irq_vector(pdev, mcs->hw->ip_vec), mcs); in mcs_remove()