Lines Matching defs:pe
22 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
28 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
32 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
35 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
37 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]);
40 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
42 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]);
49 struct mvpp2_prs_entry *pe, int tid)
58 memset(pe, 0, sizeof(*pe));
59 pe->index = tid;
62 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
64 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
66 if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
70 pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
73 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
75 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
80 int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
86 err = __mvpp2_prs_init_from_hw(priv, pe, tid);
117 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
119 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK);
120 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);
121 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK);
122 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK);
126 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
130 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port));
132 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port));
136 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
139 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK);
140 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK);
141 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK);
145 unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
147 return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK;
151 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
157 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos);
158 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos);
159 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos;
160 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos);
164 void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
170 *byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff;
171 *enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff;
175 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs,
180 tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff;
185 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe,
195 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i);
197 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i);
200 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable);
204 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe)
206 return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK;
210 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
213 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
214 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
218 static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset,
221 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf);
222 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff);
226 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
229 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num)));
233 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
236 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num)));
240 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
250 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i,
253 mvpp2_prs_sram_bits_clear(pe,
257 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
262 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe)
264 return pe->sram[MVPP2_PRS_SRAM_RI_WORD];
268 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
278 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i,
281 mvpp2_prs_sram_bits_clear(pe,
285 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
290 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
297 bits = (pe->sram[ai_off] >> ai_shift) |
298 (pe->sram[ai_off + 1] << (32 - ai_shift));
306 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
311 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
313 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
319 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
324 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
327 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
331 pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |=
335 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
337 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
340 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
346 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
352 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
355 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
359 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
361 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS,
365 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
367 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
370 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
372 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
376 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
382 struct mvpp2_prs_entry pe;
393 __mvpp2_prs_init_from_hw(priv, &pe, tid);
394 bits = mvpp2_prs_sram_ai_get(&pe);
425 struct mvpp2_prs_entry pe;
428 memset(&pe, 0, sizeof(pe));
431 pe.index = MVPP2_PE_FC_DROP;
432 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
437 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);
439 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
442 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
443 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
446 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
449 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
450 mvpp2_prs_hw_write(priv, &pe);
456 struct mvpp2_prs_entry pe;
460 __mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL);
463 memset(&pe, 0, sizeof(pe));
464 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
465 pe.index = MVPP2_PE_DROP_ALL;
468 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
471 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
472 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
475 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
478 mvpp2_prs_tcam_port_map_set(&pe, 0);
482 mvpp2_prs_tcam_port_set(&pe, port, add);
484 mvpp2_prs_hw_write(priv, &pe);
492 struct mvpp2_prs_entry pe;
511 __mvpp2_prs_init_from_hw(priv, &pe, tid);
513 memset(&pe, 0, sizeof(pe));
514 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
515 pe.index = tid;
518 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
521 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK);
524 mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match,
528 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
532 mvpp2_prs_tcam_port_map_set(&pe, 0);
535 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
539 mvpp2_prs_tcam_port_set(&pe, port, add);
541 mvpp2_prs_hw_write(priv, &pe);
556 struct mvpp2_prs_entry pe;
569 __mvpp2_prs_init_from_hw(priv, &pe, tid);
572 memset(&pe, 0, sizeof(pe));
573 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
574 pe.index = tid;
577 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
581 mvpp2_prs_tcam_data_byte_set(&pe, 0,
587 mvpp2_prs_sram_ai_update(&pe, 1,
590 mvpp2_prs_sram_ai_update(&pe, 0,
594 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,
597 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
600 mvpp2_prs_sram_shift_set(&pe, shift,
604 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
606 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
610 mvpp2_prs_tcam_port_map_set(&pe, 0);
614 mvpp2_prs_tcam_port_set(&pe, port, add);
616 mvpp2_prs_hw_write(priv, &pe);
623 struct mvpp2_prs_entry pe;
640 __mvpp2_prs_init_from_hw(priv, &pe, tid);
643 memset(&pe, 0, sizeof(pe));
644 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
645 pe.index = tid;
648 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA);
649 mvpp2_prs_match_etype(&pe, 2, 0);
651 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK,
654 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift,
658 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA);
662 mvpp2_prs_tcam_data_byte_set(&pe,
667 mvpp2_prs_sram_ai_update(&pe, 0,
670 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
673 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
675 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
678 mvpp2_prs_tcam_port_map_set(&pe, port_mask);
682 mvpp2_prs_tcam_port_set(&pe, port, add);
684 mvpp2_prs_hw_write(priv, &pe);
690 struct mvpp2_prs_entry pe;
703 __mvpp2_prs_init_from_hw(priv, &pe, tid);
704 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid);
709 ri_bits = mvpp2_prs_sram_ri_get(&pe);
713 ai_bits = mvpp2_prs_tcam_ai_get(&pe);
732 struct mvpp2_prs_entry pe;
736 memset(&pe, 0, sizeof(pe));
756 __mvpp2_prs_init_from_hw(priv, &pe, tid_aux);
757 ri_bits = mvpp2_prs_sram_ri_get(&pe);
766 memset(&pe, 0, sizeof(pe));
767 pe.index = tid;
768 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
770 mvpp2_prs_match_etype(&pe, 0, tpid);
773 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
776 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
779 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE,
783 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE,
786 mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK);
788 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
790 __mvpp2_prs_init_from_hw(priv, &pe, tid);
793 mvpp2_prs_tcam_port_map_set(&pe, port_map);
795 mvpp2_prs_hw_write(priv, &pe);
817 struct mvpp2_prs_entry pe;
830 __mvpp2_prs_init_from_hw(priv, &pe, tid);
832 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) &&
833 mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2);
838 ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK;
852 struct mvpp2_prs_entry pe;
854 memset(&pe, 0, sizeof(pe));
879 __mvpp2_prs_init_from_hw(priv, &pe, tid_aux);
880 ri_bits = mvpp2_prs_sram_ri_get(&pe);
890 memset(&pe, 0, sizeof(pe));
891 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
892 pe.index = tid;
896 mvpp2_prs_match_etype(&pe, 0, tpid1);
897 mvpp2_prs_match_etype(&pe, 4, tpid2);
899 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
901 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
903 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
905 mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT,
908 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
910 __mvpp2_prs_init_from_hw(priv, &pe, tid);
914 mvpp2_prs_tcam_port_map_set(&pe, port_map);
915 mvpp2_prs_hw_write(priv, &pe);
924 struct mvpp2_prs_entry pe;
937 memset(&pe, 0, sizeof(pe));
938 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
939 pe.index = tid;
942 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
943 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
946 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4,
948 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
949 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK);
951 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00,
953 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00,
956 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK);
957 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
960 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
963 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
964 mvpp2_prs_hw_write(priv, &pe);
972 pe.index = tid;
974 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
975 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
976 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
978 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE,
981 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0);
982 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0);
985 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
986 mvpp2_prs_hw_write(priv, &pe);
994 struct mvpp2_prs_entry pe;
1002 memset(&pe, 0, sizeof(pe));
1003 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1004 pe.index = tid;
1008 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC,
1010 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
1015 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask);
1016 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask);
1017 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask);
1018 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask);
1019 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST,
1027 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1029 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1033 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1035 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1038 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1041 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1042 mvpp2_prs_hw_write(priv, &pe);
1051 struct mvpp2_prs_entry pe;
1063 memset(&pe, 0, sizeof(pe));
1064 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1065 pe.index = tid;
1068 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1069 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1070 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask);
1071 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1075 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK);
1076 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1079 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1082 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
1083 mvpp2_prs_hw_write(priv, &pe);
1091 struct mvpp2_prs_entry pe;
1102 memset(&pe, 0, sizeof(pe));
1103 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1104 pe.index = tid;
1107 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1108 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST,
1110 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1113 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1115 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC,
1117 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
1119 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1122 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
1123 mvpp2_prs_hw_write(priv, &pe);
1158 struct mvpp2_prs_entry pe;
1162 memset(&pe, 0, sizeof(pe));
1163 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1164 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1167 mvpp2_prs_tcam_port_map_set(&pe, 0);
1170 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1171 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1174 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1175 mvpp2_prs_hw_write(priv, &pe);
1182 struct mvpp2_prs_entry pe;
1184 memset(&pe, 0, sizeof(pe));
1186 pe.index = MVPP2_PE_MH_DEFAULT;
1187 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1188 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1190 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1193 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1196 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1197 mvpp2_prs_hw_write(priv, &pe);
1200 pe.index = MVPP2_PE_MH_SKIP_PRS;
1201 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1202 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1204 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1205 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1208 mvpp2_prs_tcam_port_map_set(&pe, 0);
1211 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1212 mvpp2_prs_hw_write(priv, &pe);
1220 struct mvpp2_prs_entry pe;
1222 memset(&pe, 0, sizeof(pe));
1225 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1226 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1228 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1230 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1231 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1234 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1237 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1238 mvpp2_prs_hw_write(priv, &pe);
1250 struct mvpp2_prs_entry pe;
1283 memset(&pe, 0, sizeof(pe));
1284 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA);
1285 pe.index = MVPP2_PE_DSA_DEFAULT;
1286 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1289 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1290 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1293 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1296 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1298 mvpp2_prs_hw_write(priv, &pe);
1304 struct mvpp2_prs_entry pe;
1306 memset(&pe, 0, sizeof(pe));
1309 pe.index = MVPP2_PE_VID_FLTR_DEFAULT;
1310 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
1312 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT);
1315 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN,
1319 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1321 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1324 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1327 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
1328 mvpp2_prs_hw_write(priv, &pe);
1331 memset(&pe, 0, sizeof(pe));
1334 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT;
1335 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
1337 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT,
1341 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN,
1345 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1347 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1350 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1353 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
1354 mvpp2_prs_hw_write(priv, &pe);
1360 struct mvpp2_prs_entry pe;
1369 memset(&pe, 0, sizeof(pe));
1370 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1371 pe.index = tid;
1373 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES);
1375 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1377 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1378 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1382 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1383 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1384 priv->prs_shadow[pe.index].finish = false;
1385 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1387 mvpp2_prs_hw_write(priv, &pe);
1395 memset(&pe, 0, sizeof(pe));
1396 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1397 pe.index = tid;
1399 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP);
1402 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1403 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1404 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1407 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1412 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1413 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1414 priv->prs_shadow[pe.index].finish = true;
1415 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1417 mvpp2_prs_hw_write(priv, &pe);
1425 memset(&pe, 0, sizeof(pe));
1426 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1427 pe.index = tid;
1429 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1432 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1433 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1434 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1439 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1444 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1445 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1446 priv->prs_shadow[pe.index].finish = true;
1447 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1451 mvpp2_prs_hw_write(priv, &pe);
1460 memset(&pe, 0, sizeof(pe));
1461 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1462 pe.index = tid;
1464 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP);
1465 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1470 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1471 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1474 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1478 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1483 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1484 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1485 priv->prs_shadow[pe.index].finish = false;
1486 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1488 mvpp2_prs_hw_write(priv, &pe);
1497 memset(&pe, 0, sizeof(pe));
1498 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1499 pe.index = tid;
1501 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6);
1504 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1507 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1508 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1511 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1515 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1516 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1517 priv->prs_shadow[pe.index].finish = false;
1518 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
1520 mvpp2_prs_hw_write(priv, &pe);
1523 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1524 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1525 pe.index = MVPP2_PE_ETH_TYPE_UN;
1528 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1531 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1532 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1533 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1536 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1541 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1542 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1543 priv->prs_shadow[pe.index].finish = true;
1544 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
1546 mvpp2_prs_hw_write(priv, &pe);
1560 struct mvpp2_prs_entry pe;
1588 memset(&pe, 0, sizeof(pe));
1589 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1590 pe.index = MVPP2_PE_VLAN_DBL;
1592 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID);
1595 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
1596 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE,
1599 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT,
1602 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1605 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
1606 mvpp2_prs_hw_write(priv, &pe);
1609 memset(&pe, 0, sizeof(pe));
1610 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN);
1611 pe.index = MVPP2_PE_VLAN_NONE;
1613 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
1614 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE,
1618 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1621 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN);
1622 mvpp2_prs_hw_write(priv, &pe);
1630 struct mvpp2_prs_entry pe;
1640 memset(&pe, 0, sizeof(pe));
1641 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1642 pe.index = tid;
1644 mvpp2_prs_match_etype(&pe, 0, PPP_IP);
1645 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1650 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1651 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1654 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN +
1658 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1662 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1667 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1668 mvpp2_prs_hw_write(priv, &pe);
1677 memset(&pe, 0, sizeof(pe));
1678 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1679 pe.index = tid;
1681 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6);
1683 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1684 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1687 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1691 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1696 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1697 mvpp2_prs_hw_write(priv, &pe);
1705 memset(&pe, 0, sizeof(pe));
1706 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1707 pe.index = tid;
1709 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1713 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1714 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1716 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1721 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE);
1722 mvpp2_prs_hw_write(priv, &pe);
1730 struct mvpp2_prs_entry pe;
1763 memset(&pe, 0, sizeof(pe));
1764 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1765 pe.index = MVPP2_PE_IP4_PROTO_UN;
1768 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1769 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1772 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4,
1774 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1775 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
1778 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1781 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1784 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1785 mvpp2_prs_hw_write(priv, &pe);
1788 memset(&pe, 0, sizeof(pe));
1789 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4);
1790 pe.index = MVPP2_PE_IP4_ADDR_UN;
1793 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1795 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT,
1799 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1801 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
1803 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT);
1806 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1809 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1810 mvpp2_prs_hw_write(priv, &pe);
1818 struct mvpp2_prs_entry pe;
1861 memset(&pe, 0, sizeof(pe));
1862 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1863 pe.index = tid;
1866 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1867 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1868 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN |
1873 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK);
1874 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1878 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1879 mvpp2_prs_hw_write(priv, &pe);
1882 memset(&pe, 0, sizeof(pe));
1883 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1884 pe.index = MVPP2_PE_IP6_PROTO_UN;
1887 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1888 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1889 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
1892 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4,
1896 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1899 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1902 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1903 mvpp2_prs_hw_write(priv, &pe);
1906 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1907 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1908 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN;
1911 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1912 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1913 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER,
1916 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT,
1919 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1922 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4);
1923 mvpp2_prs_hw_write(priv, &pe);
1926 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1927 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6);
1928 pe.index = MVPP2_PE_IP6_ADDR_UN;
1931 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1932 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST,
1934 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT,
1937 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1939 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT);
1941 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1944 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6);
1945 mvpp2_prs_hw_write(priv, &pe);
1954 struct mvpp2_prs_entry pe;
1965 __mvpp2_prs_init_from_hw(port->priv, &pe, tid);
1967 mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]);
1968 mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]);
1989 struct mvpp2_prs_entry pe;
1992 memset(&pe, 0, sizeof(pe));
2019 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
2020 pe.index = tid;
2023 mvpp2_prs_tcam_port_map_set(&pe, 0);
2025 __mvpp2_prs_init_from_hw(priv, &pe, tid);
2029 mvpp2_prs_tcam_port_set(&pe, port->id, true);
2032 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2035 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2038 mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid);
2041 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2044 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
2045 mvpp2_prs_hw_write(priv, &pe);
2110 struct mvpp2_prs_entry pe;
2115 memset(&pe, 0, sizeof(pe));
2119 pe.index = tid;
2127 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID);
2130 mvpp2_prs_tcam_port_map_set(&pe, 0);
2133 mvpp2_prs_tcam_port_set(&pe, port->id, true);
2136 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2);
2139 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2142 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
2146 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK);
2149 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID);
2150 mvpp2_prs_hw_write(priv, &pe);
2218 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2225 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2241 struct mvpp2_prs_entry pe;
2254 __mvpp2_prs_init_from_hw(priv, &pe, tid);
2255 entry_pmap = mvpp2_prs_tcam_port_map_get(&pe);
2257 if (mvpp2_prs_mac_range_equals(&pe, da, mask) &&
2272 struct mvpp2_prs_entry pe;
2275 memset(&pe, 0, sizeof(pe));
2294 pe.index = tid;
2297 mvpp2_prs_tcam_port_map_set(&pe, 0);
2299 __mvpp2_prs_init_from_hw(priv, &pe, tid);
2302 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
2305 mvpp2_prs_tcam_port_set(&pe, port->id, add);
2308 pmap = mvpp2_prs_tcam_port_map_get(&pe);
2313 mvpp2_prs_hw_inv(priv, pe.index);
2314 priv->prs_shadow[pe.index].valid = false;
2319 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
2324 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);
2338 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2340 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2344 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
2348 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF;
2349 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
2350 mvpp2_prs_hw_write(priv, &pe);
2390 struct mvpp2_prs_entry pe;
2405 __mvpp2_prs_init_from_hw(priv, &pe, tid);
2407 pmap = mvpp2_prs_tcam_port_map_get(&pe);
2415 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index],
2490 struct mvpp2_prs_entry pe;
2494 memset(&pe, 0, sizeof(pe));
2506 pe.index = tid;
2511 mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK);
2512 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2515 mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i],
2519 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
2520 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2521 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2522 mvpp2_prs_hw_write(priv, &pe);
2531 struct mvpp2_prs_entry pe;
2534 memset(&pe, 0, sizeof(pe));
2551 pe.index = tid;
2554 mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2555 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2558 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS);
2560 __mvpp2_prs_init_from_hw(port->priv, &pe, tid);
2563 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2564 mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id));
2565 mvpp2_prs_hw_write(port->priv, &pe);