Lines Matching +full:0 +full:xc400
13 REG_SWITCH_CNTRL = 0,
36 #define MDIO_MASTER_SEL (1 << 0)
39 #define SF2_REV_MASK 0xffff
41 #define SWITCH_TOP_REV_MASK 0xffff
44 #define PHY_REVISION_MASK 0xffff
47 #define IDDQ_BIAS (1 << 0)
54 #define PHY_PHYAD_MASK 0x1F
57 #define CROSSBAR_BCM4908_INT_P7 0
59 #define CROSSBAR_BCM4908_EXT_SERDES 0
64 #define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
81 #define LED_CNTRL_MASK 0x3
84 #define REG_LED_CTRL 0x0
85 #define LED_CTRL_RX_ACT_EN 0x00000001
86 #define LED_CTRL_TX_ACT_EN 0x00000002
87 #define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004
88 #define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008
89 #define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010
90 #define LED_CTRL_ACT_LED_ACT_SEL 0x00000020
91 #define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040
92 #define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080
93 #define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100
94 #define LED_CTRL_ACT_LED_POL_SEL 0x00000200
95 #define LED_CTRL_LED_SPD_OVRD 0x00001c00
96 #define LED_CTRL_LNK_STATUS_OVRD 0x00002000
97 #define LED_CTRL_SPD_OVRD_EN 0x00004000
98 #define LED_CTRL_LNK_OVRD_EN 0x00008000
101 #define REG_LED_LINK_SPEED_ENC_SEL 0x4
102 #define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0
108 #define LED_LINK_SPEED_ENC_SEL_MASK 0x7
111 #define REG_LED_LINK_SPEED_ENC 0x8
112 #define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0
118 #define LED_LINK_SPEED_ENC_MASK 0x7
121 #define RGMII_MODE_EN (1 << 0)
124 #define INT_EPHY (0 << PORT_MODE_SHIFT)
129 #define PORT_MODE_MASK 0x7
135 #define LPI_COUNT_MASK 0x3F
138 #define INTRL2_CPU_STATUS 0x00
139 #define INTRL2_CPU_SET 0x04
140 #define INTRL2_CPU_CLEAR 0x08
141 #define INTRL2_CPU_MASK_STATUS 0x0c
142 #define INTRL2_CPU_MASK_SET 0x10
143 #define INTRL2_CPU_MASK_CLEAR 0x14
146 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
159 #define P0_IRQ_OFF 0
175 #define P7_IRQ_OFF 0
179 #define ACB_CONTROL 0x00
180 #define ACB_EN (1 << 0)
183 #define ACB_FLUSH_MASK 0x3
185 #define ACB_QUEUE_0_CFG 0x08
186 #define XOFF_THRESHOLD_MASK 0x7ff
189 #define TOTAL_XOFF_THRESHOLD_MASK 0x7ff
193 #define PKTLEN_MASK 0x3f
194 #define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4))
197 #define CORE_G_PCTL_PORT0 0x00000
198 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
199 #define CORE_IMP_CTL 0x00020
200 #define RX_DIS (1 << 0)
206 #define CORE_SWMODE 0x0002c
207 #define SW_FWDG_MODE (1 << 0)
211 #define CORE_STS_OVERRIDE_IMP 0x00038
216 #define CORE_STS_OVERRIDE_IMP2 0x39040
218 #define CORE_NEW_CTRL 0x00084
219 #define IP_MC (1 << 0)
228 #define CORE_SWITCH_CTRL 0x00088
231 #define CORE_DIS_LEARN 0x000f0
233 #define CORE_SFT_LRN_CTRL 0x000f8
236 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
237 #define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
238 #define LINK_STS (1 << 0)
241 #define SPEED_MASK 0x3
246 #define CORE_WATCHDOG_CTRL 0x001e4
251 #define CORE_FAST_AGE_CTRL 0x00220
252 #define EN_FAST_AGE_STATIC (1 << 0)
260 #define CORE_FAST_AGE_PORT 0x00224
261 #define AGE_PORT_MASK 0xf
263 #define CORE_FAST_AGE_VID 0x00228
264 #define AGE_VID_MASK 0x3fff
266 #define CORE_LNKSTS 0x00400
267 #define LNK_STS_MASK 0x1ff
269 #define CORE_SPDSTS 0x00410
270 #define SPDSTS_10 0
274 #define SPDSTS_MASK 0x3
276 #define CORE_DUPSTS 0x00420
277 #define CORE_DUPSTS_MASK 0x1ff
279 #define CORE_PAUSESTS 0x00428
282 #define CORE_GMNCFGCFG 0x0800
283 #define RST_MIB_CNT (1 << 0)
286 #define CORE_IMP0_PRT_ID 0x0804
288 #define CORE_RST_MIB_CNT_EN 0x0950
290 #define CORE_ARLA_VTBL_RWCTRL 0x1600
291 #define ARLA_VTBL_CMD_WRITE 0
296 #define CORE_ARLA_VTBL_ADDR 0x1604
297 #define VTBL_ADDR_INDEX_MASK 0xfff
299 #define CORE_ARLA_VTBL_ENTRY 0x160c
300 #define FWD_MAP_MASK 0x1ff
301 #define UNTAG_MAP_MASK 0x1ff
303 #define MSTP_INDEX_MASK 0x7
307 #define CORE_MEM_PSM_VDD_CTRL 0x2380
309 #define P_TXQ_PSM_VDD_MASK 0x3
313 #define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
314 #define PRT_TO_QID_MASK 0x3
317 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
318 #define PORT_VLAN_CTRL_MASK 0x1ff
320 #define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80
321 #define TXQ_PAUSE_THD_MASK 0x7ff
323 (x) * 0x8)
325 #define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
328 #define PRI_MASK 0x7
330 #define CORE_JOIN_ALL_VLAN_EN 0xd140
332 #define CORE_CFP_ACC 0x28000
333 #define OP_STR_DONE (1 << 0)
347 #define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
350 #define XCESS_ADDR_MASK 0xff
358 #define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
360 #define CORE_CFP_DATA_PORT_0 0x28040
362 (x) * 0x10)
366 #define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
368 #define IPTOS_MASK 0xff
370 #define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
378 #define SLICE_NUM_MASK 0x3
380 #define CORE_CFP_MASK_PORT_0 0x280c0
383 (x) * 0x10)
385 #define CORE_ACT_POL_DATA0 0x28140
386 #define VLAN_BYP (1 << 0)
390 #define REASON_CODE_MASK 0x3f
393 #define NEW_TC_MASK 0x7
396 #define DST_MAP_IB_MASK 0x1ff
398 #define CHANGE_FWRD_MAP_IB_MASK 0x3
399 #define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
404 #define NEW_DSCP_IB_MASK 0x3f
406 #define CORE_ACT_POL_DATA1 0x28150
407 #define CHANGE_DSCP_IB (1 << 0)
409 #define DST_MAP_OB_MASK 0x3ff
411 #define CHANGE_FWRD_MAP_OB_MASK 0x3
413 #define NEW_DSCP_OB_MASK 0x3f
416 #define CHAIN_ID_MASK 0xff
419 #define NEW_COLOR_MASK 0x3
420 #define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
425 #define CORE_ACT_POL_DATA2 0x28160
426 #define MAC_LIMIT_BYPASS (1 << 0)
429 #define NEW_TC_O_MASK 0x7
434 #define CORE_RATE_METER0 0x28180
435 #define COLOR_MODE (1 << 0)
439 #define POLICER_MODE_MASK 0x3
440 #define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
445 #define CORE_RATE_METER1 0x28190
446 #define EIR_TK_BKT_MASK 0x7fffff
448 #define CORE_RATE_METER2 0x281a0
449 #define EIR_BKT_SIZE_MASK 0xfffff
451 #define CORE_RATE_METER3 0x281b0
452 #define EIR_REF_CNT_MASK 0x7ffff
454 #define CORE_RATE_METER4 0x281c0
455 #define CIR_TK_BKT_MASK 0x7fffff
457 #define CORE_RATE_METER5 0x281d0
458 #define CIR_BKT_SIZE_MASK 0xfffff
460 #define CORE_RATE_METER6 0x281e0
461 #define CIR_REF_CNT_MASK 0x7ffff
463 #define CORE_STAT_GREEN_CNTR 0x28200
464 #define CORE_STAT_YELLOW_CNTR 0x28210
465 #define CORE_STAT_RED_CNTR 0x28220
467 #define CORE_CFP_CTL_REG 0x28400
468 #define CFP_EN_MAP_MASK 0x1ff
471 #define CORE_UDF_0_A_0_8_PORT_0 0x28440
472 #define CFG_UDF_OFFSET_MASK 0x1f
474 #define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
479 #define CORE_UDF_0_B_0_8_PORT_0 0x28500
482 #define CORE_UDF_0_D_0_11_PORT_0 0x28680
489 #define UDF_SLICE_OFFSET 0x40