Lines Matching +full:0 +full:x01c2bc00
67 /* Registers address (physical base address 0x01C2BC00) */
68 #define SUN4I_REG_MSEL_ADDR 0x0000 /* CAN Mode Select */
69 #define SUN4I_REG_CMD_ADDR 0x0004 /* CAN Command */
70 #define SUN4I_REG_STA_ADDR 0x0008 /* CAN Status */
71 #define SUN4I_REG_INT_ADDR 0x000c /* CAN Interrupt Flag */
72 #define SUN4I_REG_INTEN_ADDR 0x0010 /* CAN Interrupt Enable */
73 #define SUN4I_REG_BTIME_ADDR 0x0014 /* CAN Bus Timing 0 */
74 #define SUN4I_REG_TEWL_ADDR 0x0018 /* CAN Tx Error Warning Limit */
75 #define SUN4I_REG_ERRC_ADDR 0x001c /* CAN Error Counter */
76 #define SUN4I_REG_RMCNT_ADDR 0x0020 /* CAN Receive Message Counter */
77 #define SUN4I_REG_RBUFSA_ADDR 0x0024 /* CAN Receive Buffer Start Address */
78 #define SUN4I_REG_BUF0_ADDR 0x0040 /* CAN Tx/Rx Buffer 0 */
79 #define SUN4I_REG_BUF1_ADDR 0x0044 /* CAN Tx/Rx Buffer 1 */
80 #define SUN4I_REG_BUF2_ADDR 0x0048 /* CAN Tx/Rx Buffer 2 */
81 #define SUN4I_REG_BUF3_ADDR 0x004c /* CAN Tx/Rx Buffer 3 */
82 #define SUN4I_REG_BUF4_ADDR 0x0050 /* CAN Tx/Rx Buffer 4 */
83 #define SUN4I_REG_BUF5_ADDR 0x0054 /* CAN Tx/Rx Buffer 5 */
84 #define SUN4I_REG_BUF6_ADDR 0x0058 /* CAN Tx/Rx Buffer 6 */
85 #define SUN4I_REG_BUF7_ADDR 0x005c /* CAN Tx/Rx Buffer 7 */
86 #define SUN4I_REG_BUF8_ADDR 0x0060 /* CAN Tx/Rx Buffer 8 */
87 #define SUN4I_REG_BUF9_ADDR 0x0064 /* CAN Tx/Rx Buffer 9 */
88 #define SUN4I_REG_BUF10_ADDR 0x0068 /* CAN Tx/Rx Buffer 10 */
89 #define SUN4I_REG_BUF11_ADDR 0x006c /* CAN Tx/Rx Buffer 11 */
90 #define SUN4I_REG_BUF12_ADDR 0x0070 /* CAN Tx/Rx Buffer 12 */
91 #define SUN4I_REG_ACPC_ADDR 0x0040 /* CAN Acceptance Code 0 */
92 #define SUN4I_REG_ACPM_ADDR 0x0044 /* CAN Acceptance Mask 0 */
93 #define SUN4I_REG_ACPC_ADDR_D1 0x0028 /* CAN Acceptance Code 0 on the D1 */
94 #define SUN4I_REG_ACPM_ADDR_D1 0x002C /* CAN Acceptance Mask 0 on the D1 */
95 #define SUN4I_REG_RBUF_RBACK_START_ADDR 0x0180 /* CAN transmit buffer start */
96 #define SUN4I_REG_RBUF_RBACK_END_ADDR 0x01b0 /* CAN transmit buffer end */
101 * offset:0x0000 default:0x0000_0001
103 #define SUN4I_MSEL_SLEEP_MODE (0x01 << 4) /* write in reset mode */
104 #define SUN4I_MSEL_WAKE_UP (0x00 << 4)
105 #define SUN4I_MSEL_SINGLE_FILTER (0x01 << 3) /* write in reset mode */
106 #define SUN4I_MSEL_DUAL_FILTERS (0x00 << 3)
109 #define SUN4I_MSEL_RESET_MODE BIT(0)
112 * offset:0x0004 default:0x0000_0000
119 #define SUN4I_CMD_TRANS_REQ BIT(0)
122 * offset:0x0008 default:0x0000_003c
124 #define SUN4I_STA_BIT_ERR (0x00 << 22)
125 #define SUN4I_STA_FORM_ERR (0x01 << 22)
126 #define SUN4I_STA_STUFF_ERR (0x02 << 22)
127 #define SUN4I_STA_OTHER_ERR (0x03 << 22)
128 #define SUN4I_STA_MASK_ERR (0x03 << 22)
130 #define SUN4I_STA_ERR_SEG_CODE (0x1f << 16)
131 #define SUN4I_STA_START (0x03 << 16)
132 #define SUN4I_STA_ID28_21 (0x02 << 16)
133 #define SUN4I_STA_ID20_18 (0x06 << 16)
134 #define SUN4I_STA_SRTR (0x04 << 16)
135 #define SUN4I_STA_IDE (0x05 << 16)
136 #define SUN4I_STA_ID17_13 (0x07 << 16)
137 #define SUN4I_STA_ID12_5 (0x0f << 16)
138 #define SUN4I_STA_ID4_0 (0x0e << 16)
139 #define SUN4I_STA_RTR (0x0c << 16)
140 #define SUN4I_STA_RB1 (0x0d << 16)
141 #define SUN4I_STA_RB0 (0x09 << 16)
142 #define SUN4I_STA_DLEN (0x0b << 16)
143 #define SUN4I_STA_DATA_FIELD (0x0a << 16)
144 #define SUN4I_STA_CRC_SEQUENCE (0x08 << 16)
145 #define SUN4I_STA_CRC_DELIMITER (0x18 << 16)
146 #define SUN4I_STA_ACK (0x19 << 16)
147 #define SUN4I_STA_ACK_DELIMITER (0x1b << 16)
148 #define SUN4I_STA_END (0x1a << 16)
149 #define SUN4I_STA_INTERMISSION (0x12 << 16)
150 #define SUN4I_STA_ACTIVE_ERROR (0x11 << 16)
151 #define SUN4I_STA_PASSIVE_ERROR (0x16 << 16)
152 #define SUN4I_STA_TOLERATE_DOMINANT_BITS (0x13 << 16)
153 #define SUN4I_STA_ERROR_DELIMITER (0x17 << 16)
154 #define SUN4I_STA_OVERLOAD (0x1c << 16)
162 #define SUN4I_STA_RBUF_RDY BIT(0)
165 * offset:0x000c default:0x0000_0000
174 #define SUN4I_INT_RBUF_VLD BIT(0)
177 * offset:0x0010 default:0x0000_0000
186 #define SUN4I_INTEN_RX BIT(0)
189 #define SUN4I_ERR_INRCV (0x1 << 5)
190 #define SUN4I_ERR_INTRANS (0x0 << 5)
193 #define SUN4I_FILTER_CLOSE 0
250 u32 mod_reg_val = 0; in set_normal_mode()
264 return 0; in set_normal_mode()
271 u32 mod_reg_val = 0; in set_reset_mode()
285 return 0; in set_reset_mode()
295 cfg = ((bt->brp - 1) & 0x3FF) | in sun4ican_set_bittiming()
296 (((bt->sjw - 1) & 0x3) << 14) | in sun4ican_set_bittiming()
297 (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) | in sun4ican_set_bittiming()
298 (((bt->phase_seg2 - 1) & 0x7) << 20); in sun4ican_set_bittiming()
300 cfg |= 0x800000; in sun4ican_set_bittiming()
302 netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg); in sun4ican_set_bittiming()
305 return 0; in sun4ican_set_bittiming()
323 bec->txerr = errors & 0xFF; in sun4ican_get_berr_counter()
324 bec->rxerr = (errors >> 16) & 0xFF; in sun4ican_get_berr_counter()
328 return 0; in sun4ican_get_berr_counter()
345 writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv->acp_offset); in sun4i_can_start()
346 writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv->acp_offset); in sun4i_can_start()
349 writel(0, priv->base + SUN4I_REG_ERRC_ADDR); in sun4i_can_start()
353 writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR); in sun4i_can_start()
355 writel(0xFF & ~SUN4I_INTEN_BERR, in sun4i_can_start()
379 return 0; in sun4i_can_start()
396 writel(0, priv->base + SUN4I_REG_INTEN_ADDR); in sun4i_can_stop()
398 return 0; in sun4i_can_stop()
419 return 0; in sun4ican_set_mode()
451 writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); in sun4ican_start_xmit()
452 writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR); in sun4ican_start_xmit()
453 writel((id >> 5) & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR); in sun4ican_start_xmit()
454 writel((id << 3) & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR); in sun4ican_start_xmit()
457 writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR); in sun4ican_start_xmit()
458 writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR); in sun4ican_start_xmit()
461 for (i = 0; i < dlc; i++) in sun4ican_start_xmit()
466 can_put_echo_skb(skb, dev, 0, 0); in sun4ican_start_xmit()
493 cf->len = can_cc_dlc2len(fi & 0x0F); in sun4i_can_rx()
499 ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3) & 0x1f); in sun4i_can_rx()
504 ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7); in sun4i_can_rx()
511 for (i = 0; i < cf->len; i++) in sun4i_can_rx()
540 rxerr = (errc >> 16) & 0xFF; in sun4i_can_err()
541 txerr = errc & 0xFF; in sun4i_can_err()
605 if ((ecc & SUN4I_STA_ERR_DIR) == 0) { in sun4i_can_err()
628 cf->data[0] = (alc >> 8) & 0x1f; in sun4i_can_err()
633 tx_state = txerr >= rxerr ? state : 0; in sun4i_can_err()
634 rx_state = txerr <= rxerr ? state : 0; in sun4i_can_err()
649 return 0; in sun4i_can_err()
658 int n = 0; in sun4i_can_interrupt()
670 stats->tx_bytes += can_get_echo_skb(dev, 0, NULL); in sun4i_can_interrupt()
711 err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev); in sun4ican_open()
739 return 0; in sun4ican_open()
764 return 0; in sun4ican_close()
779 .acp_offset = 0,
784 .acp_offset = 0,
847 clk = of_clk_get(np, 0); in sun4ican_probe()
854 irq = platform_get_irq(pdev, 0); in sun4ican_probe()
855 if (irq < 0) { in sun4ican_probe()
860 addr = devm_platform_ioremap_resource(pdev, 0); in sun4ican_probe()
907 return 0; in sun4ican_probe()