27 #define CORE_MCI_VERSION		0x50
29 #define CORE_VERSION_MAJOR_MASK		(0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK		0xff
32 #define CORE_MCI_GENERICS		0x70
35 #define HC_MODE_EN		0x1
36 #define CORE_POWER		0x0
40 #define CORE_PWRCTL_BUS_OFF	BIT(0)
44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
48 #define REQ_BUS_OFF		BIT(0)
52 #define INT_MASK		0xf
62 #define CORE_CMD_DAT_TRACK_SEL	BIT(0)
64 #define CORE_DDR_CAL_EN		BIT(0)
68 #define DLL_USR_CTL_POR_VAL	0x10800
73 #define DLL_CONFIG_3_LOW_FREQ_VAL	0x08
74 #define DLL_CONFIG_3_HIGH_FREQ_VAL	0x10
76 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
91 #define CORE_CSR_CDC_CTLR_CFG0		0x130
95 #define CORE_CSR_CDC_CTLR_CFG1		0x134
96 #define CORE_CSR_CDC_CAL_TIMER_CFG0	0x138
99 #define CORE_CSR_CDC_CAL_TIMER_CFG1	0x13C
100 #define CORE_CSR_CDC_REFCOUNT_CFG	0x140
101 #define CORE_CSR_CDC_COARSE_CAL_CFG	0x144
102 #define CORE_CDC_OFFSET_CFG		0x14C
103 #define CORE_CSR_CDC_DELAY_CFG		0x150
104 #define CORE_CDC_SLAVE_DDA_CFG		0x160
105 #define CORE_CSR_CDC_STATUS0		0x164
106 #define CORE_CALIBRATION_DONE		BIT(0)
108 #define CORE_CDC_ERROR_CODE_MASK	0x7000000
110 #define CORE_CSR_CDC_GEN_CFG		0x178
111 #define CORE_CDC_SWITCH_BYPASS_OFF	BIT(0)
114 #define CORE_CDC_T4_DLY_SEL		BIT(0)
120 #define DDR_CONFIG_POR_VAL	0x80040873
128 #define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)
156 #define CQHCI_VENDOR_CFG1	0xA00
157 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN	(0x3 << 13)
186 	u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
192 	.core_mci_data_cnt = 0x35c,
193 	.core_mci_status = 0x324,
194 	.core_mci_fifo_cnt = 0x308,
195 	.core_mci_version = 0x318,
196 	.core_generics = 0x320,
197 	.core_testbus_config = 0x32c,
201 	.core_pwrctl_status = 0x240,
202 	.core_pwrctl_mask = 0x244,
203 	.core_pwrctl_clear = 0x248,
204 	.core_pwrctl_ctl = 0x24c,
205 	.core_sdcc_debug_reg = 0x358,
206 	.core_dll_config = 0x200,
207 	.core_dll_status = 0x208,
208 	.core_vendor_spec = 0x20c,
209 	.core_vendor_spec_adma_err_addr0 = 0x214,
210 	.core_vendor_spec_adma_err_addr1 = 0x218,
211 	.core_vendor_spec_func2 = 0x210,
212 	.core_vendor_spec_capabilities0 = 0x21c,
213 	.core_ddr_200_cfg = 0x224,
214 	.core_vendor_spec3 = 0x250,
215 	.core_dll_config_2 = 0x254,
216 	.core_dll_config_3 = 0x258,
217 	.core_ddr_config = 0x25c,
218 	.core_dll_usr_ctl = 0x388,
222 	.core_hc_mode = 0x78,
223 	.core_mci_data_cnt = 0x30,
224 	.core_mci_status = 0x34,
225 	.core_mci_fifo_cnt = 0x44,
226 	.core_mci_version = 0x050,
227 	.core_generics = 0x70,
228 	.core_testbus_config = 0x0cc,
232 	.core_pwrctl_status = 0xdc,
233 	.core_pwrctl_mask = 0xe0,
234 	.core_pwrctl_clear = 0xe4,
235 	.core_pwrctl_ctl = 0xe8,
236 	.core_sdcc_debug_reg = 0x124,
237 	.core_dll_config = 0x100,
238 	.core_dll_status = 0x108,
239 	.core_vendor_spec = 0x10c,
240 	.core_vendor_spec_adma_err_addr0 = 0x114,
241 	.core_vendor_spec_adma_err_addr1 = 0x118,
242 	.core_vendor_spec_func2 = 0x110,
243 	.core_vendor_spec_capabilities0 = 0x11c,
244 	.core_ddr_200_cfg = 0x184,
245 	.core_vendor_spec3 = 0x1b0,
246 	.core_dll_config_2 = 0x1b4,
247 	.core_ddr_config_old = 0x1b8,
248 	.core_ddr_config = 0x1bc,
369 	struct clk *core_clk = msm_host->bulk_clks[0].clk;  in msm_set_clock_rate_for_bus_mode()
416 		if (--wait_cnt == 0) {  in msm_dll_poll_ck_out_en()
427 	return 0;  in msm_dll_poll_ck_out_en()
434 		0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,  in msm_config_cm_dll_phase()
435 		0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8  in msm_config_cm_dll_phase()
443 	if (phase > 0xf)  in msm_config_cm_dll_phase()
453 	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */  in msm_config_cm_dll_phase()
454 	rc = msm_dll_poll_ck_out_en(host, 0);  in msm_config_cm_dll_phase()
459 	 * Write the selected DLL clock output phase (0 ... 15)  in msm_config_cm_dll_phase()
493  * setting for SD3.0 UHS-I card read operation (in SDR104
504 	u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };  in msm_find_most_appropriate_phase()
505 	u8 phases_per_row[MAX_PHASES] = { 0 };  in msm_find_most_appropriate_phase()
506 	int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;  in msm_find_most_appropriate_phase()
507 	int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;  in msm_find_most_appropriate_phase()
517 	for (cnt = 0; cnt < total_phases; cnt++) {  in msm_find_most_appropriate_phase()
527 			col_index = 0;  in msm_find_most_appropriate_phase()
534 	/* Check if phase-0 is present in first valid window? */  in msm_find_most_appropriate_phase()
535 	if (!ranges[0][0]) {  in msm_find_most_appropriate_phase()
537 		phase_0_raw_index = 0;  in msm_find_most_appropriate_phase()
541 				for (i = 0; i < phases_per_row[cnt]; i++) {  in msm_find_most_appropriate_phase()
554 		/* number of phases in raw where phase 0 is present */  in msm_find_most_appropriate_phase()
569 		for (cnt = 0; cnt < phases_0; cnt++) {  in msm_find_most_appropriate_phase()
576 		phases_per_row[phase_0_raw_index] = 0;  in msm_find_most_appropriate_phase()
580 	for (cnt = 0; cnt <= row_index; cnt++) {  in msm_find_most_appropriate_phase()
604 	u32 mclk_freq = 0, config;  in msm_cm_dll_set_freq()
610 		mclk_freq = 0;  in msm_cm_dll_set_freq()
639 	unsigned long flags, xo_clk = 0;  in msm_init_cm_dll()
693 		u32 mclk_freq = 0;  in msm_init_cm_dll()
707 		config &= ~(0xFF << 10);  in msm_init_cm_dll()
750 		config &= ~0xFF;  in msm_init_cm_dll()
775 		if (--wait_cnt == 0) {  in msm_init_cm_dll()
785 	return 0;  in msm_init_cm_dll()
813 	 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field  in msm_hc_select_default()
871 			pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",  in msm_hc_select_hs400()
956 	writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);  in sdhci_msm_cdclp533_calibration()
957 	writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);  in sdhci_msm_cdclp533_calibration()
958 	writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);  in sdhci_msm_cdclp533_calibration()
959 	writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);  in sdhci_msm_cdclp533_calibration()
960 	writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);  in sdhci_msm_cdclp533_calibration()
961 	writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);  in sdhci_msm_cdclp533_calibration()
962 	writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);  in sdhci_msm_cdclp533_calibration()
963 	writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);  in sdhci_msm_cdclp533_calibration()
964 	writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);  in sdhci_msm_cdclp533_calibration()
1161 		return 0;  in sdhci_msm_restore_sdr_dll_config()
1199 	u8 phase, tuned_phases[16], tuned_phase_cnt = 0;  in sdhci_msm_execute_tuning()
1208 		return 0;  in sdhci_msm_execute_tuning()
1218 	msm_host->tuning_done = 0;  in sdhci_msm_execute_tuning()
1237 	phase = 0;  in sdhci_msm_execute_tuning()
1265 				tuned_phase_cnt = 0;  in sdhci_msm_execute_tuning()
1272 		if (rc < 0)  in sdhci_msm_execute_tuning()
1364 	 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.  in sdhci_msm_set_uhs_signaling()
1394 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",  in sdhci_msm_set_uhs_signaling()
1420 		load = 0;  in msm_config_vmmc_regulator()
1438 		load = 0;  in msm_config_vqmmc_regulator()
1453 		return 0;  in sdhci_msm_set_vmmc()
1467 		return 0;  in msm_toggle_vqmmc()
1480 			if (ret < 0) {  in msm_toggle_vqmmc()
1505 	load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;  in msm_config_vqmmc_mode()
1521 		return 0;  in sdhci_msm_set_vqmmc()
1526 	 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off  in sdhci_msm_set_vqmmc()
1593 	 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0  in sdhci_msm_check_power_status()
1635 	pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",  in sdhci_msm_dump_pwr_ctrl_regs()
1647 	u32 irq_status, irq_ack = 0;  in sdhci_msm_handle_pwr_irq()
1649 	u32 pwr_state = 0, io_level = 0;  in sdhci_msm_handle_pwr_irq()
1669 		if (retry == 0) {  in sdhci_msm_handle_pwr_irq()
1670 			pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",  in sdhci_msm_handle_pwr_irq()
1719 		if (ret < 0) {  in sdhci_msm_handle_pwr_irq()
1720 …(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",  in sdhci_msm_handle_pwr_irq()
1774 	dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",  in sdhci_msm_handle_pwr_irq()
1797 	struct clk *core_clk = msm_host->bulk_clks[0].clk;  in sdhci_msm_get_max_clock()
1819 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);  in __sdhci_msm_set_clock()
1821 	if (clock == 0)  in __sdhci_msm_set_clock()
1840 		host->mmc->actual_clock = msm_host->clk_rate = 0;  in sdhci_msm_set_clock()
1867 		return 0;  in sdhci_msm_ice_init()
1881 	return 0;  in sdhci_msm_ice_init()
1895 	return 0;  in sdhci_msm_ice_resume()
1903 	return 0;  in sdhci_msm_ice_suspend()
1940 	return 0;  in sdhci_msm_ice_init()
1950 	return 0;  in sdhci_msm_ice_resume()
1956 	return 0;  in sdhci_msm_ice_suspend()
1968 	int cmd_error = 0;  in sdhci_msm_cqe_irq()
1969 	int data_error = 0;  in sdhci_msm_cqe_irq()
1975 	return 0;  in sdhci_msm_cqe_irq()
2126 	u32 req_type = 0;  in __sdhci_msm_check_write()
2155 		msm_host->pwr_irq_flag = 0;  in __sdhci_msm_check_write()
2168 	u32 req_type = 0;  in sdhci_msm_writew()
2180 	u32 req_type = 0;  in sdhci_msm_writeb()
2194 	u32 caps = 0, config;  in sdhci_msm_set_regulator_caps()
2229 	pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);  in sdhci_msm_set_regulator_caps()
2242 	return 0;  in sdhci_msm_register_vreg()
2256 		return 0;  in sdhci_msm_start_signal_voltage_switch()
2265 		/* Set 1.8V Signal Enable in the Host Control2 register to 0 */  in sdhci_msm_start_signal_voltage_switch()
2289 		return 0;  in sdhci_msm_start_signal_voltage_switch()
2310 			"DLL sts: 0x%08x | DLL cfg:  0x%08x | DLL cfg2: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2315 			"DLL cfg3: 0x%08x | DLL usr ctl:  0x%08x | DDR cfg: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2320 			"Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",  in sdhci_msm_dump_vendor_regs()
2415 	int ret = 0;  in sdhci_msm_gcc_reset()
2468 	host->sdma_boundary = 0;  in sdhci_msm_probe()
2528 	msm_host->bulk_clks[0].clk = clk;  in sdhci_msm_probe()
2600 	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",  in sdhci_msm_probe()
2609 	dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",  in sdhci_msm_probe()
2612 	if (core_major == 1 && core_minor >= 0x42)  in sdhci_msm_probe()
2616 	 * SDCC 5 controller with major version 1, minor version 0x34 and later  in sdhci_msm_probe()
2619 	if (core_major == 1 && core_minor < 0x34)  in sdhci_msm_probe()
2626 	if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {  in sdhci_msm_probe()
2633 	if (core_major == 1 && core_minor >= 0x49)  in sdhci_msm_probe()
2636 	if (core_major == 1 && core_minor >= 0x71)  in sdhci_msm_probe()
2650 	sdhci_msm_handle_pwr_irq(host, 0);  in sdhci_msm_probe()
2660 	if (msm_host->pwr_irq < 0) {  in sdhci_msm_probe()
2681 	host->max_timeout_count = 0xF;  in sdhci_msm_probe()
2703 	return 0;  in sdhci_msm_probe()
2726 		    0xffffffff);  in sdhci_msm_remove()
2753 	dev_pm_opp_set_rate(dev, 0);  in sdhci_msm_runtime_suspend()