Lines Matching full:host
30 #include <linux/mmc/host.h>
432 void __iomem *base; /* host base address */
433 void __iomem *top_base; /* host top register base address */
446 int irq; /* host interrupt */
669 static void msdc_reset_hw(struct msdc_host *host) in msdc_reset_hw() argument
673 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
674 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
676 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
677 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
680 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
681 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
684 static void msdc_cmd_next(struct msdc_host *host,
686 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
704 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, in msdc_dma_setup() argument
735 if (host->dev_comp->support_64g) { in msdc_dma_setup()
741 if (host->dev_comp->support_64g) { in msdc_dma_setup()
759 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
760 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
763 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
764 if (host->dev_comp->support_64g) in msdc_dma_setup()
765 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
767 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
770 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) in msdc_prepare_data() argument
774 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
779 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) in msdc_unprepare_data() argument
785 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
791 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) in msdc_timeout_cal() argument
793 struct mmc_host *mmc = mmc_from_priv(host); in msdc_timeout_cal()
807 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
808 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
811 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
821 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) in msdc_set_timeout() argument
825 host->timeout_ns = ns; in msdc_set_timeout()
826 host->timeout_clks = clks; in msdc_set_timeout()
828 timeout = msdc_timeout_cal(host, ns, clks); in msdc_set_timeout()
829 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
833 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) in msdc_set_busy_timeout() argument
837 timeout = msdc_timeout_cal(host, ns, clks); in msdc_set_busy_timeout()
838 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
842 static void msdc_gate_clock(struct msdc_host *host) in msdc_gate_clock() argument
844 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
845 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
846 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
847 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
848 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
849 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
852 static int msdc_ungate_clock(struct msdc_host *host) in msdc_ungate_clock() argument
857 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
858 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
859 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
860 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
861 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
862 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
864 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
868 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
872 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) in msdc_set_mclk() argument
874 struct mmc_host *mmc = mmc_from_priv(host); in msdc_set_mclk()
879 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
883 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
884 host->mclk = 0; in msdc_set_mclk()
886 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
890 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
891 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
892 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
893 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
895 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
905 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
907 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
909 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
910 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
915 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
916 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
917 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
920 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
922 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
925 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
928 sclk = host->src_clk_freq; in msdc_set_mclk()
931 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
933 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
935 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
936 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
939 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
941 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
942 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
943 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
947 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
951 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
952 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
953 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
955 host->mclk = hz; in msdc_set_mclk()
956 host->timing = timing; in msdc_set_mclk()
958 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
959 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
966 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
967 if (host->top_base) { in msdc_set_mclk()
968 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
969 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
970 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
971 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
973 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
974 host->base + tune_reg); in msdc_set_mclk()
977 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
978 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
979 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
980 if (host->top_base) { in msdc_set_mclk()
981 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
982 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
983 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
984 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
986 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
987 host->base + tune_reg); in msdc_set_mclk()
992 host->dev_comp->hs400_tune) in msdc_set_mclk()
993 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
995 host->hs400_cmd_int_delay); in msdc_set_mclk()
996 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1000 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, in msdc_cmd_find_resp() argument
1028 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, in msdc_cmd_prepare_raw_cmd() argument
1031 struct mmc_host *mmc = mmc_from_priv(host); in msdc_cmd_prepare_raw_cmd()
1037 u32 resp = msdc_cmd_find_resp(host, cmd); in msdc_cmd_prepare_raw_cmd()
1040 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1071 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1073 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1074 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1075 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1078 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1083 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, in msdc_start_data() argument
1088 WARN_ON(host->data); in msdc_start_data()
1089 host->data = data; in msdc_start_data()
1092 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1093 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1094 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1095 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1096 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1097 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1101 static int msdc_auto_cmd_done(struct msdc_host *host, int events, in msdc_auto_cmd_done() argument
1106 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1111 msdc_reset_hw(host); in msdc_auto_cmd_done()
1114 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1117 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1119 dev_err(host->dev, in msdc_auto_cmd_done()
1129 * Host controller may lost interrupt in some special case.
1133 static void msdc_recheck_sdio_irq(struct msdc_host *host) in msdc_recheck_sdio_irq() argument
1135 struct mmc_host *mmc = mmc_from_priv(host); in msdc_recheck_sdio_irq()
1139 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1141 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1142 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1145 __msdc_enable_sdio_irq(host, 0); in msdc_recheck_sdio_irq()
1152 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) in msdc_track_cmd_data() argument
1154 if (host->error) in msdc_track_cmd_data()
1155 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1156 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1159 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) in msdc_request_done() argument
1167 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1169 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1170 host->mrq = NULL; in msdc_request_done()
1171 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1173 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1175 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1176 if (host->error) in msdc_request_done()
1177 msdc_reset_hw(host); in msdc_request_done()
1178 mmc_request_done(mmc_from_priv(host), mrq); in msdc_request_done()
1179 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1180 msdc_recheck_sdio_irq(host); in msdc_request_done()
1184 static bool msdc_cmd_done(struct msdc_host *host, int events, in msdc_cmd_done() argument
1195 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1204 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1205 done = !host->cmd; in msdc_cmd_done()
1206 host->cmd = NULL; in msdc_cmd_done()
1207 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1213 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1217 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1218 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1219 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1220 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1222 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1227 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) || in msdc_cmd_done()
1228 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1234 msdc_reset_hw(host); in msdc_cmd_done()
1237 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1240 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1244 dev_dbg(host->dev, in msdc_cmd_done()
1249 msdc_cmd_next(host, mrq, cmd); in msdc_cmd_done()
1254 * is correct before issue a request. but host design do below
1257 static inline bool msdc_cmd_is_ready(struct msdc_host *host, in msdc_cmd_is_ready() argument
1264 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1267 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1268 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1269 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); in msdc_cmd_is_ready()
1275 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1278 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1279 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1280 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); in msdc_cmd_is_ready()
1287 static void msdc_start_command(struct msdc_host *host, in msdc_start_command() argument
1293 WARN_ON(host->cmd); in msdc_start_command()
1294 host->cmd = cmd; in msdc_start_command()
1296 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1297 if (!msdc_cmd_is_ready(host, mrq, cmd)) in msdc_start_command()
1300 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1301 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1302 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1303 msdc_reset_hw(host); in msdc_start_command()
1307 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); in msdc_start_command()
1309 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1310 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1311 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1313 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1314 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1317 static void msdc_cmd_next(struct msdc_host *host, in msdc_cmd_next() argument
1320 if ((cmd->error && !host->hs400_tuning && in msdc_cmd_next()
1324 msdc_request_done(host, mrq); in msdc_cmd_next()
1326 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1328 msdc_request_done(host, mrq); in msdc_cmd_next()
1330 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1335 struct msdc_host *host = mmc_priv(mmc); in msdc_ops_request() local
1337 host->error = 0; in msdc_ops_request()
1338 WARN_ON(host->mrq); in msdc_ops_request()
1339 host->mrq = mrq; in msdc_ops_request()
1342 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1350 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1352 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1357 struct msdc_host *host = mmc_priv(mmc); in msdc_pre_req() local
1363 msdc_prepare_data(host, data); in msdc_pre_req()
1370 struct msdc_host *host = mmc_priv(mmc); in msdc_post_req() local
1378 msdc_unprepare_data(host, data); in msdc_post_req()
1382 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) in msdc_data_xfer_next() argument
1386 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1388 msdc_request_done(host, mrq); in msdc_data_xfer_next()
1391 static void msdc_data_xfer_done(struct msdc_host *host, u32 events, in msdc_data_xfer_done() argument
1404 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1405 done = !host->data; in msdc_data_xfer_done()
1407 host->data = NULL; in msdc_data_xfer_done()
1408 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1415 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1416 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1417 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1420 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1423 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1425 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1428 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1430 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1431 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1436 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1437 msdc_reset_hw(host); in msdc_data_xfer_done()
1438 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1446 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1448 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1452 msdc_data_xfer_next(host, mrq); in msdc_data_xfer_done()
1456 static void msdc_set_buswidth(struct msdc_host *host, u32 width) in msdc_set_buswidth() argument
1458 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1475 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1476 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1481 struct msdc_host *host = mmc_priv(mmc); in msdc_ops_switch_volt() local
1487 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1493 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1500 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1502 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1509 struct msdc_host *host = mmc_priv(mmc); in msdc_card_busy() local
1510 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1518 struct msdc_host *host = container_of(work, struct msdc_host, in msdc_request_timeout() local
1522 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1523 if (host->mrq) { in msdc_request_timeout()
1524 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1525 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1526 if (host->cmd) { in msdc_request_timeout()
1527 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1528 __func__, host->cmd->opcode); in msdc_request_timeout()
1529 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1530 host->cmd); in msdc_request_timeout()
1531 } else if (host->data) { in msdc_request_timeout()
1532 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1533 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1534 host->data->blocks); in msdc_request_timeout()
1535 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1536 host->data); in msdc_request_timeout()
1541 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) in __msdc_enable_sdio_irq() argument
1544 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1545 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1546 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1547 msdc_recheck_sdio_irq(host); in __msdc_enable_sdio_irq()
1549 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1550 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1556 struct msdc_host *host = mmc_priv(mmc); in msdc_enable_sdio_irq() local
1560 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1561 __msdc_enable_sdio_irq(host, enb); in msdc_enable_sdio_irq()
1562 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1564 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1572 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1573 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1576 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1577 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1578 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1580 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1583 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1585 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1589 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1590 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1591 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1593 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1598 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) in msdc_cmdq_irq() argument
1600 struct mmc_host *mmc = mmc_from_priv(host); in msdc_cmdq_irq()
1605 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1608 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1613 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1616 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1620 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", in msdc_cmdq_irq()
1629 struct msdc_host *host = (struct msdc_host *) dev_id; in msdc_irq() local
1630 struct mmc_host *mmc = mmc_from_priv(host); in msdc_irq()
1638 spin_lock(&host->lock); in msdc_irq()
1639 events = readl(host->base + MSDC_INT); in msdc_irq()
1640 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1642 __msdc_enable_sdio_irq(host, 0); in msdc_irq()
1644 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1646 mrq = host->mrq; in msdc_irq()
1647 cmd = host->cmd; in msdc_irq()
1648 data = host->data; in msdc_irq()
1649 spin_unlock(&host->lock); in msdc_irq()
1655 if (host->internal_cd) in msdc_irq()
1665 msdc_cmdq_irq(host, events); in msdc_irq()
1667 writel(events, host->base + MSDC_INT); in msdc_irq()
1672 dev_err(host->dev, in msdc_irq()
1679 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1682 msdc_cmd_done(host, events, mrq, cmd); in msdc_irq()
1684 msdc_data_xfer_done(host, events, mrq, data); in msdc_irq()
1690 static void msdc_init_hw(struct msdc_host *host) in msdc_init_hw() argument
1693 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1694 struct mmc_host *mmc = mmc_from_priv(host); in msdc_init_hw()
1696 if (host->reset) { in msdc_init_hw()
1697 reset_control_assert(host->reset); in msdc_init_hw()
1699 reset_control_deassert(host->reset); in msdc_init_hw()
1703 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1706 msdc_reset_hw(host); in msdc_init_hw()
1709 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1710 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1711 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1714 if (host->internal_cd) { in msdc_init_hw()
1715 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1717 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1718 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1719 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1721 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1722 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1723 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1726 if (host->top_base) { in msdc_init_hw()
1727 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1728 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1730 writel(0, host->base + tune_reg); in msdc_init_hw()
1732 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1733 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1734 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1735 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1736 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1737 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1739 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1740 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1742 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1744 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1748 if (host->dev_comp->busy_check) in msdc_init_hw()
1749 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1751 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1752 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1754 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1755 if (host->top_base) in msdc_init_hw()
1756 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1759 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1762 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1764 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1768 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1770 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1774 if (host->dev_comp->support_64g) in msdc_init_hw()
1775 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1777 if (host->dev_comp->data_tune) { in msdc_init_hw()
1778 if (host->top_base) { in msdc_init_hw()
1779 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1781 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1783 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1786 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1792 if (host->top_base) in msdc_init_hw()
1793 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1796 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1801 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1802 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1803 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1806 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1809 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1810 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1814 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1816 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1817 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1818 if (host->top_base) { in msdc_init_hw()
1819 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1820 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1821 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1822 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1823 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1824 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1825 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1826 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1828 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1829 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1831 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1834 static void msdc_deinit_hw(struct msdc_host *host) in msdc_deinit_hw() argument
1838 if (host->internal_cd) { in msdc_deinit_hw()
1840 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1841 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1845 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1847 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1848 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
1852 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) in msdc_init_gpd_bd() argument
1867 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1872 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1879 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1886 struct msdc_host *host = mmc_priv(mmc); in msdc_ops_set_ios() local
1889 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
1895 msdc_init_hw(host); in msdc_ops_set_ios()
1899 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
1905 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
1908 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
1910 host->vqmmc_enabled = true; in msdc_ops_set_ios()
1917 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
1919 host->vqmmc_enabled = false; in msdc_ops_set_ios()
1926 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
1927 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
1947 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) in get_best_delay() argument
1955 dev_err(host->dev, "phase error: [map:%x]\n", delay); in get_best_delay()
1976 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", in get_best_delay()
1985 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) in msdc_set_cmd_delay() argument
1987 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
1989 if (host->top_base) in msdc_set_cmd_delay()
1990 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
1993 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
1997 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) in msdc_set_data_delay() argument
1999 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
2001 if (host->top_base) in msdc_set_data_delay()
2002 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2005 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2011 struct msdc_host *host = mmc_priv(mmc); in msdc_tune_response() local
2017 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2023 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2025 host->hs200_cmd_int_delay); in msdc_tune_response()
2027 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2029 msdc_set_cmd_delay(host, i); in msdc_tune_response()
2045 final_rise_delay = get_best_delay(host, rise_delay); in msdc_tune_response()
2051 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2053 msdc_set_cmd_delay(host, i); in msdc_tune_response()
2069 final_fall_delay = get_best_delay(host, fall_delay); in msdc_tune_response()
2076 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2079 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2082 msdc_set_cmd_delay(host, final_delay); in msdc_tune_response()
2084 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2088 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2094 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2095 internal_delay_phase = get_best_delay(host, internal_delay); in msdc_tune_response()
2096 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2099 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2105 struct msdc_host *host = mmc_priv(mmc); in hs400_tune_response() local
2113 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2114 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2118 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2120 host->hs200_cmd_int_delay); in hs400_tune_response()
2122 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2123 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2125 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2127 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2144 final_cmd_delay = get_best_delay(host, cmd_delay); in hs400_tune_response()
2145 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2149 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2155 struct msdc_host *host = mmc_priv(mmc); in msdc_tune_data() local
2161 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2162 host->latch_ck); in msdc_tune_data()
2163 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2164 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2166 msdc_set_data_delay(host, i); in msdc_tune_data()
2171 final_rise_delay = get_best_delay(host, rise_delay); in msdc_tune_data()
2177 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2178 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2180 msdc_set_data_delay(host, i); in msdc_tune_data()
2185 final_fall_delay = get_best_delay(host, fall_delay); in msdc_tune_data()
2190 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2191 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2194 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2195 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2198 msdc_set_data_delay(host, final_delay); in msdc_tune_data()
2200 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2210 struct msdc_host *host = mmc_priv(mmc); in msdc_tune_together() local
2216 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2217 host->latch_ck); in msdc_tune_together()
2219 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2220 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2223 msdc_set_cmd_delay(host, i); in msdc_tune_together()
2224 msdc_set_data_delay(host, i); in msdc_tune_together()
2229 final_rise_delay = get_best_delay(host, rise_delay); in msdc_tune_together()
2235 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2236 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2239 msdc_set_cmd_delay(host, i); in msdc_tune_together()
2240 msdc_set_data_delay(host, i); in msdc_tune_together()
2245 final_fall_delay = get_best_delay(host, fall_delay); in msdc_tune_together()
2250 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2251 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2255 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2256 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2261 msdc_set_cmd_delay(host, final_delay); in msdc_tune_together()
2262 msdc_set_data_delay(host, final_delay); in msdc_tune_together()
2264 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2270 struct msdc_host *host = mmc_priv(mmc); in msdc_execute_tuning() local
2272 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2274 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2276 if (host->hs400_mode) { in msdc_execute_tuning()
2277 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_execute_tuning()
2279 msdc_set_data_delay(host, 0); in msdc_execute_tuning()
2283 if (host->hs400_mode && in msdc_execute_tuning()
2284 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2289 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2292 if (host->hs400_mode == false) { in msdc_execute_tuning()
2295 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2299 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2300 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2301 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2302 if (host->top_base) { in msdc_execute_tuning()
2303 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2305 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2313 struct msdc_host *host = mmc_priv(mmc); in msdc_prepare_hs400_tuning() local
2315 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2317 if (host->top_base) { in msdc_prepare_hs400_tuning()
2318 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2319 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2320 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2321 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2322 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2323 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2325 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2326 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2327 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2328 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2329 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2332 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2334 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2341 struct msdc_host *host = mmc_priv(mmc); in msdc_execute_hs400_tuning() local
2347 if (host->top_base) { in msdc_execute_hs400_tuning()
2348 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2350 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2353 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2354 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL); in msdc_execute_hs400_tuning()
2357 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2359 if (host->top_base) in msdc_execute_hs400_tuning()
2360 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2363 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2371 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2373 dly1_delay = get_best_delay(host, result_dly1); in msdc_execute_hs400_tuning()
2375 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2378 if (host->top_base) in msdc_execute_hs400_tuning()
2379 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2382 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2385 if (host->top_base) in msdc_execute_hs400_tuning()
2386 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2388 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2390 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2395 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2401 struct msdc_host *host = mmc_priv(mmc); in msdc_hw_reset() local
2403 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2405 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2411 struct msdc_host *host = mmc_priv(mmc); in msdc_ack_sdio_irq() local
2413 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2414 __msdc_enable_sdio_irq(host, 1); in msdc_ack_sdio_irq()
2415 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2420 struct msdc_host *host = mmc_priv(mmc); in msdc_get_cd() local
2426 if (!host->internal_cd) in msdc_get_cd()
2429 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2439 struct msdc_host *host = mmc_priv(mmc); in msdc_hs400_enhanced_strobe() local
2443 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2444 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2445 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2447 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2448 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2449 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2451 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2452 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2453 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2455 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2456 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2457 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2461 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns) in msdc_cqe_cit_cal() argument
2463 struct mmc_host *mmc = mmc_from_priv(host); in msdc_cqe_cit_cal()
2473 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2491 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2497 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2502 struct msdc_host *host = mmc_priv(mmc); in msdc_cqe_enable() local
2506 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2508 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2510 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); in msdc_cqe_enable()
2512 msdc_set_timeout(host, 1000000000ULL, 0); in msdc_cqe_enable()
2515 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2520 struct msdc_host *host = mmc_priv(mmc); in msdc_cqe_disable() local
2524 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2526 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2528 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2529 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2532 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2534 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2537 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2540 msdc_reset_hw(host); in msdc_cqe_disable()
2590 struct msdc_host *host) in msdc_of_property_parse() argument
2593 &host->latch_ck); in msdc_of_property_parse()
2596 &host->hs400_ds_delay); in msdc_of_property_parse()
2599 &host->hs400_ds_dly3); in msdc_of_property_parse()
2602 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2605 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2609 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2611 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2615 host->cqhci = true; in msdc_of_property_parse()
2617 host->cqhci = false; in msdc_of_property_parse()
2621 struct msdc_host *host) in msdc_of_clock_parse() argument
2625 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2626 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2627 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2629 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2630 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2631 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2633 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2634 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2635 host->bus_clk = NULL; in msdc_of_clock_parse()
2638 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2639 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2640 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2649 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2650 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2651 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2652 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2656 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2657 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2658 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2660 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2661 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2662 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2664 host->bulk_clks); in msdc_of_clock_parse()
2676 struct msdc_host *host; in msdc_drv_probe() local
2685 /* Allocate MMC host for this device */ in msdc_drv_probe()
2690 host = mmc_priv(mmc); in msdc_drv_probe()
2695 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2696 if (IS_ERR(host->base)) in msdc_drv_probe()
2697 return PTR_ERR(host->base); in msdc_drv_probe()
2701 host->top_base = devm_ioremap_resource(&pdev->dev, res); in msdc_drv_probe()
2702 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2703 host->top_base = NULL; in msdc_drv_probe()
2710 ret = msdc_of_clock_parse(pdev, host); in msdc_drv_probe()
2714 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2716 if (IS_ERR(host->reset)) in msdc_drv_probe()
2717 return PTR_ERR(host->reset); in msdc_drv_probe()
2721 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
2722 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
2723 return PTR_ERR(host->crypto_clk); in msdc_drv_probe()
2724 else if (host->crypto_clk) in msdc_drv_probe()
2728 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2729 if (host->irq < 0) in msdc_drv_probe()
2730 return host->irq; in msdc_drv_probe()
2732 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2733 if (IS_ERR(host->pinctrl)) in msdc_drv_probe()
2734 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl), in msdc_drv_probe()
2737 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2738 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2740 return PTR_ERR(host->pins_default); in msdc_drv_probe()
2743 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2744 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2746 return PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2751 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
2752 if (host->eint_irq > 0) { in msdc_drv_probe()
2753 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2754 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2756 host->pins_eint = NULL; in msdc_drv_probe()
2763 msdc_of_property_parse(pdev, host); in msdc_drv_probe()
2765 host->dev = &pdev->dev; in msdc_drv_probe()
2766 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2767 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2768 /* Set host parameters to mmc */ in msdc_drv_probe()
2770 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2771 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2773 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2777 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2782 host->internal_cd = true; in msdc_drv_probe()
2789 if (host->cqhci) in msdc_drv_probe()
2793 if (host->dev_comp->support_64g) in msdc_drv_probe()
2800 if (host->dev_comp->support_64g) in msdc_drv_probe()
2801 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2803 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2804 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2806 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2807 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2809 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2810 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2812 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2813 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
2817 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
2818 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
2819 spin_lock_init(&host->lock); in msdc_drv_probe()
2822 ret = msdc_ungate_clock(host); in msdc_drv_probe()
2827 msdc_init_hw(host); in msdc_drv_probe()
2830 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
2831 sizeof(*host->cq_host), in msdc_drv_probe()
2833 if (!host->cq_host) { in msdc_drv_probe()
2837 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
2838 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
2839 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
2840 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
2848 msdc_cqe_cit_cal(host, 2350); in msdc_drv_probe()
2851 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
2852 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
2856 pm_runtime_set_active(host->dev); in msdc_drv_probe()
2857 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
2858 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
2859 pm_runtime_enable(host->dev); in msdc_drv_probe()
2867 pm_runtime_disable(host->dev); in msdc_drv_probe()
2869 msdc_deinit_hw(host); in msdc_drv_probe()
2871 msdc_gate_clock(host); in msdc_drv_probe()
2875 if (host->dma.gpd) in msdc_drv_probe()
2878 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
2879 if (host->dma.bd) in msdc_drv_probe()
2882 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
2889 struct msdc_host *host; in msdc_drv_remove() local
2892 host = mmc_priv(mmc); in msdc_drv_remove()
2894 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
2898 msdc_deinit_hw(host); in msdc_drv_remove()
2899 msdc_gate_clock(host); in msdc_drv_remove()
2901 pm_runtime_disable(host->dev); in msdc_drv_remove()
2902 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
2905 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
2907 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
2911 static void msdc_save_reg(struct msdc_host *host) in msdc_save_reg() argument
2913 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
2915 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2916 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
2917 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
2918 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
2919 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
2920 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
2921 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
2922 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
2923 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
2924 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
2925 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
2926 if (host->top_base) { in msdc_save_reg()
2927 host->save_para.emmc_top_control = in msdc_save_reg()
2928 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
2929 host->save_para.emmc_top_cmd = in msdc_save_reg()
2930 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
2931 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
2932 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
2934 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
2938 static void msdc_restore_reg(struct msdc_host *host) in msdc_restore_reg() argument
2940 struct mmc_host *mmc = mmc_from_priv(host); in msdc_restore_reg()
2941 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
2943 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
2944 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
2945 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
2946 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
2947 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
2948 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
2949 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
2950 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
2951 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
2952 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
2953 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
2954 if (host->top_base) { in msdc_restore_reg()
2955 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
2956 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
2957 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
2958 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
2959 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
2960 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
2962 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
2966 __msdc_enable_sdio_irq(host, 1); in msdc_restore_reg()
2972 struct msdc_host *host = mmc_priv(mmc); in msdc_runtime_suspend() local
2974 msdc_save_reg(host); in msdc_runtime_suspend()
2977 if (host->pins_eint) { in msdc_runtime_suspend()
2978 disable_irq(host->irq); in msdc_runtime_suspend()
2979 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
2982 __msdc_enable_sdio_irq(host, 0); in msdc_runtime_suspend()
2984 msdc_gate_clock(host); in msdc_runtime_suspend()
2991 struct msdc_host *host = mmc_priv(mmc); in msdc_runtime_resume() local
2994 ret = msdc_ungate_clock(host); in msdc_runtime_resume()
2998 msdc_restore_reg(host); in msdc_runtime_resume()
3000 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
3001 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
3002 enable_irq(host->irq); in msdc_runtime_resume()
3010 struct msdc_host *host = mmc_priv(mmc); in msdc_suspend() local
3018 val = readl(host->base + MSDC_INT); in msdc_suspend()
3019 writel(val, host->base + MSDC_INT); in msdc_suspend()
3026 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3035 struct msdc_host *host = mmc_priv(mmc); in msdc_resume() local
3037 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()