Lines Matching refs:src_clk_period
617 u32 src_clk_period, dst_clk_period; /* in picoseconds */ in tegra210_emc_r21021_set_clock() local
651 src_clk_period = 1000000000 / last->rate; in tegra210_emc_r21021_set_clock()
684 src_clk_period, dst_clk_period); in tegra210_emc_r21021_set_clock()
863 if (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
902 if (src_clk_period >= 1000000 / 1866) /* 535.91 ps */ in tegra210_emc_r21021_set_clock()
905 if (src_clk_period >= 1000000 / 1600) /* 625.00 ps */ in tegra210_emc_r21021_set_clock()
908 if (src_clk_period >= 1000000 / 1333) /* 750.19 ps */ in tegra210_emc_r21021_set_clock()
911 if (src_clk_period >= 1000000 / 1066) /* 938.09 ps */ in tegra210_emc_r21021_set_clock()
914 deltaTWATM = max_t(u32, div_o3(7500, src_clk_period), 8); in tegra210_emc_r21021_set_clock()
925 tRTM = fake->dram_timings[RL] + div_o3(3600, src_clk_period) + in tegra210_emc_r21021_set_clock()
926 max_t(u32, div_o3(7500, src_clk_period), 8) + tRPST + in tegra210_emc_r21021_set_clock()
1313 value = (1000 * fake->dram_timings[T_RP]) / src_clk_period; in tegra210_emc_r21021_set_clock()
1315 ccfifo_writel(emc, 0, 0, tFC_lpddr4 / src_clk_period); in tegra210_emc_r21021_set_clock()
1323 src_clk_period; in tegra210_emc_r21021_set_clock()
1346 delay = ((1000 * fake->dram_timings[T_RP] / src_clk_period) + in tegra210_emc_r21021_set_clock()
1347 (1000 * fake->dram_timings[T_RFC] / src_clk_period)); in tegra210_emc_r21021_set_clock()
1364 ramp_down_wait = tegra210_emc_dvfs_power_ramp_down(emc, src_clk_period, in tegra210_emc_r21021_set_clock()