31 #define IMX290_STANDBY					CCI_REG8(0x3000)
32 #define IMX290_REGHOLD					CCI_REG8(0x3001)
33 #define IMX290_XMSTA					CCI_REG8(0x3002)
34 #define IMX290_ADBIT					CCI_REG8(0x3005)
35 #define IMX290_ADBIT_10BIT				(0 << 0)
36 #define IMX290_ADBIT_12BIT				(1 << 0)
37 #define IMX290_CTRL_07					CCI_REG8(0x3007)
38 #define IMX290_VREVERSE					BIT(0)
40 #define IMX290_WINMODE_1080P				(0 << 4)
43 #define IMX290_FR_FDG_SEL				CCI_REG8(0x3009)
44 #define IMX290_BLKLEVEL					CCI_REG16_LE(0x300a)
45 #define IMX290_GAIN					CCI_REG8(0x3014)
46 #define IMX290_VMAX					CCI_REG24_LE(0x3018)
47 #define IMX290_VMAX_MAX					0x3ffff
48 #define IMX290_HMAX					CCI_REG16_LE(0x301c)
49 #define IMX290_HMAX_MAX					0xffff
50 #define IMX290_SHS1					CCI_REG24_LE(0x3020)
51 #define IMX290_WINWV_OB					CCI_REG8(0x303a)
52 #define IMX290_WINPV					CCI_REG16_LE(0x303c)
53 #define IMX290_WINWV					CCI_REG16_LE(0x303e)
54 #define IMX290_WINPH					CCI_REG16_LE(0x3040)
55 #define IMX290_WINWH					CCI_REG16_LE(0x3042)
56 #define IMX290_OUT_CTRL					CCI_REG8(0x3046)
57 #define IMX290_ODBIT_10BIT				(0 << 0)
58 #define IMX290_ODBIT_12BIT				(1 << 0)
59 #define IMX290_OPORTSEL_PARALLEL			(0x0 << 4)
60 #define IMX290_OPORTSEL_LVDS_2CH			(0xd << 4)
61 #define IMX290_OPORTSEL_LVDS_4CH			(0xe << 4)
62 #define IMX290_OPORTSEL_LVDS_8CH			(0xf << 4)
63 #define IMX290_XSOUTSEL					CCI_REG8(0x304b)
64 #define IMX290_XSOUTSEL_XVSOUTSEL_HIGH			(0 << 0)
65 #define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC			(2 << 0)
66 #define IMX290_XSOUTSEL_XHSOUTSEL_HIGH			(0 << 2)
68 #define IMX290_INCKSEL1					CCI_REG8(0x305c)
69 #define IMX290_INCKSEL2					CCI_REG8(0x305d)
70 #define IMX290_INCKSEL3					CCI_REG8(0x305e)
71 #define IMX290_INCKSEL4					CCI_REG8(0x305f)
72 #define IMX290_PGCTRL					CCI_REG8(0x308c)
73 #define IMX290_ADBIT1					CCI_REG8(0x3129)
74 #define IMX290_ADBIT1_10BIT				0x1d
75 #define IMX290_ADBIT1_12BIT				0x00
76 #define IMX290_INCKSEL5					CCI_REG8(0x315e)
77 #define IMX290_INCKSEL6					CCI_REG8(0x3164)
78 #define IMX290_ADBIT2					CCI_REG8(0x317c)
79 #define IMX290_ADBIT2_10BIT				0x12
80 #define IMX290_ADBIT2_12BIT				0x00
81 #define IMX290_CHIP_ID					CCI_REG16_LE(0x319a)
82 #define IMX290_ADBIT3					CCI_REG8(0x31ec)
83 #define IMX290_ADBIT3_10BIT				0x37
84 #define IMX290_ADBIT3_12BIT				0x0e
85 #define IMX290_REPETITION				CCI_REG8(0x3405)
86 #define IMX290_PHY_LANE_NUM				CCI_REG8(0x3407)
87 #define IMX290_OPB_SIZE_V				CCI_REG8(0x3414)
88 #define IMX290_Y_OUT_SIZE				CCI_REG16_LE(0x3418)
89 #define IMX290_CSI_DT_FMT				CCI_REG16_LE(0x3441)
90 #define IMX290_CSI_DT_FMT_RAW10				0x0a0a
91 #define IMX290_CSI_DT_FMT_RAW12				0x0c0c
92 #define IMX290_CSI_LANE_MODE				CCI_REG8(0x3443)
93 #define IMX290_EXTCK_FREQ				CCI_REG16_LE(0x3444)
94 #define IMX290_TCLKPOST					CCI_REG16_LE(0x3446)
95 #define IMX290_THSZERO					CCI_REG16_LE(0x3448)
96 #define IMX290_THSPREPARE				CCI_REG16_LE(0x344a)
97 #define IMX290_TCLKTRAIL				CCI_REG16_LE(0x344c)
98 #define IMX290_THSTRAIL					CCI_REG16_LE(0x344e)
99 #define IMX290_TCLKZERO					CCI_REG16_LE(0x3450)
100 #define IMX290_TCLKPREPARE				CCI_REG16_LE(0x3452)
101 #define IMX290_TLPX					CCI_REG16_LE(0x3454)
102 #define IMX290_X_OUT_SIZE				CCI_REG16_LE(0x3472)
103 #define IMX290_INCKSEL7					CCI_REG8(0x3480)
105 #define IMX290_PGCTRL_REGEN				BIT(0)
266 	{ IMX290_WINPH, 0 },
267 	{ IMX290_WINPV, 0 },
272 	{ CCI_REG8(0x3012), 0x64 },
273 	{ CCI_REG8(0x3013), 0x00 },
277 	{ CCI_REG8(0x300f), 0x00 },
278 	{ CCI_REG8(0x3010), 0x21 },
279 	{ CCI_REG8(0x3011), 0x00 },
280 	{ CCI_REG8(0x3016), 0x09 },
281 	{ CCI_REG8(0x3070), 0x02 },
282 	{ CCI_REG8(0x3071), 0x11 },
283 	{ CCI_REG8(0x309b), 0x10 },
284 	{ CCI_REG8(0x309c), 0x22 },
285 	{ CCI_REG8(0x30a2), 0x02 },
286 	{ CCI_REG8(0x30a6), 0x20 },
287 	{ CCI_REG8(0x30a8), 0x20 },
288 	{ CCI_REG8(0x30aa), 0x20 },
289 	{ CCI_REG8(0x30ac), 0x20 },
290 	{ CCI_REG8(0x30b0), 0x43 },
291 	{ CCI_REG8(0x3119), 0x9e },
292 	{ CCI_REG8(0x311c), 0x1e },
293 	{ CCI_REG8(0x311e), 0x08 },
294 	{ CCI_REG8(0x3128), 0x05 },
295 	{ CCI_REG8(0x313d), 0x83 },
296 	{ CCI_REG8(0x3150), 0x03 },
297 	{ CCI_REG8(0x317e), 0x00 },
298 	{ CCI_REG8(0x32b8), 0x50 },
299 	{ CCI_REG8(0x32b9), 0x10 },
300 	{ CCI_REG8(0x32ba), 0x00 },
301 	{ CCI_REG8(0x32bb), 0x04 },
302 	{ CCI_REG8(0x32c8), 0x50 },
303 	{ CCI_REG8(0x32c9), 0x10 },
304 	{ CCI_REG8(0x32ca), 0x00 },
305 	{ CCI_REG8(0x32cb), 0x04 },
306 	{ CCI_REG8(0x332c), 0xd3 },
307 	{ CCI_REG8(0x332d), 0x10 },
308 	{ CCI_REG8(0x332e), 0x0d },
309 	{ CCI_REG8(0x3358), 0x06 },
310 	{ CCI_REG8(0x3359), 0xe1 },
311 	{ CCI_REG8(0x335a), 0x11 },
312 	{ CCI_REG8(0x3360), 0x1e },
313 	{ CCI_REG8(0x3361), 0x61 },
314 	{ CCI_REG8(0x3362), 0x10 },
315 	{ CCI_REG8(0x33b0), 0x50 },
316 	{ CCI_REG8(0x33b2), 0x1a },
317 	{ CCI_REG8(0x33b3), 0x04 },
324 		{ IMX290_INCKSEL7, 0x49 },
328 		{ IMX290_INCKSEL7, 0x92 },
333 	{ CCI_REG8(0x3011), 0x02 },
334 	{ CCI_REG8(0x309e), 0x4A },
335 	{ CCI_REG8(0x309f), 0x4A },
336 	{ CCI_REG8(0x313b), 0x61 },
375 	.repetition = 0x10,
388 	.repetition = 0x00,
401 	.repetition = 0x10,
414 	.repetition = 0x00,
426 #define FREQ_INDEX_1080P	0
461 		.incksel1 = 0x18,
462 		.incksel2 = 0x03,
463 		.incksel3 = 0x20,
464 		.incksel4 = 0x01,
465 		.incksel5 = 0x1a,
466 		.incksel6 = 0x1a,
470 		.incksel1 = 0x0c,
471 		.incksel2 = 0x03,
472 		.incksel3 = 0x10,
473 		.incksel4 = 0x01,
474 		.incksel5 = 0x1b,
475 		.incksel6 = 0x1b,
482 		.incksel1 = 0x20,
483 		.incksel2 = 0x00,
484 		.incksel3 = 0x20,
485 		.incksel4 = 0x01,
486 		.incksel5 = 0x1a,
487 		.incksel6 = 0x1a,
491 		.incksel1 = 0x10,
492 		.incksel2 = 0x00,
493 		.incksel3 = 0x10,
494 		.incksel4 = 0x01,
495 		.incksel5 = 0x1b,
496 		.incksel6 = 0x1b,
599 	for (i = 0; i < ARRAY_SIZE(imx290_formats); ++i) {  in imx290_format_info()
616 	if (ret < 0)  in imx290_set_register_array()
622 	return 0;  in imx290_set_register_array()
647 	int ret = 0;  in imx290_set_data_lanes()
653 	cci_write(imx290->regmap, IMX290_FR_FDG_SEL, 0x01, &ret);  in imx290_set_data_lanes()
672 	int ret = 0;  in imx290_set_csi_config()
714 	if (ret < 0) {  in imx290_setup_format()
743 	int ret = 0, vmax;  in imx290_set_ctrl()
750 		return 0;  in imx290_set_ctrl()
759 		return 0;  in imx290_set_ctrl()
762 	format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0);  in imx290_set_ctrl()
789 			imx290_set_black_level(imx290, format, 0, &ret);  in imx290_set_ctrl()
796 			cci_write(imx290->regmap, IMX290_PGCTRL, 0x00, &ret);  in imx290_set_ctrl()
870 	if (ret < 0)  in imx290_ctrl_init()
878 	 * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values  in imx290_ctrl_init()
889 			  V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);  in imx290_ctrl_init()
907 				       imx290_link_freqs_num(imx290) - 1, 0,  in imx290_ctrl_init()
919 				     0, 0, imx290_test_pattern_menu);  in imx290_ctrl_init()
931 					  V4L2_CID_HFLIP, 0, 1, 1, 0);  in imx290_ctrl_init()
933 					  V4L2_CID_VFLIP, 0, 1, 1, 0);  in imx290_ctrl_init()
947 	return 0;  in imx290_ctrl_init()
964 	if (ret < 0) {  in imx290_start_streaming()
972 	if (ret < 0) {  in imx290_start_streaming()
979 	if (ret < 0) {  in imx290_start_streaming()
986 	if (ret < 0) {  in imx290_start_streaming()
992 	if (ret < 0) {  in imx290_start_streaming()
998 	format = v4l2_subdev_get_pad_format(&imx290->sd, state, 0);  in imx290_start_streaming()
1000 	if (ret < 0) {  in imx290_start_streaming()
1008 	if (ret < 0) {  in imx290_start_streaming()
1020 	cci_write(imx290->regmap, IMX290_STANDBY, 0x00, &ret);  in imx290_start_streaming()
1025 	return cci_write(imx290->regmap, IMX290_XMSTA, 0x00, &ret);  in imx290_start_streaming()
1031 	int ret = 0;  in imx290_stop_streaming()
1033 	cci_write(imx290->regmap, IMX290_STANDBY, 0x01, &ret);  in imx290_stop_streaming()
1037 	return cci_write(imx290->regmap, IMX290_XMSTA, 0x01, &ret);  in imx290_stop_streaming()
1044 	int ret = 0;  in imx290_set_stream()
1050 		if (ret < 0)  in imx290_set_stream()
1088 	return 0;  in imx290_enum_mbus_code()
1109 	return 0;  in imx290_enum_frame_size()
1128 		fmt->format.code = imx290_formats[0].code[imx290->model->colour_variant];  in imx290_set_fmt()
1136 	format = v4l2_subdev_get_pad_format(sd, sd_state, 0);  in imx290_set_fmt()
1147 	return 0;  in imx290_set_fmt()
1159 		format = v4l2_subdev_get_pad_format(sd, sd_state, 0);  in imx290_get_selection()
1174 		return 0;  in imx290_get_selection()
1179 		sel->r.top = 0;  in imx290_get_selection()
1180 		sel->r.left = 0;  in imx290_get_selection()
1184 		return 0;  in imx290_get_selection()
1192 		return 0;  in imx290_get_selection()
1212 	return 0;  in imx290_entity_init_cfg()
1249 	imx290->current_mode = &imx290_modes_ptr(imx290)[0];  in imx290_subdev_init()
1260 	if (ret < 0) {  in imx290_subdev_init()
1266 	if (ret < 0) {  in imx290_subdev_init()
1274 	if (ret < 0) {  in imx290_subdev_init()
1283 	return 0;  in imx290_subdev_init()
1322 	gpiod_set_value_cansleep(imx290->rst_gpio, 0);  in imx290_power_on()
1325 	return 0;  in imx290_power_on()
1350 	return 0;  in imx290_runtime_suspend()
1371 	for (i = 0; i < ARRAY_SIZE(imx290->supplies); i++)  in imx290_get_regulators()
1410 	return 0;  in imx290_init_clk()
1414  * Returns 0 if all link frequencies used by the driver for the given number
1425 	for (i = 0; i < freqs_count; i++) {  in imx290_check_link_freqs()
1426 		for (j = 0; j < ep->nr_of_link_frequencies; j++)  in imx290_check_link_freqs()
1432 	return 0;  in imx290_check_link_freqs()
1509 	ret = 0;  in imx290_parse_dt()
1544 	if (ret < 0)  in imx290_probe()
1564 	if (ret < 0) {  in imx290_probe()
1594 	if (ret < 0) {  in imx290_probe()
1606 	return 0;  in imx290_probe()