30 	saa7146_write(dev, BASE_EVEN3,	dma_addr);  in vbi_workaround()
31 	saa7146_write(dev, BASE_ODD3,	dma_addr+vbi_pixel_to_capture);  in vbi_workaround()
32 	saa7146_write(dev, PROT_ADDR3,	dma_addr+4096);  in vbi_workaround()
33 	saa7146_write(dev, PITCH3,	vbi_pixel_to_capture);  in vbi_workaround()
34 	saa7146_write(dev, BASE_PAGE3,	0x0);  in vbi_workaround()
35 	saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));  in vbi_workaround()
36 	saa7146_write(dev, MC2, MASK_04|MASK_20);  in vbi_workaround()
89 		saa7146_write(dev, MC2, MASK_31|MASK_15);  in vbi_workaround()
91 		saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));  in vbi_workaround()
92 		saa7146_write(dev, MC2, MASK_04|MASK_20);  in vbi_workaround()
102 		saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);  in vbi_workaround()
103 		saa7146_write(dev, MC1, (MASK_13 | MASK_29));  in vbi_workaround()
116 		saa7146_write(dev, MC1, MASK_20);  in vbi_workaround()
124 			saa7146_write(dev, MC1, MASK_29);  in vbi_workaround()
199 	saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);  in saa7146_set_vbi_capture()
202 	saa7146_write(dev, MC1, (MASK_13 | MASK_29));  in saa7146_set_vbi_capture()
317 	saa7146_write(dev, MC1, MASK_29);  in vbi_stop()
323 	saa7146_write(dev, MC1, MASK_20);  in vbi_stop()
358 	saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);  in vbi_begin()
359 	saa7146_write(dev, MC2, (MASK_04|MASK_20));  in vbi_begin()
365 		saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));  in vbi_begin()
367 		saa7146_write(dev, BRS_CTRL, 0x00000001);  in vbi_begin()
376 	saa7146_write(dev, MC2, (MASK_08|MASK_24));  in vbi_begin()