1 // SPDX-License-Identifier: GPL-2.0-only
38 #define REG_EDGE_POL_EDGE(params, x)	BIT((params)->edge_single_offset + (x))
39 #define REG_EDGE_POL_LOW(params, x)	BIT((params)->pol_low_offset + (x))
40 #define REG_BOTH_EDGE(params, x)	BIT((params)->edge_both_offset + (x))
158 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
159 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
160 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
161 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
162 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
163 	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
164 	{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
165 	{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
166 	{ .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
167 	{ .compatible = "amlogic,c3-gpio-intc", .data = &c3_params },
185 	raw_spin_lock_irqsave(&ctl->lock, flags);  in meson_gpio_irq_update_bits()
187 	tmp = readl_relaxed(ctl->base + reg);  in meson_gpio_irq_update_bits()
190 	writel_relaxed(tmp, ctl->base + reg);  in meson_gpio_irq_update_bits()
192 	raw_spin_unlock_irqrestore(&ctl->lock, flags);  in meson_gpio_irq_update_bits()
209 				   ctl->params->pin_sel_mask << bit_offset,  in meson8_gpio_irq_sel_pin()
224 				   ctl->params->pin_sel_mask << bit_offset,  in meson_a1_gpio_irq_sel_pin()
242 	raw_spin_lock_irqsave(&ctl->lock, flags);  in meson_gpio_irq_request_channel()
245 	idx = find_first_zero_bit(ctl->channel_map, ctl->params->nr_channels);  in meson_gpio_irq_request_channel()
246 	if (idx >= ctl->params->nr_channels) {  in meson_gpio_irq_request_channel()
247 		raw_spin_unlock_irqrestore(&ctl->lock, flags);  in meson_gpio_irq_request_channel()
249 		return -ENOSPC;  in meson_gpio_irq_request_channel()
253 	set_bit(idx, ctl->channel_map);  in meson_gpio_irq_request_channel()
255 	raw_spin_unlock_irqrestore(&ctl->lock, flags);  in meson_gpio_irq_request_channel()
261 	ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);  in meson_gpio_irq_request_channel()
269 	*channel_hwirq = &(ctl->channel_irqs[idx]);  in meson_gpio_irq_request_channel()
271 	pr_debug("hwirq %lu assigned to channel %d - irq %u\n",  in meson_gpio_irq_request_channel()
281 	return channel_hwirq - ctl->channel_irqs;  in meson_gpio_irq_get_channel_idx()
291 	clear_bit(idx, ctl->channel_map);  in meson_gpio_irq_release_channel()
301 	params = ctl->params;  in meson8_gpio_irq_set_type()
318 		if (!params->support_edge_both)  in meson8_gpio_irq_set_type()
319 			return -EINVAL;  in meson8_gpio_irq_set_type()
337  * gpio irq relative registers for s4
338  * -PADCTRL_GPIO_IRQ_CTRL0
340  * bit[12-23]: single edge trigger
341  * bit[0-11]:  polarity trigger
343  * -PADCTRL_GPIO_IRQ_CTRL[X]
344  * bit[0-16]: 7 bits to choose gpio source for irq line 2*[X] - 2
345  * bit[16-22]:7 bits to choose gpio source for irq line 2*[X] - 1
346  * where X = 1-6
348  * -PADCTRL_GPIO_IRQ_CTRL[7]
349  * bit[0-11]: both edge trigger
364 		val |= BIT(ctl->params->edge_both_offset + idx);  in meson_s4_gpio_irq_set_type()
366 					   BIT(ctl->params->edge_both_offset + idx), val);  in meson_s4_gpio_irq_set_type()
371 		val |= BIT(ctl->params->pol_low_offset + idx);  in meson_s4_gpio_irq_set_type()
374 		val |= BIT(ctl->params->edge_single_offset + idx);  in meson_s4_gpio_irq_set_type()
401 	struct meson_gpio_irq_controller *ctl = data->domain->host_data;  in meson_gpio_irq_set_type()
405 	ret = ctl->params->ops.gpio_irq_set_type(ctl, type, channel_hwirq);  in meson_gpio_irq_set_type()
414 	.name			= "meson-gpio-irqchip",
431 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {  in meson_gpio_irq_domain_translate()
432 		*hwirq	= fwspec->param[0];  in meson_gpio_irq_domain_translate()
433 		*type	= fwspec->param[1];  in meson_gpio_irq_domain_translate()
437 	return -EINVAL;  in meson_gpio_irq_domain_translate()
447 	fwspec.fwnode = domain->parent->fwnode;  in meson_gpio_irq_allocate_gic_irq()
462 	struct meson_gpio_irq_controller *ctl = domain->host_data;  in meson_gpio_irq_domain_alloc()
469 		return -EINVAL;  in meson_gpio_irq_domain_alloc()
497 	struct meson_gpio_irq_controller *ctl = domain->host_data;  in meson_gpio_irq_domain_free()
525 		return -ENODEV;  in meson_gpio_irq_parse_dt()
527 	ctl->params = match->data;  in meson_gpio_irq_parse_dt()
530 						  "amlogic,channel-interrupts",  in meson_gpio_irq_parse_dt()
531 						  ctl->channel_irqs,  in meson_gpio_irq_parse_dt()
532 						  ctl->params->nr_channels,  in meson_gpio_irq_parse_dt()
533 						  ctl->params->nr_channels);  in meson_gpio_irq_parse_dt()
535 		pr_err("can't get %d channel interrupts\n", ctl->params->nr_channels);  in meson_gpio_irq_parse_dt()
539 	ctl->params->ops.gpio_irq_init(ctl);  in meson_gpio_irq_parse_dt()
552 		return -ENODEV;  in meson_gpio_irq_of_init()
558 		return -ENXIO;  in meson_gpio_irq_of_init()
563 		return -ENOMEM;  in meson_gpio_irq_of_init()
565 	raw_spin_lock_init(&ctl->lock);  in meson_gpio_irq_of_init()
567 	ctl->base = of_iomap(node, 0);  in meson_gpio_irq_of_init()
568 	if (!ctl->base) {  in meson_gpio_irq_of_init()
569 		ret = -ENOMEM;  in meson_gpio_irq_of_init()
578 					     ctl->params->nr_hwirq,  in meson_gpio_irq_of_init()
584 		ret = -ENODEV;  in meson_gpio_irq_of_init()
588 	pr_info("%d to %d gpio interrupt mux initialized\n",  in meson_gpio_irq_of_init()
589 		ctl->params->nr_hwirq, ctl->params->nr_channels);  in meson_gpio_irq_of_init()
594 	iounmap(ctl->base);  in meson_gpio_irq_of_init()
602 IRQCHIP_MATCH("amlogic,meson-gpio-intc", meson_gpio_irq_of_init)
607 MODULE_ALIAS("platform:meson-gpio-intc");