58 	struct irq_chip_generic		*gc;  member
73 	struct irq_chip_generic *gc = handler->priv->gc;  in liointc_chained_handle_irq()  local
84 			(handler->parent_int_map & gc->mask_cache &  in liointc_chained_handle_irq()
94 		generic_handle_domain_irq(gc->domain, bit);  in liointc_chained_handle_irq()
101 static void liointc_set_bit(struct irq_chip_generic *gc,  in liointc_set_bit()  argument
106 		writel(readl(gc->reg_base + offset) | mask,  in liointc_set_bit()
107 				gc->reg_base + offset);  in liointc_set_bit()
109 		writel(readl(gc->reg_base + offset) & ~mask,  in liointc_set_bit()
110 				gc->reg_base + offset);  in liointc_set_bit()
115 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in liointc_set_type()  local
119 	irq_gc_lock_irqsave(gc, flags);  in liointc_set_type()
122 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);  in liointc_set_type()
123 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);  in liointc_set_type()
126 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);  in liointc_set_type()
127 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);  in liointc_set_type()
130 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);  in liointc_set_type()
131 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);  in liointc_set_type()
134 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);  in liointc_set_type()
135 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);  in liointc_set_type()
138 		irq_gc_unlock_irqrestore(gc, flags);  in liointc_set_type()
141 	irq_gc_unlock_irqrestore(gc, flags);  in liointc_set_type()
147 static void liointc_suspend(struct irq_chip_generic *gc)  in liointc_suspend()  argument
149 	struct liointc_priv *priv = gc->private;  in liointc_suspend()
151 	priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);  in liointc_suspend()
152 	priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);  in liointc_suspend()
155 static void liointc_resume(struct irq_chip_generic *gc)  in liointc_resume()  argument
157 	struct liointc_priv *priv = gc->private;  in liointc_resume()
161 	irq_gc_lock_irqsave(gc, flags);  in liointc_resume()
163 	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);  in liointc_resume()
166 		writeb(priv->map_cache[i], gc->reg_base + i);  in liointc_resume()
167 	writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);  in liointc_resume()
168 	writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);  in liointc_resume()
170 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);  in liointc_resume()
171 	irq_gc_unlock_irqrestore(gc, flags);  in liointc_resume()
207 	struct irq_chip_generic *gc;  in liointc_init()  local
284 	gc = irq_get_domain_generic_chip(domain, 0);  in liointc_init()
285 	gc->private = priv;  in liointc_init()
286 	gc->reg_base = base;  in liointc_init()
287 	gc->domain = domain;  in liointc_init()
288 	gc->suspend = liointc_suspend;  in liointc_init()
289 	gc->resume = liointc_resume;  in liointc_init()
291 	ct = gc->chip_types;  in liointc_init()
300 	gc->mask_cache = 0;  in liointc_init()
301 	priv->gc = gc;  in liointc_init()