Lines Matching +full:dte +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
14 #include <linux/pci-ats.h>
19 #include <linux/dma-map-ops.h>
20 #include <linux/dma-direct.h>
21 #include <linux/iommu-helper.h>
23 #include <linux/amd-iommu.h>
30 #include <linux/io-pgtable.h>
42 #include "../dma-iommu.h"
45 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
70 int amd_iommu_max_glx_val = -1;
97 return -ENODEV; in get_acpihid_device_id()
100 if (acpi_dev_hid_uid_match(adev, p->hid, in get_acpihid_device_id()
101 p->uid[0] ? p->uid : NULL)) { in get_acpihid_device_id()
104 return p->devid; in get_acpihid_device_id()
107 return -EINVAL; in get_acpihid_device_id()
125 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in get_dev_table()
128 dev_table = pci_seg->dev_table; in get_dev_table()
141 seg = pci_domain_nr(pdev->bus); in get_device_segment()
154 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in amd_iommu_set_rlookup_table()
156 pci_seg->rlookup_table[devid] = iommu; in amd_iommu_set_rlookup_table()
164 if (pci_seg->id == seg) in __rlookup_amd_iommu()
165 return pci_seg->rlookup_table[devid]; in __rlookup_amd_iommu()
188 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in alloc_dev_data()
194 spin_lock_init(&dev_data->lock); in alloc_dev_data()
195 dev_data->devid = devid; in alloc_dev_data()
196 ratelimit_default_init(&dev_data->rs); in alloc_dev_data()
198 llist_add(&dev_data->dev_data_list, &pci_seg->dev_data_list); in alloc_dev_data()
206 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in search_dev_data()
208 if (llist_empty(&pci_seg->dev_data_list)) in search_dev_data()
211 node = pci_seg->dev_data_list.first; in search_dev_data()
213 if (dev_data->devid == devid) in search_dev_data()
229 iommu = rlookup_amd_iommu(&pdev->dev); in clone_alias()
255 clone_alias(pdev, iommu->pci_seg->alias_table[pci_dev_id(pdev)], NULL); in clone_aliases()
263 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in setup_aliases()
274 ivrs_alias = pci_seg->alias_table[pci_dev_id(pdev)]; in setup_aliases()
276 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) in setup_aliases()
294 dev_data->defer_attach = true; in find_dev_data()
313 if ((devid == p->devid) && p->group) in acpihid_device_group()
314 entry->group = p->group; in acpihid_device_group()
317 if (!entry->group) in acpihid_device_group()
318 entry->group = generic_device_group(dev); in acpihid_device_group()
320 iommu_group_ref_get(entry->group); in acpihid_device_group()
322 return entry->group; in acpihid_device_group()
368 pci_seg = iommu->pci_seg; in check_device()
369 if (devid > pci_seg->last_bdf) in check_device()
390 return -ENOMEM; in iommu_init_device()
392 dev_data->dev = dev; in iommu_init_device()
396 * By default we use passthrough mode for IOMMUv2 capable device. in iommu_init_device()
399 * it'll be forced to go into translation mode. in iommu_init_device()
403 dev_data->iommu_v2 = iommu->is_iommu_v2; in iommu_init_device()
413 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in iommu_ignore_device()
422 pci_seg->rlookup_table[devid] = NULL; in iommu_ignore_device()
436 if (dev_data->domain) in amd_iommu_uninit_device()
443 * device is re-plugged - not doing so would introduce a ton of races. in amd_iommu_uninit_device()
459 pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]); in dump_dte_entry()
468 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); in dump_command()
483 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), in amd_iommu_report_rmp_hw_error()
486 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_report_rmp_hw_error()
489 if (__ratelimit(&dev_data->rs)) { in amd_iommu_report_rmp_hw_error()
495 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in amd_iommu_report_rmp_hw_error()
516 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), in amd_iommu_report_rmp_fault()
519 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_report_rmp_fault()
522 if (__ratelimit(&dev_data->rs)) { in amd_iommu_report_rmp_fault()
528 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in amd_iommu_report_rmp_fault()
549 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), in amd_iommu_report_page_fault()
552 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_report_page_fault()
562 if (dev_data->domain == NULL) { in amd_iommu_report_page_fault()
565 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), in amd_iommu_report_page_fault()
570 if (!report_iommu_fault(&dev_data->domain->domain, in amd_iommu_report_page_fault()
571 &pdev->dev, address, in amd_iommu_report_page_fault()
578 if (__ratelimit(&dev_data->rs)) { in amd_iommu_report_page_fault()
584 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in amd_iommu_report_page_fault()
595 struct device *dev = iommu->iommu.dev; in iommu_print_event()
628 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
635 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
640 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
653 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
658 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
671 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
693 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_poll_events()
694 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_poll_events()
697 iommu_print_event(iommu, iommu->evt_buf + head); in iommu_poll_events()
701 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_poll_events()
715 fault.sbdf = PCI_SEG_DEVID_TO_SBDF(iommu->pci_seg->id, PPR_DEVID(raw[0])); in iommu_handle_ppr_entry()
726 if (iommu->ppr_log == NULL) in iommu_poll_ppr_log()
729 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_poll_ppr_log()
730 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_poll_ppr_log()
737 raw = (u64 *)(iommu->ppr_log + head); in iommu_poll_ppr_log()
750 /* Avoid memcpy function-call overhead */ in iommu_poll_ppr_log()
763 /* Update head pointer of hardware ring-buffer */ in iommu_poll_ppr_log()
765 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_poll_ppr_log()
770 /* Refresh ring-buffer information */ in iommu_poll_ppr_log()
771 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_poll_ppr_log()
772 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_poll_ppr_log()
791 if (iommu->ga_log == NULL) in iommu_poll_ga_log()
794 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_poll_ga_log()
795 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_poll_ga_log()
801 raw = (u64 *)(iommu->ga_log + head); in iommu_poll_ga_log()
803 /* Avoid memcpy function-call overhead */ in iommu_poll_ga_log()
806 /* Update head pointer of hardware ring-buffer */ in iommu_poll_ga_log()
808 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_poll_ga_log()
836 dev_set_msi_domain(dev, iommu->ir_domain); in amd_iommu_set_pci_msi_domain()
850 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_handle_irq()
855 writel(mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_handle_irq()
859 iommu->index, evt_type); in amd_iommu_handle_irq()
868 * When re-enabling interrupt (by writing 1 in amd_iommu_handle_irq()
877 * again and re-clear the bits in amd_iommu_handle_irq()
879 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_handle_irq()
936 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) { in wait_on_sem()
942 pr_alert("Completion-Wait loop timed out\n"); in wait_on_sem()
943 return -EIO; in wait_on_sem()
956 tail = iommu->cmd_buf_tail; in copy_cmd_to_buffer()
957 target = iommu->cmd_buf + tail; in copy_cmd_to_buffer()
961 iommu->cmd_buf_tail = tail; in copy_cmd_to_buffer()
964 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in copy_cmd_to_buffer()
971 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); in build_completion_wait()
974 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; in build_completion_wait()
975 cmd->data[1] = upper_32_bits(paddr); in build_completion_wait()
976 cmd->data[2] = lower_32_bits(data); in build_completion_wait()
977 cmd->data[3] = upper_32_bits(data); in build_completion_wait()
984 cmd->data[0] = devid; in build_inv_dte()
1001 end = address + size - 1; in build_inv_address()
1007 msb_diff = fls64(end ^ address) - 1; in build_inv_address()
1017 * The msb-bit must be clear on the address. Just set all the in build_inv_address()
1020 address |= (1ull << msb_diff) - 1; in build_inv_address()
1026 /* Set the size bit - we flush more than one 4kb page */ in build_inv_address()
1036 cmd->data[1] |= domid; in build_inv_iommu_pages()
1037 cmd->data[2] = lower_32_bits(inv_address); in build_inv_iommu_pages()
1038 cmd->data[3] = upper_32_bits(inv_address); in build_inv_iommu_pages()
1040 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ in build_inv_iommu_pages()
1041 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; in build_inv_iommu_pages()
1050 cmd->data[0] = devid; in build_inv_iotlb_pages()
1051 cmd->data[0] |= (qdep & 0xff) << 24; in build_inv_iotlb_pages()
1052 cmd->data[1] = devid; in build_inv_iotlb_pages()
1053 cmd->data[2] = lower_32_bits(inv_address); in build_inv_iotlb_pages()
1054 cmd->data[3] = upper_32_bits(inv_address); in build_inv_iotlb_pages()
1065 cmd->data[0] = pasid; in build_inv_iommu_pasid()
1066 cmd->data[1] = domid; in build_inv_iommu_pasid()
1067 cmd->data[2] = lower_32_bits(address); in build_inv_iommu_pasid()
1068 cmd->data[3] = upper_32_bits(address); in build_inv_iommu_pasid()
1069 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; in build_inv_iommu_pasid()
1070 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; in build_inv_iommu_pasid()
1072 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; in build_inv_iommu_pasid()
1083 cmd->data[0] = devid; in build_inv_iotlb_pasid()
1084 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; in build_inv_iotlb_pasid()
1085 cmd->data[0] |= (qdep & 0xff) << 24; in build_inv_iotlb_pasid()
1086 cmd->data[1] = devid; in build_inv_iotlb_pasid()
1087 cmd->data[1] |= (pasid & 0xff) << 16; in build_inv_iotlb_pasid()
1088 cmd->data[2] = lower_32_bits(address); in build_inv_iotlb_pasid()
1089 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; in build_inv_iotlb_pasid()
1090 cmd->data[3] = upper_32_bits(address); in build_inv_iotlb_pasid()
1092 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; in build_inv_iotlb_pasid()
1101 cmd->data[0] = devid; in build_complete_ppr()
1103 cmd->data[1] = pasid; in build_complete_ppr()
1104 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; in build_complete_ppr()
1106 cmd->data[3] = tag & 0x1ff; in build_complete_ppr()
1107 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; in build_complete_ppr()
1121 cmd->data[0] = devid; in build_inv_irt()
1136 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; in __iommu_queue_command_sync()
1138 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; in __iommu_queue_command_sync()
1145 return -EIO; in __iommu_queue_command_sync()
1152 iommu->cmd_buf_head = readl(iommu->mmio_base + in __iommu_queue_command_sync()
1161 iommu->need_sync = sync; in __iommu_queue_command_sync()
1173 raw_spin_lock_irqsave(&iommu->lock, flags); in iommu_queue_command_sync()
1175 raw_spin_unlock_irqrestore(&iommu->lock, flags); in iommu_queue_command_sync()
1196 if (!iommu->need_sync) in iommu_completion_wait()
1199 data = atomic64_add_return(1, &iommu->cmd_sem_val); in iommu_completion_wait()
1202 raw_spin_lock_irqsave(&iommu->lock, flags); in iommu_completion_wait()
1211 raw_spin_unlock_irqrestore(&iommu->lock, flags); in iommu_completion_wait()
1228 u16 last_bdf = iommu->pci_seg->last_bdf; in amd_iommu_flush_dte_all()
1243 u16 last_bdf = iommu->pci_seg->last_bdf; in amd_iommu_flush_tlb_all()
1288 u16 last_bdf = iommu->pci_seg->last_bdf; in amd_iommu_flush_irt_all()
1290 if (iommu->irtcachedis_enabled) in amd_iommu_flush_irt_all()
1311 * Command send function for flushing on-device TLB
1320 qdep = dev_data->ats.qdep; in device_flush_iotlb()
1321 iommu = rlookup_amd_iommu(dev_data->dev); in device_flush_iotlb()
1323 return -EINVAL; in device_flush_iotlb()
1325 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); in device_flush_iotlb()
1348 iommu = rlookup_amd_iommu(dev_data->dev); in device_flush_dte()
1350 return -EINVAL; in device_flush_dte()
1352 if (dev_is_pci(dev_data->dev)) in device_flush_dte()
1353 pdev = to_pci_dev(dev_data->dev); in device_flush_dte()
1359 ret = iommu_flush_dte(iommu, dev_data->devid); in device_flush_dte()
1363 pci_seg = iommu->pci_seg; in device_flush_dte()
1364 alias = pci_seg->alias_table[dev_data->devid]; in device_flush_dte()
1365 if (alias != dev_data->devid) { in device_flush_dte()
1371 if (dev_data->ats.enabled) in device_flush_dte()
1389 build_inv_iommu_pages(&cmd, address, size, domain->id, pde); in __domain_flush_pages()
1392 if (!domain->dev_iommu[i]) in __domain_flush_pages()
1402 list_for_each_entry(dev_data, &domain->dev_list, list) { in __domain_flush_pages()
1404 if (!dev_data->ats.enabled) in __domain_flush_pages()
1438 * size is always non-zero, but address might be zero, causing in domain_flush_pages()
1441 * of the address on x86-32, cast to long when doing the check. in domain_flush_pages()
1452 size -= flush_size; in domain_flush_pages()
1456 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1467 if (domain && !domain->dev_iommu[i]) in amd_iommu_domain_flush_complete()
1485 spin_lock_irqsave(&domain->lock, flags); in domain_flush_np_cache()
1488 spin_unlock_irqrestore(&domain->lock, flags); in domain_flush_np_cache()
1500 list_for_each_entry(dev_data, &domain->dev_list, list) in domain_flush_devices()
1570 if (domain->glx == 2) in free_gcr3_table()
1571 free_gcr3_tbl_level2(domain->gcr3_tbl); in free_gcr3_table()
1572 else if (domain->glx == 1) in free_gcr3_table()
1573 free_gcr3_tbl_level1(domain->gcr3_tbl); in free_gcr3_table()
1575 BUG_ON(domain->glx != 0); in free_gcr3_table()
1577 free_page((unsigned long)domain->gcr3_tbl); in free_gcr3_table()
1588 if (domain->iop.mode != PAGE_MODE_NONE) in set_dte_entry()
1589 pte_root = iommu_virt_to_phys(domain->iop.root); in set_dte_entry()
1591 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK) in set_dte_entry()
1600 if (!amd_iommu_snp_en || (domain->id != 0)) in set_dte_entry()
1613 if (domain->flags & PD_IOMMUV2_MASK) { in set_dte_entry()
1614 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); in set_dte_entry()
1615 u64 glx = domain->glx; in set_dte_entry()
1628 /* Encode GCR3 table into DTE */ in set_dte_entry()
1643 if (domain->flags & PD_GIOV_MASK) in set_dte_entry()
1648 flags |= domain->id; in set_dte_entry()
1656 * the previous kernel--if so, it needs to flush the translation cache in set_dte_entry()
1685 iommu = rlookup_amd_iommu(dev_data->dev); in do_attach()
1688 ats = dev_data->ats.enabled; in do_attach()
1691 dev_data->domain = domain; in do_attach()
1692 list_add(&dev_data->list, &domain->dev_list); in do_attach()
1695 if (domain->nid == NUMA_NO_NODE) in do_attach()
1696 domain->nid = dev_to_node(dev_data->dev); in do_attach()
1699 domain->dev_iommu[iommu->index] += 1; in do_attach()
1700 domain->dev_cnt += 1; in do_attach()
1703 set_dte_entry(iommu, dev_data->devid, domain, in do_attach()
1704 ats, dev_data->iommu_v2); in do_attach()
1705 clone_aliases(iommu, dev_data->dev); in do_attach()
1712 struct protection_domain *domain = dev_data->domain; in do_detach()
1715 iommu = rlookup_amd_iommu(dev_data->dev); in do_detach()
1720 dev_data->domain = NULL; in do_detach()
1721 list_del(&dev_data->list); in do_detach()
1722 clear_dte_entry(iommu, dev_data->devid); in do_detach()
1723 clone_aliases(iommu, dev_data->dev); in do_detach()
1725 /* Flush the DTE entry */ in do_detach()
1734 /* decrease reference counters - needs to happen after the flushes */ in do_detach()
1735 domain->dev_iommu[iommu->index] -= 1; in do_detach()
1736 domain->dev_cnt -= 1; in do_detach()
1750 /* Only allow access to user-accessible pages */ in pdev_pri_ats_enable()
1793 spin_lock_irqsave(&domain->lock, flags); in attach_device()
1797 spin_lock(&dev_data->lock); in attach_device()
1799 ret = -EBUSY; in attach_device()
1800 if (dev_data->domain != NULL) in attach_device()
1807 if (domain->flags & PD_IOMMUV2_MASK) { in attach_device()
1810 ret = -EINVAL; in attach_device()
1813 * In case of using AMD_IOMMU_V1 page table mode and the device in attach_device()
1818 def_domain->type != IOMMU_DOMAIN_IDENTITY) { in attach_device()
1822 if (dev_data->iommu_v2) { in attach_device()
1826 dev_data->ats.enabled = true; in attach_device()
1827 dev_data->ats.qdep = pci_ats_queue_depth(pdev); in attach_device()
1828 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev); in attach_device()
1832 dev_data->ats.enabled = true; in attach_device()
1833 dev_data->ats.qdep = pci_ats_queue_depth(pdev); in attach_device()
1842 * We might boot into a crash-kernel here. The crashed kernel in attach_device()
1851 spin_unlock(&dev_data->lock); in attach_device()
1853 spin_unlock_irqrestore(&domain->lock, flags); in attach_device()
1868 domain = dev_data->domain; in detach_device()
1870 spin_lock_irqsave(&domain->lock, flags); in detach_device()
1872 spin_lock(&dev_data->lock); in detach_device()
1880 if (WARN_ON(!dev_data->domain)) in detach_device()
1888 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) in detach_device()
1890 else if (dev_data->ats.enabled) in detach_device()
1893 dev_data->ats.enabled = false; in detach_device()
1896 spin_unlock(&dev_data->lock); in detach_device()
1898 spin_unlock_irqrestore(&domain->lock, flags); in detach_device()
1908 return ERR_PTR(-ENODEV); in amd_iommu_probe_device()
1912 return ERR_PTR(-ENODEV); in amd_iommu_probe_device()
1915 if (!iommu->iommu.ops) in amd_iommu_probe_device()
1916 return ERR_PTR(-ENODEV); in amd_iommu_probe_device()
1919 return &iommu->iommu; in amd_iommu_probe_device()
1923 if (ret != -ENOTSUPP) in amd_iommu_probe_device()
1924 dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); in amd_iommu_probe_device()
1929 iommu_dev = &iommu->iommu; in amd_iommu_probe_device()
1939 /* Domains are initialized for this device - have a look what we ended up with */ in amd_iommu_probe_finalize()
1977 list_for_each_entry(dev_data, &domain->dev_list, list) { in update_device_table()
1978 struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev); in update_device_table()
1982 set_dte_entry(iommu, dev_data->devid, domain, in update_device_table()
1983 dev_data->ats.enabled, dev_data->iommu_v2); in update_device_table()
1984 clone_aliases(iommu, dev_data->dev); in update_device_table()
2019 spin_lock_irqsave(&domain->lock, flags); in cleanup_domain()
2021 while (!list_empty(&domain->dev_list)) { in cleanup_domain()
2022 entry = list_first_entry(&domain->dev_list, in cleanup_domain()
2024 BUG_ON(!entry->domain); in cleanup_domain()
2028 spin_unlock_irqrestore(&domain->lock, flags); in cleanup_domain()
2036 if (domain->iop.pgtbl_cfg.tlb) in protection_domain_free()
2037 free_io_pgtable_ops(&domain->iop.iop.ops); in protection_domain_free()
2039 if (domain->id) in protection_domain_free()
2040 domain_id_free(domain->id); in protection_domain_free()
2045 static int protection_domain_init_v1(struct protection_domain *domain, int mode) in protection_domain_init_v1() argument
2049 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL); in protection_domain_init_v1()
2051 spin_lock_init(&domain->lock); in protection_domain_init_v1()
2052 domain->id = domain_id_alloc(); in protection_domain_init_v1()
2053 if (!domain->id) in protection_domain_init_v1()
2054 return -ENOMEM; in protection_domain_init_v1()
2055 INIT_LIST_HEAD(&domain->dev_list); in protection_domain_init_v1()
2057 if (mode != PAGE_MODE_NONE) { in protection_domain_init_v1()
2060 domain_id_free(domain->id); in protection_domain_init_v1()
2061 return -ENOMEM; in protection_domain_init_v1()
2065 amd_iommu_domain_set_pgtable(domain, pt_root, mode); in protection_domain_init_v1()
2072 spin_lock_init(&domain->lock); in protection_domain_init_v2()
2073 domain->id = domain_id_alloc(); in protection_domain_init_v2()
2074 if (!domain->id) in protection_domain_init_v2()
2075 return -ENOMEM; in protection_domain_init_v2()
2076 INIT_LIST_HEAD(&domain->dev_list); in protection_domain_init_v2()
2078 domain->flags |= PD_GIOV_MASK; in protection_domain_init_v2()
2080 domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; in protection_domain_init_v2()
2083 domain_id_free(domain->id); in protection_domain_init_v2()
2084 return -ENOMEM; in protection_domain_init_v2()
2095 int mode = DEFAULT_PGTABLE_LEVEL; in protection_domain_alloc() local
2100 * when allocating domain for pass-through devices. in protection_domain_alloc()
2104 mode = PAGE_MODE_NONE; in protection_domain_alloc()
2119 ret = protection_domain_init_v1(domain, mode); in protection_domain_alloc()
2125 ret = -EINVAL; in protection_domain_alloc()
2131 /* No need to allocate io pgtable ops in passthrough mode */ in protection_domain_alloc()
2135 domain->nid = NUMA_NO_NODE; in protection_domain_alloc()
2137 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain); in protection_domain_alloc()
2139 domain_id_free(domain->id); in protection_domain_alloc()
2155 return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1); in dma_max_address()
2163 * Since DTE[Mode]=0 is prohibited on SNP-enabled system, in amd_iommu_domain_alloc()
2173 domain->domain.geometry.aperture_start = 0; in amd_iommu_domain_alloc()
2174 domain->domain.geometry.aperture_end = dma_max_address(); in amd_iommu_domain_alloc()
2175 domain->domain.geometry.force_aperture = true; in amd_iommu_domain_alloc()
2177 return &domain->domain; in amd_iommu_domain_alloc()
2186 if (domain->dev_cnt > 0) in amd_iommu_domain_free()
2189 BUG_ON(domain->dev_cnt != 0); in amd_iommu_domain_free()
2194 if (domain->flags & PD_IOMMUV2_MASK) in amd_iommu_domain_free()
2212 if (dev_data->domain == domain) in amd_iommu_attach_device()
2215 dev_data->defer_attach = false; in amd_iommu_attach_device()
2217 if (dev_data->domain) in amd_iommu_attach_device()
2224 if (dom->type == IOMMU_DOMAIN_UNMANAGED) in amd_iommu_attach_device()
2225 dev_data->use_vapic = 1; in amd_iommu_attach_device()
2227 dev_data->use_vapic = 0; in amd_iommu_attach_device()
2240 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_iotlb_sync_map()
2242 if (ops->map_pages) in amd_iommu_iotlb_sync_map()
2251 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_map_pages()
2253 int ret = -EINVAL; in amd_iommu_map_pages()
2256 (domain->iop.mode == PAGE_MODE_NONE)) in amd_iommu_map_pages()
2257 return -EINVAL; in amd_iommu_map_pages()
2264 if (ops->map_pages) { in amd_iommu_map_pages()
2265 ret = ops->map_pages(ops, iova, paddr, pgsize, in amd_iommu_map_pages()
2279 * to whether "non-present cache" is on, it is probably best to prefer in amd_iommu_iotlb_gather_add_page()
2283 * the guest, and the trade-off is different: unnecessary TLB flushes in amd_iommu_iotlb_gather_add_page()
2298 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_unmap_pages()
2302 (domain->iop.mode == PAGE_MODE_NONE)) in amd_iommu_unmap_pages()
2305 r = (ops->unmap_pages) ? ops->unmap_pages(ops, iova, pgsize, pgcount, NULL) : 0; in amd_iommu_unmap_pages()
2317 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_iova_to_phys()
2319 return ops->iova_to_phys(ops, iova); in amd_iommu_iova_to_phys()
2359 pci_seg = iommu->pci_seg; in amd_iommu_get_resv_regions()
2361 list_for_each_entry(entry, &pci_seg->unity_map, list) { in amd_iommu_get_resv_regions()
2365 if (devid < entry->devid_start || devid > entry->devid_end) in amd_iommu_get_resv_regions()
2369 length = entry->address_end - entry->address_start; in amd_iommu_get_resv_regions()
2370 if (entry->prot & IOMMU_PROT_IR) in amd_iommu_get_resv_regions()
2372 if (entry->prot & IOMMU_PROT_IW) in amd_iommu_get_resv_regions()
2374 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) in amd_iommu_get_resv_regions()
2378 region = iommu_alloc_resv_region(entry->address_start, in amd_iommu_get_resv_regions()
2382 dev_err(dev, "Out of memory allocating dm-regions\n"); in amd_iommu_get_resv_regions()
2385 list_add_tail(®ion->list, head); in amd_iommu_get_resv_regions()
2389 MSI_RANGE_END - MSI_RANGE_START + 1, in amd_iommu_get_resv_regions()
2393 list_add_tail(®ion->list, head); in amd_iommu_get_resv_regions()
2396 HT_RANGE_END - HT_RANGE_START + 1, in amd_iommu_get_resv_regions()
2400 list_add_tail(®ion->list, head); in amd_iommu_get_resv_regions()
2407 return dev_data->defer_attach; in amd_iommu_is_attach_deferred()
2416 spin_lock_irqsave(&dom->lock, flags); in amd_iommu_flush_iotlb_all()
2419 spin_unlock_irqrestore(&dom->lock, flags); in amd_iommu_flush_iotlb_all()
2428 spin_lock_irqsave(&dom->lock, flags); in amd_iommu_iotlb_sync()
2429 domain_flush_pages(dom, gather->start, gather->end - gather->start + 1, 1); in amd_iommu_iotlb_sync()
2431 spin_unlock_irqrestore(&dom->lock, flags); in amd_iommu_iotlb_sync()
2444 * - memory encryption is active, because some of those devices in amd_iommu_def_domain_type()
2445 * (AMD GPUs) don't have the encryption bit in their DMA-mask in amd_iommu_def_domain_type()
2447 * - SNP is enabled, because it prohibits DTE[Mode]=0. in amd_iommu_def_domain_type()
2449 if (dev_data->iommu_v2 && in amd_iommu_def_domain_type()
2491 * mode
2493 * In passthrough mode the IOMMU is initialized and enabled but not used for
2494 * DMA-API translation.
2516 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_domain_direct_map()
2518 if (domain->iop.pgtbl_cfg.tlb) in amd_iommu_domain_direct_map()
2519 free_io_pgtable_ops(&domain->iop.iop.ops); in amd_iommu_domain_direct_map()
2521 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_domain_direct_map()
2525 /* Note: This function expects iommu_domain->lock to be held prior calling the function. */
2531 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) in domain_enable_v2()
2535 return -EINVAL; in domain_enable_v2()
2537 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); in domain_enable_v2()
2538 if (domain->gcr3_tbl == NULL) in domain_enable_v2()
2539 return -ENOMEM; in domain_enable_v2()
2541 domain->glx = levels; in domain_enable_v2()
2542 domain->flags |= PD_IOMMUV2_MASK; in domain_enable_v2()
2555 spin_lock_irqsave(&pdom->lock, flags); in amd_iommu_domain_enable_v2()
2560 * devices attached when it is switched into IOMMUv2 mode. in amd_iommu_domain_enable_v2()
2562 ret = -EBUSY; in amd_iommu_domain_enable_v2()
2563 if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK) in amd_iommu_domain_enable_v2()
2566 if (!pdom->gcr3_tbl) in amd_iommu_domain_enable_v2()
2570 spin_unlock_irqrestore(&pdom->lock, flags); in amd_iommu_domain_enable_v2()
2582 if (!(domain->flags & PD_IOMMUV2_MASK)) in __flush_pasid()
2583 return -EINVAL; in __flush_pasid()
2585 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); in __flush_pasid()
2592 if (domain->dev_iommu[i] == 0) in __flush_pasid()
2604 list_for_each_entry(dev_data, &domain->dev_list, list) { in __flush_pasid()
2609 There might be non-IOMMUv2 capable devices in an IOMMUv2 in __flush_pasid()
2612 if (!dev_data->ats.enabled) in __flush_pasid()
2615 qdep = dev_data->ats.qdep; in __flush_pasid()
2616 iommu = rlookup_amd_iommu(dev_data->dev); in __flush_pasid()
2619 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, in __flush_pasid()
2650 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_flush_page()
2652 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_flush_page()
2670 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_flush_tlb()
2672 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_flush_tlb()
2704 level -= 1; in __get_gcr3_pte()
2715 if (domain->iop.mode != PAGE_MODE_NONE) in __set_gcr3()
2716 return -EINVAL; in __set_gcr3()
2718 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); in __set_gcr3()
2720 return -ENOMEM; in __set_gcr3()
2731 if (domain->iop.mode != PAGE_MODE_NONE) in __clear_gcr3()
2732 return -EINVAL; in __clear_gcr3()
2734 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); in __clear_gcr3()
2750 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_domain_set_gcr3()
2752 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_domain_set_gcr3()
2764 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_domain_clear_gcr3()
2766 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_domain_clear_gcr3()
2779 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_complete_ppr()
2780 iommu = rlookup_amd_iommu(&pdev->dev); in amd_iommu_complete_ppr()
2782 return -ENODEV; in amd_iommu_complete_ppr()
2784 build_complete_ppr(&cmd, dev_data->devid, pasid, status, in amd_iommu_complete_ppr()
2785 tag, dev_data->pri_tlp); in amd_iommu_complete_ppr()
2798 return -EINVAL; in amd_iommu_device_info()
2801 return -EINVAL; in amd_iommu_device_info()
2806 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; in amd_iommu_device_info()
2810 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; in amd_iommu_device_info()
2819 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; in amd_iommu_device_info()
2820 info->max_pasids = min(pci_max_pasids(pdev), max_pasids); in amd_iommu_device_info()
2824 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; in amd_iommu_device_info()
2826 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; in amd_iommu_device_info()
2851 if (iommu->irtcachedis_enabled) in iommu_flush_irt_and_complete()
2855 data = atomic64_add_return(1, &iommu->cmd_sem_val); in iommu_flush_irt_and_complete()
2858 raw_spin_lock_irqsave(&iommu->lock, flags); in iommu_flush_irt_and_complete()
2867 raw_spin_unlock_irqrestore(&iommu->lock, flags); in iommu_flush_irt_and_complete()
2873 u64 dte; in set_dte_irq_entry() local
2876 dte = dev_table[devid].data[2]; in set_dte_irq_entry()
2877 dte &= ~DTE_IRQ_PHYS_ADDR_MASK; in set_dte_irq_entry()
2878 dte |= iommu_virt_to_phys(table->table); in set_dte_irq_entry()
2879 dte |= DTE_IRQ_REMAP_INTCTL; in set_dte_irq_entry()
2880 dte |= DTE_INTTABLEN; in set_dte_irq_entry()
2881 dte |= DTE_IRQ_REMAP_ENABLE; in set_dte_irq_entry()
2883 dev_table[devid].data[2] = dte; in set_dte_irq_entry()
2889 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in get_irq_table()
2891 if (WARN_ONCE(!pci_seg->rlookup_table[devid], in get_irq_table()
2893 __func__, pci_seg->id, devid)) in get_irq_table()
2896 table = pci_seg->irq_lookup_table[devid]; in get_irq_table()
2898 __func__, pci_seg->id, devid)) in get_irq_table()
2912 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); in __alloc_irq_table()
2913 if (!table->table) { in __alloc_irq_table()
2917 raw_spin_lock_init(&table->lock); in __alloc_irq_table()
2920 memset(table->table, 0, in __alloc_irq_table()
2923 memset(table->table, 0, in __alloc_irq_table()
2931 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in set_remap_table_entry()
2933 pci_seg->irq_lookup_table[devid] = table; in set_remap_table_entry()
2943 struct amd_iommu *iommu = rlookup_amd_iommu(&pdev->dev); in set_remap_table_entry_alias()
2946 return -EINVAL; in set_remap_table_entry_alias()
2948 pci_seg = iommu->pci_seg; in set_remap_table_entry_alias()
2949 pci_seg->irq_lookup_table[alias] = table; in set_remap_table_entry_alias()
2951 iommu_flush_dte(pci_seg->rlookup_table[alias], alias); in set_remap_table_entry_alias()
2967 pci_seg = iommu->pci_seg; in alloc_irq_table()
2968 table = pci_seg->irq_lookup_table[devid]; in alloc_irq_table()
2972 alias = pci_seg->alias_table[devid]; in alloc_irq_table()
2973 table = pci_seg->irq_lookup_table[alias]; in alloc_irq_table()
2987 table = pci_seg->irq_lookup_table[devid]; in alloc_irq_table()
2991 table = pci_seg->irq_lookup_table[alias]; in alloc_irq_table()
3016 kmem_cache_free(amd_iommu_irq_cache, new_table->table); in alloc_irq_table()
3031 return -ENODEV; in alloc_irq_index()
3036 raw_spin_lock_irqsave(&table->lock, flags); in alloc_irq_index()
3039 for (index = ALIGN(table->min_index, alignment), c = 0; in alloc_irq_index()
3041 if (!iommu->irte_ops->is_allocated(table, index)) { in alloc_irq_index()
3050 for (; c != 0; --c) in alloc_irq_index()
3051 iommu->irte_ops->set_allocated(table, index - c + 1); in alloc_irq_index()
3053 index -= count - 1; in alloc_irq_index()
3060 index = -ENOSPC; in alloc_irq_index()
3063 raw_spin_unlock_irqrestore(&table->lock, flags); in alloc_irq_index()
3078 return -ENOMEM; in modify_irte_ga()
3080 raw_spin_lock_irqsave(&table->lock, flags); in modify_irte_ga()
3082 entry = (struct irte_ga *)table->table; in modify_irte_ga()
3086 * We use cmpxchg16 to atomically update the 128-bit IRTE, in modify_irte_ga()
3091 old = entry->irte; in modify_irte_ga()
3092 WARN_ON(!try_cmpxchg128(&entry->irte, &old, irte->irte)); in modify_irte_ga()
3094 raw_spin_unlock_irqrestore(&table->lock, flags); in modify_irte_ga()
3109 return -ENOMEM; in modify_irte()
3111 raw_spin_lock_irqsave(&table->lock, flags); in modify_irte()
3112 table->table[index] = irte->val; in modify_irte()
3113 raw_spin_unlock_irqrestore(&table->lock, flags); in modify_irte()
3129 raw_spin_lock_irqsave(&table->lock, flags); in free_irte()
3130 iommu->irte_ops->clear_allocated(table, index); in free_irte()
3131 raw_spin_unlock_irqrestore(&table->lock, flags); in free_irte()
3142 irte->val = 0; in irte_prepare()
3143 irte->fields.vector = vector; in irte_prepare()
3144 irte->fields.int_type = delivery_mode; in irte_prepare()
3145 irte->fields.destination = dest_apicid; in irte_prepare()
3146 irte->fields.dm = dest_mode; in irte_prepare()
3147 irte->fields.valid = 1; in irte_prepare()
3156 irte->lo.val = 0; in irte_ga_prepare()
3157 irte->hi.val = 0; in irte_ga_prepare()
3158 irte->lo.fields_remap.int_type = delivery_mode; in irte_ga_prepare()
3159 irte->lo.fields_remap.dm = dest_mode; in irte_ga_prepare()
3160 irte->hi.fields.vector = vector; in irte_ga_prepare()
3161 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); in irte_ga_prepare()
3162 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); in irte_ga_prepare()
3163 irte->lo.fields_remap.valid = 1; in irte_ga_prepare()
3170 irte->fields.valid = 1; in irte_activate()
3178 irte->lo.fields_remap.valid = 1; in irte_ga_activate()
3186 irte->fields.valid = 0; in irte_deactivate()
3194 irte->lo.fields_remap.valid = 0; in irte_ga_deactivate()
3203 irte->fields.vector = vector; in irte_set_affinity()
3204 irte->fields.destination = dest_apicid; in irte_set_affinity()
3213 if (!irte->lo.fields_remap.guest_mode) { in irte_ga_set_affinity()
3214 irte->hi.fields.vector = vector; in irte_ga_set_affinity()
3215 irte->lo.fields_remap.destination = in irte_ga_set_affinity()
3217 irte->hi.fields.destination = in irte_ga_set_affinity()
3226 table->table[index] = IRTE_ALLOCATED; in irte_set_allocated()
3231 struct irte_ga *ptr = (struct irte_ga *)table->table; in irte_ga_set_allocated()
3234 memset(&irte->lo.val, 0, sizeof(u64)); in irte_ga_set_allocated()
3235 memset(&irte->hi.val, 0, sizeof(u64)); in irte_ga_set_allocated()
3236 irte->hi.fields.vector = 0xff; in irte_ga_set_allocated()
3241 union irte *ptr = (union irte *)table->table; in irte_is_allocated()
3244 return irte->val != 0; in irte_is_allocated()
3249 struct irte_ga *ptr = (struct irte_ga *)table->table; in irte_ga_is_allocated()
3252 return irte->hi.fields.vector != 0; in irte_ga_is_allocated()
3257 table->table[index] = 0; in irte_clear_allocated()
3262 struct irte_ga *ptr = (struct irte_ga *)table->table; in irte_ga_clear_allocated()
3265 memset(&irte->lo.val, 0, sizeof(u64)); in irte_ga_clear_allocated()
3266 memset(&irte->hi.val, 0, sizeof(u64)); in irte_ga_clear_allocated()
3271 switch (info->type) { in get_devid()
3273 return get_ioapic_devid(info->devid); in get_devid()
3275 return get_hpet_devid(info->devid); in get_devid()
3278 return get_device_sbdf_id(msi_desc_to_dev(info->desc)); in get_devid()
3281 return -1; in get_devid()
3295 msg->data = index; in fill_msi_msg()
3296 msg->address_lo = 0; in fill_msi_msg()
3297 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; in fill_msi_msg()
3298 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; in fill_msi_msg()
3306 struct irq_2_irte *irte_info = &data->irq_2_irte; in irq_remapping_prepare_irte()
3307 struct amd_iommu *iommu = data->iommu; in irq_remapping_prepare_irte()
3312 data->irq_2_irte.devid = devid; in irq_remapping_prepare_irte()
3313 data->irq_2_irte.index = index + sub_handle; in irq_remapping_prepare_irte()
3314 iommu->irte_ops->prepare(data->entry, apic->delivery_mode, in irq_remapping_prepare_irte()
3315 apic->dest_mode_logical, irq_cfg->vector, in irq_remapping_prepare_irte()
3316 irq_cfg->dest_apicid, devid); in irq_remapping_prepare_irte()
3318 switch (info->type) { in irq_remapping_prepare_irte()
3323 fill_msi_msg(&data->msi_entry, irte_info->index); in irq_remapping_prepare_irte()
3364 return -EINVAL; in irq_remapping_alloc()
3365 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI) in irq_remapping_alloc()
3366 return -EINVAL; in irq_remapping_alloc()
3370 return -EINVAL; in irq_remapping_alloc()
3376 return -EINVAL; in irq_remapping_alloc()
3382 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { in irq_remapping_alloc()
3387 if (!table->min_index) { in irq_remapping_alloc()
3392 table->min_index = 32; in irq_remapping_alloc()
3394 iommu->irte_ops->set_allocated(table, i); in irq_remapping_alloc()
3396 WARN_ON(table->min_index != 32); in irq_remapping_alloc()
3397 index = info->ioapic.pin; in irq_remapping_alloc()
3399 index = -ENOMEM; in irq_remapping_alloc()
3401 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI || in irq_remapping_alloc()
3402 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) { in irq_remapping_alloc()
3403 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI); in irq_remapping_alloc()
3406 msi_desc_to_pci_dev(info->desc)); in irq_remapping_alloc()
3421 ret = -EINVAL; in irq_remapping_alloc()
3425 ret = -ENOMEM; in irq_remapping_alloc()
3431 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); in irq_remapping_alloc()
3433 data->entry = kzalloc(sizeof(struct irte_ga), in irq_remapping_alloc()
3435 if (!data->entry) { in irq_remapping_alloc()
3440 data->iommu = iommu; in irq_remapping_alloc()
3441 irq_data->hwirq = (devid << 16) + i; in irq_remapping_alloc()
3442 irq_data->chip_data = data; in irq_remapping_alloc()
3443 irq_data->chip = &amd_ir_chip; in irq_remapping_alloc()
3451 for (i--; i >= 0; i--) { in irq_remapping_alloc()
3454 kfree(irq_data->chip_data); in irq_remapping_alloc()
3473 if (irq_data && irq_data->chip_data) { in irq_remapping_free()
3474 data = irq_data->chip_data; in irq_remapping_free()
3475 irte_info = &data->irq_2_irte; in irq_remapping_free()
3476 free_irte(data->iommu, irte_info->devid, irte_info->index); in irq_remapping_free()
3477 kfree(data->entry); in irq_remapping_free()
3492 struct amd_ir_data *data = irq_data->chip_data; in irq_remapping_activate()
3493 struct irq_2_irte *irte_info = &data->irq_2_irte; in irq_remapping_activate()
3494 struct amd_iommu *iommu = data->iommu; in irq_remapping_activate()
3500 iommu->irte_ops->activate(iommu, data->entry, irte_info->devid, in irq_remapping_activate()
3501 irte_info->index); in irq_remapping_activate()
3509 struct amd_ir_data *data = irq_data->chip_data; in irq_remapping_deactivate()
3510 struct irq_2_irte *irte_info = &data->irq_2_irte; in irq_remapping_deactivate()
3511 struct amd_iommu *iommu = data->iommu; in irq_remapping_deactivate()
3514 iommu->irte_ops->deactivate(iommu, data->entry, irte_info->devid, in irq_remapping_deactivate()
3515 irte_info->index); in irq_remapping_deactivate()
3522 int devid = -1; in irq_remapping_select()
3528 devid = get_ioapic_devid(fwspec->param[0]); in irq_remapping_select()
3530 devid = get_hpet_devid(fwspec->param[0]); in irq_remapping_select()
3536 return iommu && iommu->ir_domain == d; in irq_remapping_select()
3550 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; in amd_iommu_activate_guest_mode()
3556 valid = entry->lo.fields_vapic.valid; in amd_iommu_activate_guest_mode()
3558 entry->lo.val = 0; in amd_iommu_activate_guest_mode()
3559 entry->hi.val = 0; in amd_iommu_activate_guest_mode()
3561 entry->lo.fields_vapic.valid = valid; in amd_iommu_activate_guest_mode()
3562 entry->lo.fields_vapic.guest_mode = 1; in amd_iommu_activate_guest_mode()
3563 entry->lo.fields_vapic.ga_log_intr = 1; in amd_iommu_activate_guest_mode()
3564 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr; in amd_iommu_activate_guest_mode()
3565 entry->hi.fields.vector = ir_data->ga_vector; in amd_iommu_activate_guest_mode()
3566 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; in amd_iommu_activate_guest_mode()
3568 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, in amd_iommu_activate_guest_mode()
3569 ir_data->irq_2_irte.index, entry); in amd_iommu_activate_guest_mode()
3576 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; in amd_iommu_deactivate_guest_mode()
3577 struct irq_cfg *cfg = ir_data->cfg; in amd_iommu_deactivate_guest_mode()
3581 !entry || !entry->lo.fields_vapic.guest_mode) in amd_iommu_deactivate_guest_mode()
3584 valid = entry->lo.fields_remap.valid; in amd_iommu_deactivate_guest_mode()
3586 entry->lo.val = 0; in amd_iommu_deactivate_guest_mode()
3587 entry->hi.val = 0; in amd_iommu_deactivate_guest_mode()
3589 entry->lo.fields_remap.valid = valid; in amd_iommu_deactivate_guest_mode()
3590 entry->lo.fields_remap.dm = apic->dest_mode_logical; in amd_iommu_deactivate_guest_mode()
3591 entry->lo.fields_remap.int_type = apic->delivery_mode; in amd_iommu_deactivate_guest_mode()
3592 entry->hi.fields.vector = cfg->vector; in amd_iommu_deactivate_guest_mode()
3593 entry->lo.fields_remap.destination = in amd_iommu_deactivate_guest_mode()
3594 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); in amd_iommu_deactivate_guest_mode()
3595 entry->hi.fields.destination = in amd_iommu_deactivate_guest_mode()
3596 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); in amd_iommu_deactivate_guest_mode()
3598 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, in amd_iommu_deactivate_guest_mode()
3599 ir_data->irq_2_irte.index, entry); in amd_iommu_deactivate_guest_mode()
3607 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; in amd_ir_set_vcpu_affinity()
3608 struct amd_ir_data *ir_data = data->chip_data; in amd_ir_set_vcpu_affinity()
3609 struct irq_2_irte *irte_info = &ir_data->irq_2_irte; in amd_ir_set_vcpu_affinity()
3612 if (ir_data->iommu == NULL) in amd_ir_set_vcpu_affinity()
3613 return -EINVAL; in amd_ir_set_vcpu_affinity()
3615 dev_data = search_dev_data(ir_data->iommu, irte_info->devid); in amd_ir_set_vcpu_affinity()
3618 * This device has never been set up for guest mode. in amd_ir_set_vcpu_affinity()
3621 if (!dev_data || !dev_data->use_vapic) in amd_ir_set_vcpu_affinity()
3622 return -EINVAL; in amd_ir_set_vcpu_affinity()
3624 ir_data->cfg = irqd_cfg(data); in amd_ir_set_vcpu_affinity()
3625 pi_data->ir_data = ir_data; in amd_ir_set_vcpu_affinity()
3628 * SVM tries to set up for VAPIC mode, but we are in in amd_ir_set_vcpu_affinity()
3629 * legacy mode. So, we force legacy mode instead. in amd_ir_set_vcpu_affinity()
3634 pi_data->is_guest_mode = false; in amd_ir_set_vcpu_affinity()
3637 pi_data->prev_ga_tag = ir_data->cached_ga_tag; in amd_ir_set_vcpu_affinity()
3638 if (pi_data->is_guest_mode) { in amd_ir_set_vcpu_affinity()
3639 ir_data->ga_root_ptr = (pi_data->base >> 12); in amd_ir_set_vcpu_affinity()
3640 ir_data->ga_vector = vcpu_pi_info->vector; in amd_ir_set_vcpu_affinity()
3641 ir_data->ga_tag = pi_data->ga_tag; in amd_ir_set_vcpu_affinity()
3644 ir_data->cached_ga_tag = pi_data->ga_tag; in amd_ir_set_vcpu_affinity()
3653 ir_data->cached_ga_tag = 0; in amd_ir_set_vcpu_affinity()
3670 iommu->irte_ops->set_affinity(iommu, ir_data->entry, irte_info->devid, in amd_ir_update_irte()
3671 irte_info->index, cfg->vector, in amd_ir_update_irte()
3672 cfg->dest_apicid); in amd_ir_update_irte()
3678 struct amd_ir_data *ir_data = data->chip_data; in amd_ir_set_affinity()
3679 struct irq_2_irte *irte_info = &ir_data->irq_2_irte; in amd_ir_set_affinity()
3681 struct irq_data *parent = data->parent_data; in amd_ir_set_affinity()
3682 struct amd_iommu *iommu = ir_data->iommu; in amd_ir_set_affinity()
3686 return -ENODEV; in amd_ir_set_affinity()
3688 ret = parent->chip->irq_set_affinity(parent, mask, force); in amd_ir_set_affinity()
3705 struct amd_ir_data *ir_data = irq_data->chip_data; in ir_compose_msi_msg()
3707 *msg = ir_data->msi_entry; in ir_compose_msi_msg()
3711 .name = "AMD-IR",
3722 .prefix = "IR-",
3729 .prefix = "vIR-",
3737 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); in amd_iommu_create_irq_domain()
3739 return -ENOMEM; in amd_iommu_create_irq_domain()
3740 iommu->ir_domain = irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 0, 0, in amd_iommu_create_irq_domain()
3742 if (!iommu->ir_domain) { in amd_iommu_create_irq_domain()
3744 return -ENOMEM; in amd_iommu_create_irq_domain()
3747 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI); in amd_iommu_create_irq_domain()
3748 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT | in amd_iommu_create_irq_domain()
3752 iommu->ir_domain->msi_parent_ops = &virt_amdvi_msi_parent_ops; in amd_iommu_create_irq_domain()
3754 iommu->ir_domain->msi_parent_ops = &amdvi_msi_parent_ops; in amd_iommu_create_irq_domain()
3762 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; in amd_iommu_update_ga()
3765 !entry || !entry->lo.fields_vapic.guest_mode) in amd_iommu_update_ga()
3768 if (!ir_data->iommu) in amd_iommu_update_ga()
3769 return -ENODEV; in amd_iommu_update_ga()
3772 entry->lo.fields_vapic.destination = in amd_iommu_update_ga()
3774 entry->hi.fields.destination = in amd_iommu_update_ga()
3777 entry->lo.fields_vapic.is_run = is_run; in amd_iommu_update_ga()
3779 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, in amd_iommu_update_ga()
3780 ir_data->irq_2_irte.index, entry); in amd_iommu_update_ga()