Lines Matching +full:excitation +full:- +full:current +full:- +full:1 +full:- +full:nanoamp
1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
47 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0)
83 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1)
88 #define AD4130_FILTER_SELECT_MIN 1
125 #define AD4130_INVALID_SLOT -1
128 [AD4130_STATUS_REG] = 1,
133 [AD4130_ID_REG] = 1,
136 [AD4130_MCLK_COUNT_REG] = 1,
137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
144 [AD4130_FIFO_STATUS_REG] = 1,
221 AD4130_PIN_FN_DIFF = BIT(1),
312 u8 reg_read_tx_buf[1];
363 .samp_freq_avail_len = 1, \
370 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10),
372 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047),
373 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047),
397 return -EINVAL; in ad4130_get_reg_size()
431 st->reg_write_tx_buf[0] = reg; in ad4130_reg_write()
435 put_unaligned_be24(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
438 put_unaligned_be16(val, &st->reg_write_tx_buf[1]); in ad4130_reg_write()
440 case 1: in ad4130_reg_write()
441 st->reg_write_tx_buf[1] = val; in ad4130_reg_write()
444 return -EINVAL; in ad4130_reg_write()
447 return spi_write(st->spi, st->reg_write_tx_buf, size + 1); in ad4130_reg_write()
455 .tx_buf = st->reg_read_tx_buf, in ad4130_reg_read()
456 .len = sizeof(st->reg_read_tx_buf), in ad4130_reg_read()
459 .rx_buf = st->reg_read_rx_buf, in ad4130_reg_read()
469 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg; in ad4130_reg_read()
470 t[1].len = size; in ad4130_reg_read()
472 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); in ad4130_reg_read()
478 *val = get_unaligned_be24(st->reg_read_rx_buf); in ad4130_reg_read()
481 *val = get_unaligned_be16(st->reg_read_rx_buf); in ad4130_reg_read()
483 case 1: in ad4130_reg_read()
484 *val = st->reg_read_rx_buf[0]; in ad4130_reg_read()
487 return -EINVAL; in ad4130_reg_read()
506 * Output-only GPIO functionality is available on pins AIN2 through in ad4130_gpio_init_valid_mask()
511 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE; in ad4130_gpio_init_valid_mask()
531 regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, in ad4130_gpio_set()
537 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mode()
544 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_watermark_interrupt_en()
560 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_mode()
569 unsigned int transfer_len = st->effective_watermark * data_reg_size; in ad4130_push_fifo_data()
570 unsigned int set_size = st->num_enabled_channels * data_reg_size; in ad4130_push_fifo_data()
574 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark); in ad4130_push_fifo_data()
575 st->fifo_xfer[1].len = transfer_len; in ad4130_push_fifo_data()
577 ret = spi_sync(st->spi, &st->fifo_msg); in ad4130_push_fifo_data()
582 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]); in ad4130_push_fifo_data()
593 complete(&st->completion); in ad4130_irq_handler()
618 if (a->iout0_val != b->iout0_val || in ad4130_setup_info_eq()
619 a->iout1_val != b->iout1_val || in ad4130_setup_info_eq()
620 a->burnout != b->burnout || in ad4130_setup_info_eq()
621 a->pga != b->pga || in ad4130_setup_info_eq()
622 a->fs != b->fs || in ad4130_setup_info_eq()
623 a->ref_sel != b->ref_sel || in ad4130_setup_info_eq()
624 a->filter_mode != b->filter_mode || in ad4130_setup_info_eq()
625 a->ref_bufp != b->ref_bufp || in ad4130_setup_info_eq()
626 a->ref_bufm != b->ref_bufm) in ad4130_setup_info_eq()
642 struct ad4130_slot_info *slot_info = &st->slots_info[i]; in ad4130_find_slot()
645 if (ad4130_setup_info_eq(target_setup_info, &slot_info->setup)) { in ad4130_find_slot()
651 if (slot_info->enabled_channels) in ad4130_find_slot()
656 slot_info->channels < st->slots_info[*slot].channels) in ad4130_find_slot()
661 return -EINVAL; in ad4130_find_slot()
670 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_unlink_channel()
671 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot]; in ad4130_unlink_channel()
673 chan_info->slot = AD4130_INVALID_SLOT; in ad4130_unlink_channel()
674 slot_info->channels--; in ad4130_unlink_channel()
682 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_unlink_slot()
684 if (!chan_info->initialized || chan_info->slot != slot) in ad4130_unlink_slot()
696 struct ad4130_slot_info *slot_info = &st->slots_info[slot]; in ad4130_link_channel_slot()
697 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_link_channel_slot()
700 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_link_channel_slot()
706 chan_info->slot = slot; in ad4130_link_channel_slot()
707 slot_info->channels++; in ad4130_link_channel_slot()
719 val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) | in ad4130_write_slot_setup()
720 FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) | in ad4130_write_slot_setup()
721 FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) | in ad4130_write_slot_setup()
722 FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) | in ad4130_write_slot_setup()
723 FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) | in ad4130_write_slot_setup()
724 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | in ad4130_write_slot_setup()
725 FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga); in ad4130_write_slot_setup()
727 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val); in ad4130_write_slot_setup()
731 val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_mode) | in ad4130_write_slot_setup()
732 FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs); in ad4130_write_slot_setup()
734 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val); in ad4130_write_slot_setup()
738 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info)); in ad4130_write_slot_setup()
746 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_write_channel_setup()
747 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_write_channel_setup()
755 * 1. Enabled and linked channel with setup changes: in ad4130_write_channel_setup()
756 * - Find a slot. If not possible, return error. in ad4130_write_channel_setup()
757 * - Unlink channel from current slot. in ad4130_write_channel_setup()
758 * - If the slot has channels linked to it, unlink all channels, and in ad4130_write_channel_setup()
760 * - Link channel to new slot. in ad4130_write_channel_setup()
763 * - Find a slot. If not possible, return error. in ad4130_write_channel_setup()
764 * - If the slot has channels linked to it, unlink all channels, and in ad4130_write_channel_setup()
766 * - Link channel to the slot. in ad4130_write_channel_setup()
769 * - Unlink channel from current slot. in ad4130_write_channel_setup()
773 * - Do nothing. in ad4130_write_channel_setup()
777 if (on_enable && chan_info->slot != AD4130_INVALID_SLOT) in ad4130_write_channel_setup()
780 if (!on_enable && !chan_info->enabled) { in ad4130_write_channel_setup()
781 if (chan_info->slot != AD4130_INVALID_SLOT) in ad4130_write_channel_setup()
789 /* Cases 1 & 2 */ in ad4130_write_channel_setup()
794 if (chan_info->slot != AD4130_INVALID_SLOT) in ad4130_write_channel_setup()
795 /* Case 1 */ in ad4130_write_channel_setup()
814 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_enable()
818 if (chan_info->enabled == status) in ad4130_set_channel_enable()
827 slot_info = &st->slots_info[chan_info->slot]; in ad4130_set_channel_enable()
829 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), in ad4130_set_channel_enable()
835 slot_info->enabled_channels += status ? 1 : -1; in ad4130_set_channel_enable()
836 chan_info->enabled = status; in ad4130_set_channel_enable()
858 * Notice that FS = 1 actually means max ODR, and that ODR decreases by
861 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
862 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
863 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
864 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
869 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
870 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
871 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
883 dividend = filter_config->fs_max * filter_config->odr_div * in ad4130_freq_to_fs()
887 temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max - in ad4130_freq_to_fs()
892 else if (temp > filter_config->fs_max) in ad4130_freq_to_fs()
893 temp = filter_config->fs_max; in ad4130_freq_to_fs()
906 dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) * in ad4130_fs_to_freq()
908 divisor = filter_config->fs_max * filter_config->odr_div; in ad4130_fs_to_freq()
919 unsigned int channel = chan->scan_index; in ad4130_set_filter_mode()
920 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_filter_mode()
921 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_set_filter_mode()
927 mutex_lock(&st->lock); in ad4130_set_filter_mode()
928 if (setup_info->filter_mode == val) in ad4130_set_filter_mode()
931 old_fs = setup_info->fs; in ad4130_set_filter_mode()
932 old_filter_mode = setup_info->filter_mode; in ad4130_set_filter_mode()
936 * close as possible. To do this, convert the current FS into ODR in ad4130_set_filter_mode()
940 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs, in ad4130_set_filter_mode()
943 ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs); in ad4130_set_filter_mode()
945 setup_info->filter_mode = val; in ad4130_set_filter_mode()
949 setup_info->fs = old_fs; in ad4130_set_filter_mode()
950 setup_info->filter_mode = old_filter_mode; in ad4130_set_filter_mode()
954 mutex_unlock(&st->lock); in ad4130_set_filter_mode()
963 unsigned int channel = chan->scan_index; in ad4130_get_filter_mode()
964 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_get_filter_mode()
967 mutex_lock(&st->lock); in ad4130_get_filter_mode()
968 filter_mode = setup_info->filter_mode; in ad4130_get_filter_mode()
969 mutex_unlock(&st->lock); in ad4130_get_filter_mode()
990 .indexed = 1,
991 .differential = 1,
1008 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_pga()
1009 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_set_channel_pga()
1014 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && in ad4130_set_channel_pga()
1015 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) in ad4130_set_channel_pga()
1019 return -EINVAL; in ad4130_set_channel_pga()
1021 mutex_lock(&st->lock); in ad4130_set_channel_pga()
1022 if (pga == setup_info->pga) in ad4130_set_channel_pga()
1025 old_pga = setup_info->pga; in ad4130_set_channel_pga()
1026 setup_info->pga = pga; in ad4130_set_channel_pga()
1030 setup_info->pga = old_pga; in ad4130_set_channel_pga()
1033 mutex_unlock(&st->lock); in ad4130_set_channel_pga()
1041 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; in ad4130_set_channel_freq()
1042 struct ad4130_setup_info *setup_info = &chan_info->setup; in ad4130_set_channel_freq()
1046 mutex_lock(&st->lock); in ad4130_set_channel_freq()
1047 old_fs = setup_info->fs; in ad4130_set_channel_freq()
1049 ad4130_freq_to_fs(setup_info->filter_mode, val, val2, &fs); in ad4130_set_channel_freq()
1051 if (fs == setup_info->fs) in ad4130_set_channel_freq()
1054 setup_info->fs = fs; in ad4130_set_channel_freq()
1058 setup_info->fs = old_fs; in ad4130_set_channel_freq()
1061 mutex_unlock(&st->lock); in ad4130_set_channel_freq()
1076 reinit_completion(&st->completion); in _ad4130_read_sample()
1082 ret = wait_for_completion_timeout(&st->completion, in _ad4130_read_sample()
1085 return -ETIMEDOUT; in _ad4130_read_sample()
1091 ret = regmap_read(st->regmap, AD4130_DATA_REG, val); in _ad4130_read_sample()
1112 mutex_lock(&st->lock); in ad4130_read_sample()
1114 mutex_unlock(&st->lock); in ad4130_read_sample()
1126 unsigned int channel = chan->scan_index; in ad4130_read_raw()
1127 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_raw()
1133 mutex_lock(&st->lock); in ad4130_read_raw()
1134 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; in ad4130_read_raw()
1135 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; in ad4130_read_raw()
1136 mutex_unlock(&st->lock); in ad4130_read_raw()
1140 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0; in ad4130_read_raw()
1144 mutex_lock(&st->lock); in ad4130_read_raw()
1145 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs, in ad4130_read_raw()
1147 mutex_unlock(&st->lock); in ad4130_read_raw()
1151 return -EINVAL; in ad4130_read_raw()
1161 unsigned int channel = chan->scan_index; in ad4130_read_avail()
1162 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; in ad4130_read_avail()
1167 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; in ad4130_read_avail()
1168 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; in ad4130_read_avail()
1174 mutex_lock(&st->lock); in ad4130_read_avail()
1175 filter_config = &ad4130_filter_configs[setup_info->filter_mode]; in ad4130_read_avail()
1176 mutex_unlock(&st->lock); in ad4130_read_avail()
1178 *vals = (int *)filter_config->samp_freq_avail; in ad4130_read_avail()
1179 *length = filter_config->samp_freq_avail_len * 2; in ad4130_read_avail()
1182 return filter_config->samp_freq_avail_type; in ad4130_read_avail()
1184 return -EINVAL; in ad4130_read_avail()
1197 return -EINVAL; in ad4130_write_raw_get_fmt()
1206 unsigned int channel = chan->scan_index; in ad4130_write_raw()
1214 return -EINVAL; in ad4130_write_raw()
1224 return regmap_read(st->regmap, reg, readval); in ad4130_reg_access()
1226 return regmap_write(st->regmap, reg, writeval); in ad4130_reg_access()
1237 mutex_lock(&st->lock); in ad4130_update_scan_mode()
1239 for_each_set_bit(channel, scan_mask, indio_dev->num_channels) { in ad4130_update_scan_mode()
1247 st->num_enabled_channels = val; in ad4130_update_scan_mode()
1250 mutex_unlock(&st->lock); in ad4130_update_scan_mode()
1262 return -EINVAL; in ad4130_set_fifo_watermark()
1264 eff = val * st->num_enabled_channels; in ad4130_set_fifo_watermark()
1270 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels); in ad4130_set_fifo_watermark()
1272 mutex_lock(&st->lock); in ad4130_set_fifo_watermark()
1274 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_set_fifo_watermark()
1281 st->effective_watermark = eff; in ad4130_set_fifo_watermark()
1282 st->watermark = val; in ad4130_set_fifo_watermark()
1285 mutex_unlock(&st->lock); in ad4130_set_fifo_watermark()
1305 mutex_lock(&st->lock); in ad4130_buffer_postenable()
1311 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); in ad4130_buffer_postenable()
1322 mutex_unlock(&st->lock); in ad4130_buffer_postenable()
1333 mutex_lock(&st->lock); in ad4130_buffer_predisable()
1339 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger); in ad4130_buffer_predisable()
1355 for (i = 0; i < indio_dev->num_channels; i++) { in ad4130_buffer_predisable()
1362 mutex_unlock(&st->lock); in ad4130_buffer_predisable()
1378 mutex_lock(&st->lock); in hwfifo_watermark_show()
1379 val = st->watermark; in hwfifo_watermark_show()
1380 mutex_unlock(&st->lock); in hwfifo_watermark_show()
1392 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val); in hwfifo_enabled_show()
1405 return sysfs_emit(buf, "%s\n", "1"); in hwfifo_watermark_min_show()
1437 return -EINVAL; in _ad4130_find_table_index()
1448 return regulator_get_voltage(st->regulators[2].consumer); in ad4130_get_ref_voltage()
1450 return regulator_get_voltage(st->regulators[3].consumer); in ad4130_get_ref_voltage()
1452 return regulator_get_voltage(st->regulators[0].consumer); in ad4130_get_ref_voltage()
1454 return st->int_ref_uv; in ad4130_get_ref_voltage()
1456 return -EINVAL; in ad4130_get_ref_voltage()
1464 struct device *dev = &st->spi->dev; in ad4130_parse_fw_setup()
1469 fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp); in ad4130_parse_fw_setup()
1473 "Invalid excitation current %unA\n", tmp); in ad4130_parse_fw_setup()
1474 setup_info->iout0_val = ret; in ad4130_parse_fw_setup()
1477 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp); in ad4130_parse_fw_setup()
1481 "Invalid excitation current %unA\n", tmp); in ad4130_parse_fw_setup()
1482 setup_info->iout1_val = ret; in ad4130_parse_fw_setup()
1485 fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp); in ad4130_parse_fw_setup()
1489 "Invalid burnout current %unA\n", tmp); in ad4130_parse_fw_setup()
1490 setup_info->burnout = ret; in ad4130_parse_fw_setup()
1492 setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive"); in ad4130_parse_fw_setup()
1493 setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative"); in ad4130_parse_fw_setup()
1495 setup_info->ref_sel = AD4130_REF_REFIN1; in ad4130_parse_fw_setup()
1496 fwnode_property_read_u32(child, "adi,reference-select", in ad4130_parse_fw_setup()
1497 &setup_info->ref_sel); in ad4130_parse_fw_setup()
1498 if (setup_info->ref_sel >= AD4130_REF_SEL_MAX) in ad4130_parse_fw_setup()
1499 return dev_err_probe(dev, -EINVAL, in ad4130_parse_fw_setup()
1501 setup_info->ref_sel); in ad4130_parse_fw_setup()
1503 if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS) in ad4130_parse_fw_setup()
1504 st->int_ref_en = true; in ad4130_parse_fw_setup()
1506 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel); in ad4130_parse_fw_setup()
1509 setup_info->ref_sel); in ad4130_parse_fw_setup()
1516 struct device *dev = &st->spi->dev; in ad4130_validate_diff_channel()
1519 return dev_err_probe(dev, -EINVAL, in ad4130_validate_diff_channel()
1525 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_diff_channel()
1526 return dev_err_probe(dev, -EINVAL, in ad4130_validate_diff_channel()
1528 st->pins_fn[pin]); in ad4130_validate_diff_channel()
1530 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF; in ad4130_validate_diff_channel()
1552 struct device *dev = &st->spi->dev; in ad4130_validate_excitation_pin()
1555 return dev_err_probe(dev, -EINVAL, in ad4130_validate_excitation_pin()
1556 "Invalid excitation pin %u\n", pin); in ad4130_validate_excitation_pin()
1558 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_excitation_pin()
1559 return dev_err_probe(dev, -EINVAL, in ad4130_validate_excitation_pin()
1561 st->pins_fn[pin]); in ad4130_validate_excitation_pin()
1563 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION; in ad4130_validate_excitation_pin()
1570 struct device *dev = &st->spi->dev; in ad4130_validate_vbias_pin()
1573 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n", in ad4130_validate_vbias_pin()
1576 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) in ad4130_validate_vbias_pin()
1577 return dev_err_probe(dev, -EINVAL, in ad4130_validate_vbias_pin()
1579 st->pins_fn[pin]); in ad4130_validate_vbias_pin()
1581 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS; in ad4130_validate_vbias_pin()
1592 for (i = 0; i < st->num_vbias_pins; i++) { in ad4130_validate_vbias_pins()
1606 unsigned int index = indio_dev->num_channels++; in ad4130_parse_fw_channel()
1607 struct device *dev = &st->spi->dev; in ad4130_parse_fw_channel()
1614 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); in ad4130_parse_fw_channel()
1616 chan = &st->chans[index]; in ad4130_parse_fw_channel()
1617 chan_info = &st->chans_info[index]; in ad4130_parse_fw_channel()
1620 chan->scan_type.realbits = resolution; in ad4130_parse_fw_channel()
1621 chan->scan_type.storagebits = resolution; in ad4130_parse_fw_channel()
1622 chan->scan_index = index; in ad4130_parse_fw_channel()
1624 chan_info->slot = AD4130_INVALID_SLOT; in ad4130_parse_fw_channel()
1625 chan_info->setup.fs = AD4130_FILTER_SELECT_MIN; in ad4130_parse_fw_channel()
1626 chan_info->initialized = true; in ad4130_parse_fw_channel()
1628 ret = fwnode_property_read_u32_array(child, "diff-channels", pins, in ad4130_parse_fw_channel()
1637 chan->channel = pins[0]; in ad4130_parse_fw_channel()
1638 chan->channel2 = pins[1]; in ad4130_parse_fw_channel()
1640 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup); in ad4130_parse_fw_channel()
1644 fwnode_property_read_u32(child, "adi,excitation-pin-0", in ad4130_parse_fw_channel()
1645 &chan_info->iout0); in ad4130_parse_fw_channel()
1646 if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) { in ad4130_parse_fw_channel()
1647 ret = ad4130_validate_excitation_pin(st, chan_info->iout0); in ad4130_parse_fw_channel()
1652 fwnode_property_read_u32(child, "adi,excitation-pin-1", in ad4130_parse_fw_channel()
1653 &chan_info->iout1); in ad4130_parse_fw_channel()
1654 if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) { in ad4130_parse_fw_channel()
1655 ret = ad4130_validate_excitation_pin(st, chan_info->iout1); in ad4130_parse_fw_channel()
1666 struct device *dev = &st->spi->dev; in ad4130_parse_fw_children()
1670 indio_dev->channels = st->chans; in ad4130_parse_fw_children()
1686 struct device *dev = &st->spi->dev; in ad4310_parse_fw()
1693 st->mclk = devm_clk_get_optional(dev, "mclk"); in ad4310_parse_fw()
1694 if (IS_ERR(st->mclk)) in ad4310_parse_fw()
1695 return dev_err_probe(dev, PTR_ERR(st->mclk), in ad4310_parse_fw()
1698 st->int_pin_sel = AD4130_INT_PIN_INT; in ad4310_parse_fw()
1704 st->int_pin_sel = i; in ad4310_parse_fw()
1709 if (st->int_pin_sel == AD4130_INT_PIN_DOUT) in ad4310_parse_fw()
1710 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1713 if (st->int_pin_sel == AD4130_INT_PIN_P2) in ad4310_parse_fw()
1714 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL; in ad4310_parse_fw()
1716 device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq); in ad4310_parse_fw()
1719 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1723 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) in ad4310_parse_fw()
1724 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT; in ad4310_parse_fw()
1725 else if (st->mclk) in ad4310_parse_fw()
1726 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT; in ad4310_parse_fw()
1728 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4310_parse_fw()
1730 if (st->int_pin_sel == AD4130_INT_PIN_CLK && in ad4310_parse_fw()
1731 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4310_parse_fw()
1732 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1734 st->mclk_sel, st->int_pin_sel); in ad4310_parse_fw()
1736 st->int_ref_uv = AD4130_INT_REF_2_5V; in ad4310_parse_fw()
1743 avdd_uv = regulator_get_voltage(st->regulators[0].consumer); in ad4310_parse_fw()
1745 st->int_ref_uv = AD4130_INT_REF_1_25V; in ad4310_parse_fw()
1747 st->bipolar = device_property_read_bool(dev, "adi,bipolar"); in ad4310_parse_fw()
1749 ret = device_property_count_u32(dev, "adi,vbias-pins"); in ad4310_parse_fw()
1752 return dev_err_probe(dev, -EINVAL, in ad4310_parse_fw()
1755 st->num_vbias_pins = ret; in ad4310_parse_fw()
1757 ret = device_property_read_u32_array(dev, "adi,vbias-pins", in ad4310_parse_fw()
1758 st->vbias_pins, in ad4310_parse_fw()
1759 st->num_vbias_pins); in ad4310_parse_fw()
1764 ret = ad4130_validate_vbias_pins(st, st->vbias_pins, in ad4310_parse_fw()
1765 st->num_vbias_pins); in ad4310_parse_fw()
1779 unsigned int pow = ad4130_resolution(st) - st->bipolar; in ad4130_fill_scale_tbls()
1793 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI); in ad4130_fill_scale_tbls()
1805 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, in ad4130_set_mclk_sel()
1821 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_is_enabled()
1833 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT; in ad4130_int_clk_prepare()
1847 st->mclk_sel = AD4130_MCLK_76_8KHZ; in ad4130_int_clk_unprepare()
1864 struct device *dev = &st->spi->dev; in ad4130_setup_int_clk()
1871 if (st->int_pin_sel == AD4130_INT_PIN_CLK || in ad4130_setup_int_clk()
1872 st->mclk_sel != AD4130_MCLK_76_8KHZ) in ad4130_setup_int_clk()
1878 clk_name = of_node->name; in ad4130_setup_int_clk()
1879 of_property_read_string(of_node, "clock-output-names", &clk_name); in ad4130_setup_int_clk()
1884 st->int_clk_hw.init = &init; in ad4130_setup_int_clk()
1885 clk = devm_clk_register(dev, &st->int_clk_hw); in ad4130_setup_int_clk()
1899 struct device *dev = &st->spi->dev; in ad4130_setup()
1906 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT) in ad4130_setup()
1909 ret = clk_set_rate(st->mclk, rate); in ad4130_setup()
1913 ret = clk_prepare_enable(st->mclk); in ad4130_setup()
1918 st->mclk); in ad4130_setup()
1922 if (st->int_ref_uv == AD4130_INT_REF_2_5V) in ad4130_setup()
1927 /* Switch to SPI 4-wire mode. */ in ad4130_setup()
1928 val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1); in ad4130_setup()
1929 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar); in ad4130_setup()
1930 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en); in ad4130_setup()
1932 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel); in ad4130_setup()
1935 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val); in ad4130_setup()
1945 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE) in ad4130_setup()
1948 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); in ad4130_setup()
1950 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val); in ad4130_setup()
1955 for (i = 0; i < st->num_vbias_pins; i++) in ad4130_setup()
1956 val |= BIT(st->vbias_pins[i]); in ad4130_setup()
1958 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val); in ad4130_setup()
1962 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, in ad4130_setup()
1973 for (i = 0; i < indio_dev->num_channels; i++) { in ad4130_setup()
1974 struct ad4130_chan_info *chan_info = &st->chans_info[i]; in ad4130_setup()
1975 struct iio_chan_spec *chan = &st->chans[i]; in ad4130_setup()
1978 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) | in ad4130_setup()
1979 FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) | in ad4130_setup()
1980 FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) | in ad4130_setup()
1981 FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1); in ad4130_setup()
1983 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); in ad4130_setup()
1995 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf)); in ad4130_soft_reset()
2008 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_disable_regulators()
2013 struct device *dev = &spi->dev; in ad4130_probe()
2020 return -ENOMEM; in ad4130_probe()
2024 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); in ad4130_probe()
2025 init_completion(&st->completion); in ad4130_probe()
2026 mutex_init(&st->lock); in ad4130_probe()
2027 st->spi = spi; in ad4130_probe()
2034 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; in ad4130_probe()
2035 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf; in ad4130_probe()
2036 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf); in ad4130_probe()
2037 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf; in ad4130_probe()
2038 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, in ad4130_probe()
2039 ARRAY_SIZE(st->fifo_xfer)); in ad4130_probe()
2041 indio_dev->name = AD4130_NAME; in ad4130_probe()
2042 indio_dev->modes = INDIO_DIRECT_MODE; in ad4130_probe()
2043 indio_dev->info = &ad4130_info; in ad4130_probe()
2045 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); in ad4130_probe()
2046 if (IS_ERR(st->regmap)) in ad4130_probe()
2047 return PTR_ERR(st->regmap); in ad4130_probe()
2049 st->regulators[0].supply = "avdd"; in ad4130_probe()
2050 st->regulators[1].supply = "iovdd"; in ad4130_probe()
2051 st->regulators[2].supply = "refin1"; in ad4130_probe()
2052 st->regulators[3].supply = "refin2"; in ad4130_probe()
2054 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), in ad4130_probe()
2055 st->regulators); in ad4130_probe()
2059 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); in ad4130_probe()
2086 st->gc.owner = THIS_MODULE; in ad4130_probe()
2087 st->gc.label = AD4130_NAME; in ad4130_probe()
2088 st->gc.base = -1; in ad4130_probe()
2089 st->gc.ngpio = AD4130_MAX_GPIOS; in ad4130_probe()
2090 st->gc.parent = dev; in ad4130_probe()
2091 st->gc.can_sleep = true; in ad4130_probe()
2092 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask; in ad4130_probe()
2093 st->gc.get_direction = ad4130_gpio_get_direction; in ad4130_probe()
2094 st->gc.set = ad4130_gpio_set; in ad4130_probe()
2096 ret = devm_gpiochip_add_data(dev, &st->gc, st); in ad4130_probe()
2106 ret = devm_request_threaded_irq(dev, spi->irq, NULL, in ad4130_probe()
2108 indio_dev->name, indio_dev); in ad4130_probe()
2120 st->irq_trigger = irq_get_trigger_type(spi->irq); in ad4130_probe()
2121 if (st->irq_trigger & IRQF_TRIGGER_RISING) in ad4130_probe()
2122 st->inv_irq_trigger = IRQF_TRIGGER_FALLING; in ad4130_probe()
2123 else if (st->irq_trigger & IRQF_TRIGGER_FALLING) in ad4130_probe()
2124 st->inv_irq_trigger = IRQF_TRIGGER_RISING; in ad4130_probe()
2126 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", in ad4130_probe()
2127 st->irq_trigger); in ad4130_probe()