99 #define NPCM_I2CCTL1			0x06  macro
707 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_eob_int()
713 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_eob_int()
773 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_int_enable()
779 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_int_enable()
786 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_start()
789 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_start()
802 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_stop()
805 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_master_stop()
824 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_stall_after_start()
830 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_stall_after_start()
837 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_nack()
840 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_nack()
858 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_int_enable()
864 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_int_enable()
876 		i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_enable()
881 		iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_slave_enable()
917 	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_reset()
924 	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_reset()
1925 		       ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&  in npcm_i2c_int_master_handler()
2174 	val = ioread8(bus->reg + NPCM_I2CCTL1);  in npcm_i2c_init_module()
2176 	iowrite8(val, bus->reg + NPCM_I2CCTL1);  in npcm_i2c_init_module()