Lines Matching +full:ascend910 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
3 * HiSilicon I2C Controller Driver for Kunpeng SoC
12 #include <linux/i2c.h>
106 /* I2C bus configuration */
114 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
119 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
124 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
129 u32 int_err = ctlr->xfer_err, reg; in hisi_i2c_handle_errors()
132 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_handle_errors()
135 dev_err(ctlr->dev, "rx fifo error read\n"); in hisi_i2c_handle_errors()
138 dev_err(ctlr->dev, "rx fifo error write\n"); in hisi_i2c_handle_errors()
141 dev_err(ctlr->dev, "tx fifo error read\n"); in hisi_i2c_handle_errors()
144 dev_err(ctlr->dev, "tx fifo error write\n"); in hisi_i2c_handle_errors()
150 struct i2c_msg *msg = ctlr->msgs; in hisi_i2c_start_xfer()
153 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
155 if (msg->flags & I2C_M_TEN) in hisi_i2c_start_xfer()
157 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
159 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
161 reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr); in hisi_i2c_start_xfer()
162 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
164 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
166 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
168 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_start_xfer()
178 ctlr->msg_num = 0; in hisi_i2c_reset_xfer()
179 ctlr->xfer_err = 0; in hisi_i2c_reset_xfer()
180 ctlr->msg_tx_idx = 0; in hisi_i2c_reset_xfer()
181 ctlr->msg_rx_idx = 0; in hisi_i2c_reset_xfer()
182 ctlr->buf_tx_idx = 0; in hisi_i2c_reset_xfer()
183 ctlr->buf_rx_idx = 0; in hisi_i2c_reset_xfer()
187 * Initialize the transfer information and start the I2C bus transfer.
200 ctlr->completion = &done; in hisi_i2c_master_xfer()
201 ctlr->msg_num = num; in hisi_i2c_master_xfer()
202 ctlr->msgs = msgs; in hisi_i2c_master_xfer()
206 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) { in hisi_i2c_master_xfer()
208 synchronize_irq(ctlr->irq); in hisi_i2c_master_xfer()
209 i2c_recover_bus(&ctlr->adapter); in hisi_i2c_master_xfer()
210 dev_err(ctlr->dev, "bus transfer timeout\n"); in hisi_i2c_master_xfer()
211 ret = -EIO; in hisi_i2c_master_xfer()
214 if (ctlr->xfer_err) { in hisi_i2c_master_xfer()
216 ret = -EIO; in hisi_i2c_master_xfer()
220 ctlr->completion = NULL; in hisi_i2c_master_xfer()
240 while (ctlr->msg_rx_idx < ctlr->msg_num) { in hisi_i2c_read_rx_fifo()
241 cur_msg = ctlr->msgs + ctlr->msg_rx_idx; in hisi_i2c_read_rx_fifo()
243 if (!(cur_msg->flags & I2C_M_RD)) { in hisi_i2c_read_rx_fifo()
244 ctlr->msg_rx_idx++; in hisi_i2c_read_rx_fifo()
248 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()
250 ctlr->buf_rx_idx < cur_msg->len) { in hisi_i2c_read_rx_fifo()
251 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA); in hisi_i2c_read_rx_fifo()
252 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_read_rx_fifo()
255 if (ctlr->buf_rx_idx == cur_msg->len) { in hisi_i2c_read_rx_fifo()
256 ctlr->buf_rx_idx = 0; in hisi_i2c_read_rx_fifo()
257 ctlr->msg_rx_idx++; in hisi_i2c_read_rx_fifo()
274 while (ctlr->msg_tx_idx < ctlr->msg_num) { in hisi_i2c_xfer_msg()
275 cur_msg = ctlr->msgs + ctlr->msg_tx_idx; in hisi_i2c_xfer_msg()
276 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1); in hisi_i2c_xfer_msg()
279 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx) in hisi_i2c_xfer_msg()
282 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()
284 ctlr->buf_tx_idx < cur_msg->len && max_write) { in hisi_i2c_xfer_msg()
293 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg) in hisi_i2c_xfer_msg()
296 if (cur_msg->flags & I2C_M_RD) in hisi_i2c_xfer_msg()
300 cur_msg->buf[ctlr->buf_tx_idx]); in hisi_i2c_xfer_msg()
302 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA); in hisi_i2c_xfer_msg()
303 ctlr->buf_tx_idx++; in hisi_i2c_xfer_msg()
304 max_write--; in hisi_i2c_xfer_msg()
306 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_xfer_msg()
310 if (ctlr->buf_tx_idx == cur_msg->len) { in hisi_i2c_xfer_msg()
311 ctlr->buf_tx_idx = 0; in hisi_i2c_xfer_msg()
312 ctlr->msg_tx_idx++; in hisi_i2c_xfer_msg()
324 if (ctlr->msg_tx_idx == ctlr->msg_num) in hisi_i2c_xfer_msg()
334 * Don't handle the interrupt if cltr->completion is NULL. We may in hisi_i2c_irq()
338 if (!ctlr->completion) in hisi_i2c_irq()
341 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT); in hisi_i2c_irq()
350 ctlr->xfer_err = int_stat; in hisi_i2c_irq()
366 complete(ctlr->completion); in hisi_i2c_irq()
386 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); in hisi_i2c_set_scl()
390 t_scl_lcnt = total_cnt - t_scl_hcnt; in hisi_i2c_set_scl()
392 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
394 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
397 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt; in hisi_i2c_set_scl()
398 scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt; in hisi_i2c_set_scl()
400 writel(scl_hcnt, ctlr->iobase + reg_hcnt); in hisi_i2c_set_scl()
401 writel(scl_lcnt, ctlr->iobase + reg_lcnt); in hisi_i2c_set_scl()
408 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true); in hisi_i2c_configure_bus()
409 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
411 switch (ctlr->t.bus_freq_hz) { in hisi_i2c_configure_bus()
425 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; in hisi_i2c_configure_bus()
430 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_configure_bus()
433 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_configure_bus()
435 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
438 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD); in hisi_i2c_configure_bus()
440 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN); in hisi_i2c_configure_bus()
444 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); in hisi_i2c_configure_bus()
450 struct device *dev = &pdev->dev; in hisi_i2c_probe()
458 return -ENOMEM; in hisi_i2c_probe()
460 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0); in hisi_i2c_probe()
461 if (IS_ERR(ctlr->iobase)) in hisi_i2c_probe()
462 return PTR_ERR(ctlr->iobase); in hisi_i2c_probe()
464 ctlr->irq = platform_get_irq(pdev, 0); in hisi_i2c_probe()
465 if (ctlr->irq < 0) in hisi_i2c_probe()
466 return ctlr->irq; in hisi_i2c_probe()
468 ctlr->dev = dev; in hisi_i2c_probe()
472 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr); in hisi_i2c_probe()
476 ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in hisi_i2c_probe()
477 if (IS_ERR_OR_NULL(ctlr->clk)) { in hisi_i2c_probe()
482 clk_rate_hz = clk_get_rate(ctlr->clk); in hisi_i2c_probe()
485 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); in hisi_i2c_probe()
489 adapter = &ctlr->adapter; in hisi_i2c_probe()
490 snprintf(adapter->name, sizeof(adapter->name), in hisi_i2c_probe()
491 "HiSilicon I2C Controller %s", dev_name(dev)); in hisi_i2c_probe()
492 adapter->owner = THIS_MODULE; in hisi_i2c_probe()
493 adapter->algo = &hisi_i2c_algo; in hisi_i2c_probe()
494 adapter->dev.parent = dev; in hisi_i2c_probe()
501 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION); in hisi_i2c_probe()
502 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n", in hisi_i2c_probe()
503 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version); in hisi_i2c_probe()
515 { .compatible = "hisilicon,ascend910-i2c", },
523 .name = "hisi-i2c",
531 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver");