Lines Matching +full:itu +full:- +full:r
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/dma-mapping.h>
14 #include <linux/media-bus-format.h>
79 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
82 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
155 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
158 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
244 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
247 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
292 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
295 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
362 iowrite32(val, dispc->base_common + reg); in dispc_write()
367 return ioread32(dispc->base_common + reg); in dispc_read()
373 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
380 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
388 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
395 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
403 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
410 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
422 return ((1 << (start - end + 1)) - 1) << end; in FLD_MASK()
731 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
737 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
743 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
758 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
761 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
774 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
777 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
795 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
803 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
823 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
838 switch (dispc->feat->subrev) { in dispc_set_irqenable()
895 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
896 tstate->bus_flags); in dispc_vp_bus_check()
898 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
899 __func__, tstate->bus_format); in dispc_vp_bus_check()
900 return -EINVAL; in dispc_vp_bus_check()
903 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
904 fmt->is_oldi_fmt) { in dispc_vp_bus_check()
905 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
906 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
907 return -EINVAL; in dispc_vp_bus_check()
917 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
920 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
922 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
924 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
926 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
928 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
970 if (fmt->data_width == 24) in dispc_enable_oldi()
972 else if (fmt->data_width != 18) in dispc_enable_oldi()
973 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
974 __func__, fmt->data_width); in dispc_enable_oldi()
978 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); in dispc_enable_oldi()
991 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
1001 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
1002 tstate->bus_flags); in dispc_vp_prepare()
1007 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
1017 const struct drm_display_mode *mode = &state->adjusted_mode; in dispc_vp_enable()
1023 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
1024 tstate->bus_flags); in dispc_vp_enable()
1029 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
1031 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_enable()
1032 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_enable()
1033 hbp = mode->htotal - mode->hsync_end; in dispc_vp_enable()
1035 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_enable()
1036 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_enable()
1037 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_enable()
1040 FLD_VAL(hsw - 1, 7, 0) | in dispc_vp_enable()
1041 FLD_VAL(hfp - 1, 19, 8) | in dispc_vp_enable()
1042 FLD_VAL(hbp - 1, 31, 20)); in dispc_vp_enable()
1045 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
1049 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); in dispc_vp_enable()
1051 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); in dispc_vp_enable()
1053 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); in dispc_vp_enable()
1055 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); in dispc_vp_enable()
1060 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); in dispc_vp_enable()
1066 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1079 FLD_VAL(mode->hdisplay - 1, 11, 0) | in dispc_vp_enable()
1080 FLD_VAL(mode->vdisplay - 1, 27, 16)); in dispc_vp_enable()
1092 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1136 u8 a, r, g, b; in argb8888_to_argb12121212() local
1140 r = (argb8888 >> 16) & 0xff; in argb8888_to_argb12121212()
1144 v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) | in argb8888_to_argb12121212()
1171 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1173 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1178 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1181 if (mode->clock > max_pclk) in dispc_vp_mode_valid()
1184 if (mode->hdisplay > 4096) in dispc_vp_mode_valid()
1187 if (mode->vdisplay > 4096) in dispc_vp_mode_valid()
1191 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dispc_vp_mode_valid()
1197 * - YUV output selected (BT656, BT1120) in dispc_vp_mode_valid()
1198 * - Dithering enabled in dispc_vp_mode_valid()
1199 * - TDM with TDMCycleFormat == 3 in dispc_vp_mode_valid()
1202 if ((mode->hdisplay % 2) != 0) in dispc_vp_mode_valid()
1205 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_mode_valid()
1206 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_mode_valid()
1207 hbp = mode->htotal - mode->hsync_end; in dispc_vp_mode_valid()
1209 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_mode_valid()
1210 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_mode_valid()
1211 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_mode_valid()
1222 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1226 bandwidth = 1000 * mode->clock; in dispc_vp_mode_valid()
1227 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; in dispc_vp_mode_valid()
1228 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); in dispc_vp_mode_valid()
1230 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1239 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1242 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1250 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1260 int r = rate / 100, rr = real_rate / 100; in dispc_pclk_diff() local
1262 return (unsigned int)(abs(((rr - r) * 100) / r)); in dispc_pclk_diff()
1268 int r; in dispc_vp_set_clk_rate() local
1271 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1272 if (r) { in dispc_vp_set_clk_rate()
1273 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1275 return r; in dispc_vp_set_clk_rate()
1278 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1281 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1285 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1286 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1328 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1351 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1392 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1393 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1394 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1402 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1403 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1404 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
1405 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); in dispc_csc_yuv2rgb_regval()
1406 regval[4] = CVAL(csc->m[CSC_BCB], 0); in dispc_csc_yuv2rgb_regval()
1414 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); in dispc_csc_rgb2yuv_regval()
1415 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); in dispc_csc_rgb2yuv_regval()
1416 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); in dispc_csc_rgb2yuv_regval()
1417 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); in dispc_csc_rgb2yuv_regval()
1418 regval[4] = CVAL(csc->m[CSC_CBB], 0); in dispc_csc_rgb2yuv_regval()
1426 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); in dispc_csc_cpr_regval()
1427 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); in dispc_csc_cpr_regval()
1428 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); in dispc_csc_cpr_regval()
1429 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); in dispc_csc_cpr_regval()
1430 regval[4] = CVAL(csc->m[CSC_BB], 0); in dispc_csc_cpr_regval()
1449 csc->to_regval(csc, regval); in dispc_k2g_vid_write_csc()
1452 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1453 __func__, csc->name); in dispc_k2g_vid_write_csc()
1472 csc->to_regval(csc, regval); in dispc_k3_vid_write_csc()
1479 /* YUV -> RGB, ITU-R BT.601, full range */
1483 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1485 { 0, -2048, -2048, }, /* full range */
1491 /* YUV -> RGB, ITU-R BT.601, limited range */
1495 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1497 { -256, -2048, -2048, }, /* limited range */
1503 /* YUV -> RGB, ITU-R BT.709, full range */
1507 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1509 { 0, -2048, -2048, }, /* full range */
1515 /* YUV -> RGB, ITU-R BT.709, limited range */
1519 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1521 { -256, -2048, -2048, }, /* limited range */
1562 coef = dispc_find_csc(state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1564 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1565 __func__, state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1569 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1619 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1625 u16 c0 = coefs->c0[phase]; in dispc_vid_write_fir_coefs()
1635 c1 = coefs->c1[phase]; in dispc_vid_write_fir_coefs()
1636 c2 = coefs->c2[phase]; in dispc_vid_write_fir_coefs()
1669 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1670 u32 fourcc = state->fb->format->format; in dispc_vid_calc_scaling()
1671 u32 in_width_max_5tap = f->in_width_max_5tap_rgb; in dispc_vid_calc_scaling()
1672 u32 in_width_max_3tap = f->in_width_max_3tap_rgb; in dispc_vid_calc_scaling()
1677 sp->xinc = 1; in dispc_vid_calc_scaling()
1678 sp->yinc = 1; in dispc_vid_calc_scaling()
1679 sp->in_w = state->src_w >> 16; in dispc_vid_calc_scaling()
1680 sp->in_w_uv = sp->in_w; in dispc_vid_calc_scaling()
1681 sp->in_h = state->src_h >> 16; in dispc_vid_calc_scaling()
1682 sp->in_h_uv = sp->in_h; in dispc_vid_calc_scaling()
1684 sp->scale_x = sp->in_w != state->crtc_w; in dispc_vid_calc_scaling()
1685 sp->scale_y = sp->in_h != state->crtc_h; in dispc_vid_calc_scaling()
1688 in_width_max_5tap = f->in_width_max_5tap_yuv; in dispc_vid_calc_scaling()
1689 in_width_max_3tap = f->in_width_max_3tap_yuv; in dispc_vid_calc_scaling()
1691 sp->in_w_uv >>= 1; in dispc_vid_calc_scaling()
1692 sp->scale_x = true; in dispc_vid_calc_scaling()
1695 sp->in_h_uv >>= 1; in dispc_vid_calc_scaling()
1696 sp->scale_y = true; in dispc_vid_calc_scaling()
1701 if ((!sp->scale_x && !sp->scale_y) || lite_plane) in dispc_vid_calc_scaling()
1704 if (sp->in_w > in_width_max_5tap) { in dispc_vid_calc_scaling()
1705 sp->five_taps = false; in dispc_vid_calc_scaling()
1707 downscale_limit = f->downscale_limit_3tap; in dispc_vid_calc_scaling()
1709 sp->five_taps = true; in dispc_vid_calc_scaling()
1711 downscale_limit = f->downscale_limit_5tap; in dispc_vid_calc_scaling()
1714 if (sp->scale_x) { in dispc_vid_calc_scaling()
1715 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1717 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1718 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1719 "%s: X-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1720 __func__, state->crtc_w, state->src_w >> 16, in dispc_vid_calc_scaling()
1721 f->upscale_limit); in dispc_vid_calc_scaling()
1722 return -EINVAL; in dispc_vid_calc_scaling()
1725 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1726 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, in dispc_vid_calc_scaling()
1727 state->crtc_w), in dispc_vid_calc_scaling()
1730 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1731 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1732 "%s: X-scaling factor %u/%u < 1/%u\n", in dispc_vid_calc_scaling()
1733 __func__, state->crtc_w, in dispc_vid_calc_scaling()
1734 state->src_w >> 16, in dispc_vid_calc_scaling()
1735 downscale_limit * f->xinc_max); in dispc_vid_calc_scaling()
1736 return -EINVAL; in dispc_vid_calc_scaling()
1739 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1742 while (sp->in_w > in_width_max) { in dispc_vid_calc_scaling()
1743 sp->xinc++; in dispc_vid_calc_scaling()
1744 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1747 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1748 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1750 state->src_w >> 16, in_width_max * f->xinc_max); in dispc_vid_calc_scaling()
1751 return -EINVAL; in dispc_vid_calc_scaling()
1760 sp->in_w &= ~1; in dispc_vid_calc_scaling()
1762 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1765 if (sp->scale_y) { in dispc_vid_calc_scaling()
1766 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); in dispc_vid_calc_scaling()
1768 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1769 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1770 "%s: Y-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1771 __func__, state->crtc_h, state->src_h >> 16, in dispc_vid_calc_scaling()
1772 f->upscale_limit); in dispc_vid_calc_scaling()
1773 return -EINVAL; in dispc_vid_calc_scaling()
1776 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1777 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, in dispc_vid_calc_scaling()
1778 state->crtc_h), in dispc_vid_calc_scaling()
1781 sp->in_h /= sp->yinc; in dispc_vid_calc_scaling()
1782 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, in dispc_vid_calc_scaling()
1783 state->crtc_h); in dispc_vid_calc_scaling()
1787 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1788 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", in dispc_vid_calc_scaling()
1789 __func__, state->src_w >> 16, state->src_h >> 16, in dispc_vid_calc_scaling()
1790 sp->xinc, sp->yinc, sp->in_w, sp->in_h, in dispc_vid_calc_scaling()
1791 sp->fir_xinc / 0x200000u, in dispc_vid_calc_scaling()
1792 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1793 sp->fir_yinc / 0x200000u, in dispc_vid_calc_scaling()
1794 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1795 sp->five_taps ? 5 : 3, in dispc_vid_calc_scaling()
1796 state->crtc_w, state->crtc_h); in dispc_vid_calc_scaling()
1799 if (sp->scale_x) { in dispc_vid_calc_scaling()
1800 sp->in_w_uv /= sp->xinc; in dispc_vid_calc_scaling()
1801 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, in dispc_vid_calc_scaling()
1802 state->crtc_w); in dispc_vid_calc_scaling()
1803 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1804 sp->fir_xinc_uv, in dispc_vid_calc_scaling()
1807 if (sp->scale_y) { in dispc_vid_calc_scaling()
1808 sp->in_h_uv /= sp->yinc; in dispc_vid_calc_scaling()
1809 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, in dispc_vid_calc_scaling()
1810 state->crtc_h); in dispc_vid_calc_scaling()
1811 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1812 sp->fir_yinc_uv, in dispc_vid_calc_scaling()
1813 sp->five_taps); in dispc_vid_calc_scaling()
1817 if (sp->scale_x) in dispc_vid_calc_scaling()
1818 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1821 if (sp->scale_y) in dispc_vid_calc_scaling()
1822 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1823 sp->five_taps); in dispc_vid_calc_scaling()
1835 sp->scale_x, 7, 7); in dispc_vid_set_scaling()
1839 sp->scale_y, 8, 8); in dispc_vid_set_scaling()
1842 if (!sp->scale_x && !sp->scale_y) in dispc_vid_set_scaling()
1845 /* VERTICAL 5-TAPS */ in dispc_vid_set_scaling()
1847 sp->five_taps, 21, 21); in dispc_vid_set_scaling()
1850 if (sp->scale_x) { in dispc_vid_set_scaling()
1852 sp->fir_xinc_uv); in dispc_vid_set_scaling()
1855 sp->xcoef_uv); in dispc_vid_set_scaling()
1857 if (sp->scale_y) { in dispc_vid_set_scaling()
1859 sp->fir_yinc_uv); in dispc_vid_set_scaling()
1862 sp->ycoef_uv); in dispc_vid_set_scaling()
1866 if (sp->scale_x) { in dispc_vid_set_scaling()
1867 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1870 sp->xcoef); in dispc_vid_set_scaling()
1873 if (sp->scale_y) { in dispc_vid_set_scaling()
1874 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1876 DISPC_VID_FIR_COEF_VERT, sp->ycoef); in dispc_vid_set_scaling()
1947 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
1949 *len = dispc->num_fourccs; in dispc_plane_formats()
1951 return dispc->fourccs; in dispc_plane_formats()
1959 return 1 + (pixels - 1) * ps; in pixinc()
1961 return 1 - (-pixels + 1) * ps; in pixinc()
1971 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1972 u32 fourcc = state->fb->format->format; in dispc_plane_check()
1973 bool need_scaling = state->src_w >> 16 != state->crtc_w || in dispc_plane_check()
1974 state->src_h >> 16 != state->crtc_h; in dispc_plane_check()
1979 if (!dispc_find_csc(state->color_encoding, in dispc_plane_check()
1980 state->color_range)) { in dispc_plane_check()
1981 dev_dbg(dispc->dev, in dispc_plane_check()
1983 __func__, state->color_encoding, in dispc_plane_check()
1984 state->color_range, hw_plane); in dispc_plane_check()
1985 return -EINVAL; in dispc_plane_check()
1991 dev_dbg(dispc->dev, in dispc_plane_check()
1994 state->src_w >> 16, state->src_h >> 16, in dispc_plane_check()
1995 state->crtc_w, state->crtc_h); in dispc_plane_check()
1996 return -EINVAL; in dispc_plane_check()
2009 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_dma_addr()
2011 u32 x = state->src_x >> 16; in dispc_plane_state_dma_addr()
2012 u32 y = state->src_y >> 16; in dispc_plane_state_dma_addr()
2014 gem = drm_fb_dma_get_gem_obj(state->fb, 0); in dispc_plane_state_dma_addr()
2016 return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] + in dispc_plane_state_dma_addr()
2017 y * fb->pitches[0]; in dispc_plane_state_dma_addr()
2023 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_p_uv_addr()
2025 u32 x = state->src_x >> 16; in dispc_plane_state_p_uv_addr()
2026 u32 y = state->src_y >> 16; in dispc_plane_state_p_uv_addr()
2028 if (WARN_ON(state->fb->format->num_planes != 2)) in dispc_plane_state_p_uv_addr()
2033 return gem->dma_addr + fb->offsets[1] + in dispc_plane_state_p_uv_addr()
2034 (x * fb->format->cpp[1] / fb->format->hsub) + in dispc_plane_state_p_uv_addr()
2035 (y * fb->pitches[1] / fb->format->vsub); in dispc_plane_state_p_uv_addr()
2042 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
2043 u32 fourcc = state->fb->format->format; in dispc_plane_setup()
2044 u16 cpp = state->fb->format->cpp[0]; in dispc_plane_setup()
2045 u32 fb_width = state->fb->pitches[0] / cpp; in dispc_plane_setup()
2059 (scale.in_w - 1) | ((scale.in_h - 1) << 16)); in dispc_plane_setup()
2070 pixinc(1 + (scale.yinc * fb_width - in dispc_plane_setup()
2074 if (state->fb->format->num_planes == 2) { in dispc_plane_setup()
2075 u16 cpp_uv = state->fb->format->cpp[1]; in dispc_plane_setup()
2076 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; in dispc_plane_setup()
2089 pixinc(1 + (scale.yinc * fb_width_uv - in dispc_plane_setup()
2096 (state->crtc_w - 1) | in dispc_plane_setup()
2097 ((state->crtc_h - 1) << 16)); in dispc_plane_setup()
2102 /* enable YUV->RGB color conversion */ in dispc_plane_setup()
2111 0xFF & (state->alpha >> 8)); in dispc_plane_setup()
2113 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) in dispc_plane_setup()
2149 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2156 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2162 thr_high = size - 1; in dispc_k2g_plane_init()
2170 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2172 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2186 * Prefetch up to fifo high-threshold value to minimize the in dispc_k2g_plane_init()
2201 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2211 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2217 thr_high = size - 1; in dispc_k3_plane_init()
2225 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2227 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2248 switch (dispc->feat->subrev) { in dispc_plane_init()
2266 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2268 /* Enable the gamma Shadow bit-field for all VPs*/ in dispc_vp_init()
2269 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2279 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2290 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2291 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2294 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2296 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2312 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2313 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2316 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2318 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2333 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2334 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2337 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2339 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2355 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2382 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2383 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2387 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2390 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2400 for (i = 0; i < length - 1; ++i) { in dispc_vp_set_gamma()
2401 unsigned int first = i * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2402 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2403 unsigned int w = last - first; in dispc_vp_set_gamma()
2404 u16 r, g, b; in dispc_vp_set_gamma() local
2411 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; in dispc_vp_set_gamma()
2412 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; in dispc_vp_set_gamma()
2413 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; in dispc_vp_set_gamma()
2415 r >>= 16 - hwbits; in dispc_vp_set_gamma()
2416 g >>= 16 - hwbits; in dispc_vp_set_gamma()
2417 b >>= 16 - hwbits; in dispc_vp_set_gamma()
2419 table[first + j] = (r << (hwbits * 2)) | in dispc_vp_set_gamma()
2434 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); in dispc_S31_32_to_s2_8()
2446 cpr->to_regval = dispc_csc_cpr_regval; in dispc_k2g_cpr_from_ctm()
2447 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); in dispc_k2g_cpr_from_ctm()
2448 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); in dispc_k2g_cpr_from_ctm()
2449 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); in dispc_k2g_cpr_from_ctm()
2450 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); in dispc_k2g_cpr_from_ctm()
2451 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); in dispc_k2g_cpr_from_ctm()
2452 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); in dispc_k2g_cpr_from_ctm()
2453 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); in dispc_k2g_cpr_from_ctm()
2454 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); in dispc_k2g_cpr_from_ctm()
2455 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); in dispc_k2g_cpr_from_ctm()
2464 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); in dispc_k2g_vp_csc_cpr_regval()
2465 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); in dispc_k2g_vp_csc_cpr_regval()
2466 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); in dispc_k2g_vp_csc_cpr_regval()
2512 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); in dispc_S31_32_to_s3_8()
2524 cpr->to_regval = dispc_csc_cpr_regval; in dispc_csc_from_ctm()
2525 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); in dispc_csc_from_ctm()
2526 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); in dispc_csc_from_ctm()
2527 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); in dispc_csc_from_ctm()
2528 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); in dispc_csc_from_ctm()
2529 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); in dispc_csc_from_ctm()
2530 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); in dispc_csc_from_ctm()
2531 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); in dispc_csc_from_ctm()
2532 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); in dispc_csc_from_ctm()
2533 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); in dispc_csc_from_ctm()
2547 csc->to_regval(csc, regval); in dispc_k3_vp_write_csc()
2580 if (!(state->color_mgmt_changed || newmodeset)) in dispc_vp_set_color_mgmt()
2583 if (state->gamma_lut) { in dispc_vp_set_color_mgmt()
2584 lut = (struct drm_color_lut *)state->gamma_lut->data; in dispc_vp_set_color_mgmt()
2585 length = state->gamma_lut->length / sizeof(*lut); in dispc_vp_set_color_mgmt()
2590 if (state->ctm) in dispc_vp_set_color_mgmt()
2591 ctm = (struct drm_color_ctm *)state->ctm->data; in dispc_vp_set_color_mgmt()
2593 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2608 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2610 dispc->is_enabled = false; in dispc_runtime_suspend()
2612 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2619 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2621 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2624 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2626 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2629 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2634 if (dispc->feat->subrev == DISPC_AM625 || in dispc_runtime_resume()
2635 dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2636 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2641 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2646 dispc->is_enabled = true; in dispc_runtime_resume()
2648 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2655 dev_dbg(tidss->dev, "%s\n", __func__); in dispc_remove()
2657 tidss->dispc = NULL; in dispc_remove()
2667 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); in dispc_iomap_resource()
2679 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2680 syscon_regmap_lookup_by_phandle(dev->of_node, in dispc_init_am65x_oldi_io_ctrl()
2681 "ti,am65x-oldi-io-ctrl"); in dispc_init_am65x_oldi_io_ctrl()
2682 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2683 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2684 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2686 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2687 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2700 dispc->errata.i2000 = true; in dispc_init_errata()
2701 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2711 if (dispc->feat->subrev == DISPC_K2G) in dispc_softreset()
2717 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, in dispc_softreset()
2720 dev_err(dispc->dev, "failed to reset dispc\n"); in dispc_softreset()
2729 struct device *dev = dispc->dev; in dispc_init_hw()
2738 ret = clk_prepare_enable(dispc->fclk); in dispc_init_hw()
2748 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2758 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2772 struct device *dev = tidss->dev; in dispc_init()
2777 int r = 0; in dispc_init() local
2781 feat = tidss->feat; in dispc_init()
2783 if (feat->subrev != DISPC_K2G) { in dispc_init()
2784 r = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); in dispc_init()
2785 if (r) in dispc_init()
2786 dev_warn(dev, "cannot set DMA masks to 48-bit\n"); in dispc_init()
2793 return -ENOMEM; in dispc_init()
2795 dispc->tidss = tidss; in dispc_init()
2796 dispc->dev = dev; in dispc_init()
2797 dispc->feat = feat; in dispc_init()
2801 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2802 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2803 if (!dispc->fourccs) in dispc_init()
2804 return -ENOMEM; in dispc_init()
2808 if (dispc->errata.i2000 && in dispc_init()
2812 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2815 dispc->num_fourccs = num_fourccs; in dispc_init()
2817 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2819 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2820 &dispc->base_common); in dispc_init()
2821 if (r) in dispc_init()
2822 return r; in dispc_init()
2824 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2825 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2826 &dispc->base_vid[i]); in dispc_init()
2827 if (r) in dispc_init()
2828 return r; in dispc_init()
2831 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2832 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2836 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2837 &dispc->base_ovr[i]); in dispc_init()
2838 if (r) in dispc_init()
2839 return r; in dispc_init()
2841 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2842 &dispc->base_vp[i]); in dispc_init()
2843 if (r) in dispc_init()
2844 return r; in dispc_init()
2846 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2849 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2852 dispc->vp_clk[i] = clk; in dispc_init()
2858 return -ENOMEM; in dispc_init()
2859 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2862 if (feat->subrev == DISPC_AM65X) { in dispc_init()
2863 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); in dispc_init()
2864 if (r) in dispc_init()
2865 return r; in dispc_init()
2868 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2869 if (IS_ERR(dispc->fclk)) { in dispc_init()
2871 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2872 return PTR_ERR(dispc->fclk); in dispc_init()
2874 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2876 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2877 &dispc->memory_bandwidth_limit); in dispc_init()
2879 r = dispc_init_hw(dispc); in dispc_init()
2880 if (r) in dispc_init()
2881 return r; in dispc_init()
2883 tidss->dispc = dispc; in dispc_init()