7463 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
7468 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
7479 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);  in si_vce_send_vcepll_ctlreq()
7495 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()
7500 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,  in si_set_vce_clocks()
7505 		WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,  in si_set_vce_clocks()
7517 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);  in si_set_vce_clocks()
7520 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,  in si_set_vce_clocks()
7524 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,  in si_set_vce_clocks()
7526 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);  in si_set_vce_clocks()
7529 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
7538 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
7541 	WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in si_set_vce_clocks()
7544 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);  in si_set_vce_clocks()
7547 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);  in si_set_vce_clocks()
7550 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()
7558 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);  in si_set_vce_clocks()
7563 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);  in si_set_vce_clocks()
7570 	WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,  in si_set_vce_clocks()