Lines Matching +full:wo +full:- +full:data
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
54 #define GPU_PWR_KEY 0x50 /* (WO) Power manager key register */
115 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
116 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
118 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
119 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
121 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
122 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
128 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
129 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
131 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
132 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
134 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
135 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
281 (deprecated - only for use with T60x) */
296 #define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */
329 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) argument
330 #define gpu_read(dev, reg) readl(dev->iomem + reg)