Lines Matching refs:dev_priv
178 struct drm_i915_private *dev_priv = in ivb_parity_work() local
179 container_of(work, typeof(*dev_priv), l3_parity.error_work); in ivb_parity_work()
180 struct intel_gt *gt = to_gt(dev_priv); in ivb_parity_work()
190 mutex_lock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
193 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
196 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL, in ivb_parity_work()
198 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
200 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivb_parity_work()
204 if (drm_WARN_ON_ONCE(&dev_priv->drm, in ivb_parity_work()
205 slice >= NUM_L3_SLICES(dev_priv))) in ivb_parity_work()
208 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivb_parity_work()
212 error_status = intel_uncore_read(&dev_priv->uncore, reg); in ivb_parity_work()
217 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); in ivb_parity_work()
218 intel_uncore_posting_read(&dev_priv->uncore, reg); in ivb_parity_work()
227 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, in ivb_parity_work()
230 drm_dbg(&dev_priv->drm, in ivb_parity_work()
240 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in ivb_parity_work()
243 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
245 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); in ivb_parity_work()
248 mutex_unlock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
253 struct drm_i915_private *dev_priv = arg; in valleyview_irq_handler() local
256 if (!intel_irqs_enabled(dev_priv)) in valleyview_irq_handler()
260 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
268 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); in valleyview_irq_handler()
269 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); in valleyview_irq_handler()
270 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
290 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_handler()
291 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); in valleyview_irq_handler()
294 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); in valleyview_irq_handler()
296 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); in valleyview_irq_handler()
299 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in valleyview_irq_handler()
303 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in valleyview_irq_handler()
307 intel_lpe_audio_irq_handler(dev_priv); in valleyview_irq_handler()
314 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in valleyview_irq_handler()
316 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in valleyview_irq_handler()
317 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_handler()
320 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir); in valleyview_irq_handler()
322 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); in valleyview_irq_handler()
325 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in valleyview_irq_handler()
327 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); in valleyview_irq_handler()
330 pmu_irq_stats(dev_priv, ret); in valleyview_irq_handler()
332 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
339 struct drm_i915_private *dev_priv = arg; in cherryview_irq_handler() local
342 if (!intel_irqs_enabled(dev_priv)) in cherryview_irq_handler()
346 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
354 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
355 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
375 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
376 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0); in cherryview_irq_handler()
378 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); in cherryview_irq_handler()
381 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in cherryview_irq_handler()
385 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in cherryview_irq_handler()
390 intel_lpe_audio_irq_handler(dev_priv); in cherryview_irq_handler()
397 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in cherryview_irq_handler()
399 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in cherryview_irq_handler()
400 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
403 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in cherryview_irq_handler()
405 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); in cherryview_irq_handler()
408 pmu_irq_stats(dev_priv, ret); in cherryview_irq_handler()
410 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
513 struct drm_i915_private *dev_priv = arg; in gen8_irq_handler() local
514 void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore); in gen8_irq_handler()
517 if (!intel_irqs_enabled(dev_priv)) in gen8_irq_handler()
527 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); in gen8_irq_handler()
531 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
532 gen8_de_irq_handler(dev_priv, master_ctl); in gen8_irq_handler()
533 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
538 pmu_irq_stats(dev_priv, IRQ_HANDLED); in gen8_irq_handler()
662 static void ibx_irq_reset(struct drm_i915_private *dev_priv) in ibx_irq_reset() argument
664 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_reset()
666 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_reset()
671 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
672 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); in ibx_irq_reset()
677 static void ilk_irq_reset(struct drm_i915_private *dev_priv) in ilk_irq_reset() argument
679 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_reset()
682 dev_priv->irq_mask = ~0u; in ilk_irq_reset()
684 if (GRAPHICS_VER(dev_priv) == 7) in ilk_irq_reset()
687 if (IS_HASWELL(dev_priv)) { in ilk_irq_reset()
692 gen5_gt_irq_reset(to_gt(dev_priv)); in ilk_irq_reset()
694 ibx_irq_reset(dev_priv); in ilk_irq_reset()
697 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) in valleyview_irq_reset() argument
699 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_reset()
700 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_reset()
702 gen5_gt_irq_reset(to_gt(dev_priv)); in valleyview_irq_reset()
704 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
705 if (dev_priv->display_irqs_enabled) in valleyview_irq_reset()
706 vlv_display_irq_reset(dev_priv); in valleyview_irq_reset()
707 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
710 static void gen8_irq_reset(struct drm_i915_private *dev_priv) in gen8_irq_reset() argument
712 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_reset()
716 gen8_gt_irq_reset(to_gt(dev_priv)); in gen8_irq_reset()
717 gen8_display_irq_reset(dev_priv); in gen8_irq_reset()
720 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_reset()
721 ibx_irq_reset(dev_priv); in gen8_irq_reset()
725 static void gen11_irq_reset(struct drm_i915_private *dev_priv) in gen11_irq_reset() argument
727 struct intel_gt *gt = to_gt(dev_priv); in gen11_irq_reset()
730 gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); in gen11_irq_reset()
733 gen11_display_irq_reset(dev_priv); in gen11_irq_reset()
739 static void dg1_irq_reset(struct drm_i915_private *dev_priv) in dg1_irq_reset() argument
741 struct intel_uncore *uncore = &dev_priv->uncore; in dg1_irq_reset()
745 dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore)); in dg1_irq_reset()
747 for_each_gt(gt, dev_priv, i) in dg1_irq_reset()
750 gen11_display_irq_reset(dev_priv); in dg1_irq_reset()
756 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) in cherryview_irq_reset() argument
758 struct intel_uncore *uncore = &dev_priv->uncore; in cherryview_irq_reset()
761 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_reset()
763 gen8_gt_irq_reset(to_gt(dev_priv)); in cherryview_irq_reset()
767 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
768 if (dev_priv->display_irqs_enabled) in cherryview_irq_reset()
769 vlv_display_irq_reset(dev_priv); in cherryview_irq_reset()
770 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
773 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) in ilk_irq_postinstall() argument
775 gen5_gt_irq_postinstall(to_gt(dev_priv)); in ilk_irq_postinstall()
777 ilk_de_irq_postinstall(dev_priv); in ilk_irq_postinstall()
780 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) in valleyview_irq_postinstall() argument
782 gen5_gt_irq_postinstall(to_gt(dev_priv)); in valleyview_irq_postinstall()
784 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
785 if (dev_priv->display_irqs_enabled) in valleyview_irq_postinstall()
786 vlv_display_irq_postinstall(dev_priv); in valleyview_irq_postinstall()
787 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
789 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_postinstall()
790 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_postinstall()
793 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_irq_postinstall() argument
795 gen8_gt_irq_postinstall(to_gt(dev_priv)); in gen8_irq_postinstall()
796 gen8_de_irq_postinstall(dev_priv); in gen8_irq_postinstall()
798 gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore)); in gen8_irq_postinstall()
801 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) in gen11_irq_postinstall() argument
803 struct intel_gt *gt = to_gt(dev_priv); in gen11_irq_postinstall()
808 gen11_de_irq_postinstall(dev_priv); in gen11_irq_postinstall()
813 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); in gen11_irq_postinstall()
816 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) in dg1_irq_postinstall() argument
818 struct intel_uncore *uncore = &dev_priv->uncore; in dg1_irq_postinstall()
823 for_each_gt(gt, dev_priv, i) in dg1_irq_postinstall()
828 dg1_de_irq_postinstall(dev_priv); in dg1_irq_postinstall()
834 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) in cherryview_irq_postinstall() argument
836 gen8_gt_irq_postinstall(to_gt(dev_priv)); in cherryview_irq_postinstall()
838 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
839 if (dev_priv->display_irqs_enabled) in cherryview_irq_postinstall()
840 vlv_display_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
841 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
843 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_postinstall()
844 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_postinstall()
847 static void i8xx_irq_reset(struct drm_i915_private *dev_priv) in i8xx_irq_reset() argument
849 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_reset()
851 i9xx_pipestat_irq_reset(dev_priv); in i8xx_irq_reset()
854 dev_priv->irq_mask = ~0u; in i8xx_irq_reset()
878 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv) in i8xx_irq_postinstall() argument
880 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_postinstall()
883 intel_uncore_write16(uncore, EMR, i9xx_error_mask(dev_priv)); in i8xx_irq_postinstall()
886 dev_priv->irq_mask = in i8xx_irq_postinstall()
897 gen2_irq_init(uncore, dev_priv->irq_mask, enable_mask); in i8xx_irq_postinstall()
901 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
902 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
903 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
904 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
935 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, in i8xx_error_irq_handler() argument
938 drm_dbg(&dev_priv->drm, "Master Error: EIR 0x%04x\n", eir); in i8xx_error_irq_handler()
941 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", in i8xx_error_irq_handler()
944 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", in i8xx_error_irq_handler()
945 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); in i8xx_error_irq_handler()
948 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, in i9xx_error_irq_ack() argument
953 *eir = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
954 intel_uncore_write(&dev_priv->uncore, EIR, *eir); in i9xx_error_irq_ack()
956 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
970 emr = intel_uncore_read(&dev_priv->uncore, EMR); in i9xx_error_irq_ack()
971 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); in i9xx_error_irq_ack()
972 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); in i9xx_error_irq_ack()
975 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, in i9xx_error_irq_handler() argument
978 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir); in i9xx_error_irq_handler()
981 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", in i9xx_error_irq_handler()
984 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n", in i9xx_error_irq_handler()
985 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); in i9xx_error_irq_handler()
990 struct drm_i915_private *dev_priv = arg; in i8xx_irq_handler() local
993 if (!intel_irqs_enabled(dev_priv)) in i8xx_irq_handler()
997 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
1004 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); in i8xx_irq_handler()
1012 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
1015 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i8xx_irq_handler()
1017 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); in i8xx_irq_handler()
1020 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i8xx_irq_handler()
1023 i8xx_error_irq_handler(dev_priv, eir, eir_stuck); in i8xx_irq_handler()
1025 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
1028 pmu_irq_stats(dev_priv, ret); in i8xx_irq_handler()
1030 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
1035 static void i915_irq_reset(struct drm_i915_private *dev_priv) in i915_irq_reset() argument
1037 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_reset()
1039 if (I915_HAS_HOTPLUG(dev_priv)) { in i915_irq_reset()
1040 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i915_irq_reset()
1041 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_STAT, 0, 0); in i915_irq_reset()
1044 i9xx_pipestat_irq_reset(dev_priv); in i915_irq_reset()
1047 dev_priv->irq_mask = ~0u; in i915_irq_reset()
1050 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) in i915_irq_postinstall() argument
1052 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_postinstall()
1055 intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv)); in i915_irq_postinstall()
1058 dev_priv->irq_mask = in i915_irq_postinstall()
1071 if (I915_HAS_HOTPLUG(dev_priv)) { in i915_irq_postinstall()
1075 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
1078 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i915_irq_postinstall()
1082 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
1083 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1084 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1085 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
1087 i915_enable_asle_pipestat(dev_priv); in i915_irq_postinstall()
1092 struct drm_i915_private *dev_priv = arg; in i915_irq_handler() local
1095 if (!intel_irqs_enabled(dev_priv)) in i915_irq_handler()
1099 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
1107 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i915_irq_handler()
1113 if (I915_HAS_HOTPLUG(dev_priv) && in i915_irq_handler()
1115 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in i915_irq_handler()
1119 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i915_irq_handler()
1122 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i915_irq_handler()
1124 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i915_irq_handler()
1127 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i915_irq_handler()
1130 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); in i915_irq_handler()
1133 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in i915_irq_handler()
1135 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i915_irq_handler()
1138 pmu_irq_stats(dev_priv, ret); in i915_irq_handler()
1140 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
1145 static void i965_irq_reset(struct drm_i915_private *dev_priv) in i965_irq_reset() argument
1147 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_reset()
1149 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i965_irq_reset()
1152 i9xx_pipestat_irq_reset(dev_priv); in i965_irq_reset()
1155 dev_priv->irq_mask = ~0u; in i965_irq_reset()
1177 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) in i965_irq_postinstall() argument
1179 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_postinstall()
1182 intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv)); in i965_irq_postinstall()
1185 dev_priv->irq_mask = in i965_irq_postinstall()
1200 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
1203 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i965_irq_postinstall()
1207 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
1208 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
1209 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
1210 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
1211 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
1213 i915_enable_asle_pipestat(dev_priv); in i965_irq_postinstall()
1218 struct drm_i915_private *dev_priv = arg; in i965_irq_handler() local
1221 if (!intel_irqs_enabled(dev_priv)) in i965_irq_handler()
1225 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
1233 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i965_irq_handler()
1240 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in i965_irq_handler()
1244 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i965_irq_handler()
1247 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i965_irq_handler()
1249 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i965_irq_handler()
1252 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], in i965_irq_handler()
1256 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], in i965_irq_handler()
1260 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); in i965_irq_handler()
1263 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in i965_irq_handler()
1265 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i965_irq_handler()
1268 pmu_irq_stats(dev_priv, IRQ_HANDLED); in i965_irq_handler()
1270 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
1282 void intel_irq_init(struct drm_i915_private *dev_priv) in intel_irq_init() argument
1286 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); in intel_irq_init()
1288 dev_priv->l3_parity.remap_info[i] = NULL; in intel_irq_init()
1291 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11) in intel_irq_init()
1292 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16; in intel_irq_init()
1309 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) in intel_irq_handler() argument
1311 if (HAS_GMCH(dev_priv)) { in intel_irq_handler()
1312 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_handler()
1314 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
1316 else if (GRAPHICS_VER(dev_priv) == 4) in intel_irq_handler()
1318 else if (GRAPHICS_VER(dev_priv) == 3) in intel_irq_handler()
1323 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_handler()
1325 else if (GRAPHICS_VER(dev_priv) >= 11) in intel_irq_handler()
1327 else if (GRAPHICS_VER(dev_priv) >= 8) in intel_irq_handler()
1334 static void intel_irq_reset(struct drm_i915_private *dev_priv) in intel_irq_reset() argument
1336 if (HAS_GMCH(dev_priv)) { in intel_irq_reset()
1337 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_reset()
1338 cherryview_irq_reset(dev_priv); in intel_irq_reset()
1339 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
1340 valleyview_irq_reset(dev_priv); in intel_irq_reset()
1341 else if (GRAPHICS_VER(dev_priv) == 4) in intel_irq_reset()
1342 i965_irq_reset(dev_priv); in intel_irq_reset()
1343 else if (GRAPHICS_VER(dev_priv) == 3) in intel_irq_reset()
1344 i915_irq_reset(dev_priv); in intel_irq_reset()
1346 i8xx_irq_reset(dev_priv); in intel_irq_reset()
1348 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_reset()
1349 dg1_irq_reset(dev_priv); in intel_irq_reset()
1350 else if (GRAPHICS_VER(dev_priv) >= 11) in intel_irq_reset()
1351 gen11_irq_reset(dev_priv); in intel_irq_reset()
1352 else if (GRAPHICS_VER(dev_priv) >= 8) in intel_irq_reset()
1353 gen8_irq_reset(dev_priv); in intel_irq_reset()
1355 ilk_irq_reset(dev_priv); in intel_irq_reset()
1359 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) in intel_irq_postinstall() argument
1361 if (HAS_GMCH(dev_priv)) { in intel_irq_postinstall()
1362 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_postinstall()
1363 cherryview_irq_postinstall(dev_priv); in intel_irq_postinstall()
1364 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
1365 valleyview_irq_postinstall(dev_priv); in intel_irq_postinstall()
1366 else if (GRAPHICS_VER(dev_priv) == 4) in intel_irq_postinstall()
1367 i965_irq_postinstall(dev_priv); in intel_irq_postinstall()
1368 else if (GRAPHICS_VER(dev_priv) == 3) in intel_irq_postinstall()
1369 i915_irq_postinstall(dev_priv); in intel_irq_postinstall()
1371 i8xx_irq_postinstall(dev_priv); in intel_irq_postinstall()
1373 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) in intel_irq_postinstall()
1374 dg1_irq_postinstall(dev_priv); in intel_irq_postinstall()
1375 else if (GRAPHICS_VER(dev_priv) >= 11) in intel_irq_postinstall()
1376 gen11_irq_postinstall(dev_priv); in intel_irq_postinstall()
1377 else if (GRAPHICS_VER(dev_priv) >= 8) in intel_irq_postinstall()
1378 gen8_irq_postinstall(dev_priv); in intel_irq_postinstall()
1380 ilk_irq_postinstall(dev_priv); in intel_irq_postinstall()
1395 int intel_irq_install(struct drm_i915_private *dev_priv) in intel_irq_install() argument
1397 int irq = to_pci_dev(dev_priv->drm.dev)->irq; in intel_irq_install()
1405 dev_priv->runtime_pm.irqs_enabled = true; in intel_irq_install()
1407 dev_priv->irq_enabled = true; in intel_irq_install()
1409 intel_irq_reset(dev_priv); in intel_irq_install()
1411 ret = request_irq(irq, intel_irq_handler(dev_priv), in intel_irq_install()
1412 IRQF_SHARED, DRIVER_NAME, dev_priv); in intel_irq_install()
1414 dev_priv->irq_enabled = false; in intel_irq_install()
1418 intel_irq_postinstall(dev_priv); in intel_irq_install()
1430 void intel_irq_uninstall(struct drm_i915_private *dev_priv) in intel_irq_uninstall() argument
1432 int irq = to_pci_dev(dev_priv->drm.dev)->irq; in intel_irq_uninstall()
1440 if (!dev_priv->irq_enabled) in intel_irq_uninstall()
1443 dev_priv->irq_enabled = false; in intel_irq_uninstall()
1445 intel_irq_reset(dev_priv); in intel_irq_uninstall()
1447 free_irq(irq, dev_priv); in intel_irq_uninstall()
1449 intel_hpd_cancel_work(dev_priv); in intel_irq_uninstall()
1450 dev_priv->runtime_pm.irqs_enabled = false; in intel_irq_uninstall()
1460 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_disable_interrupts() argument
1462 intel_irq_reset(dev_priv); in intel_runtime_pm_disable_interrupts()
1463 dev_priv->runtime_pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
1464 intel_synchronize_irq(dev_priv); in intel_runtime_pm_disable_interrupts()
1474 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable_interrupts() argument
1476 dev_priv->runtime_pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
1477 intel_irq_reset(dev_priv); in intel_runtime_pm_enable_interrupts()
1478 intel_irq_postinstall(dev_priv); in intel_runtime_pm_enable_interrupts()
1481 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) in intel_irqs_enabled() argument
1483 return dev_priv->runtime_pm.irqs_enabled; in intel_irqs_enabled()