33 	} dot, vco, n, m, m1, m2, p, p1;  member
46 	.m2 = { .min = 6, .max = 16 },
59 	.m2 = { .min = 6, .max = 16 },
72 	.m2 = { .min = 6, .max = 16 },
85 	.m2 = { .min = 3, .max = 7 },
98 	.m2 = { .min = 3, .max = 7 },
112 	.m2 = { .min = 5, .max = 11 },
127 	.m2 = { .min = 5, .max = 11 },
140 	.m2 = { .min = 5, .max = 11 },
154 	.m2 = { .min = 5, .max = 11 },
168 	/* Pineview only has one combined m divider, which we treat as m2. */
170 	.m2 = { .min = 0, .max = 254 },
183 	.m2 = { .min = 0, .max = 254 },
192  * We calculate clock using (register_value + 2) for N/M1/M2, so here
201 	.m2 = { .min = 5, .max = 9 },
214 	.m2 = { .min = 5, .max = 9 },
227 	.m2 = { .min = 5, .max = 9 },
241 	.m2 = { .min = 5, .max = 9 },
254 	.m2 = { .min = 5, .max = 9 },
272 	.m2 = { .min = 11, .max = 156 },
288 	.m2 = { .min = 24 << 22, .max = 175 << 22 },
298 	/* FIXME: find real m2 limits */
299 	.m2 = { .min = 2 << 22, .max = 255 << 22 },
315 	clock->m = clock->m2 + 2;  in pnv_calc_dpll_params()
327 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
344 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
356 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
379 	if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)  in intel_pll_is_valid()
385 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
457 		for (clock.m2 = limit->m2.min;  in i9xx_find_best_dpll()
458 		     clock.m2 <= limit->m2.max; clock.m2++) {  in i9xx_find_best_dpll()
459 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
515 		for (clock.m2 = limit->m2.min;  in pnv_find_best_dpll()
516 		     clock.m2 <= limit->m2.max; clock.m2++) {  in pnv_find_best_dpll()
575 		/* based on hardware requirement, prefere larger m1,m2 */  in g4x_find_best_dpll()
578 			for (clock.m2 = limit->m2.max;  in g4x_find_best_dpll()
579 			     clock.m2 >= limit->m2.min; clock.m2--) {  in g4x_find_best_dpll()
671 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
675 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,  in vlv_find_best_dpll()
717 	u64 m2;  in chv_find_best_dpll()  local
739 			m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,  in chv_find_best_dpll()
742 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
745 			clock.m2 = m2;  in chv_find_best_dpll()
778 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
783 	return (1 << dpll->n) << 16 | dpll->m2;  in pnv_dpll_compute_fp()
1672 	bestm2 = crtc_state->dpll.m2;  in vlv_prepare_pll()
1800 	bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;  in chv_prepare_pll()
1801 	bestm2 = crtc_state->dpll.m2 >> 22;  in chv_prepare_pll()
1817 	/* Feedback post-divider - m2 */  in chv_prepare_pll()
1825 	/* M2 fraction division */  in chv_prepare_pll()
1828 	/* M2 fraction division enable */  in chv_prepare_pll()