Lines Matching full:cdclk
44 * DOC: CDCLK / RAWCLK
49 * are the core display clock (CDCLK) and RAWCLK.
51 * CDCLK clocks most of the display pipe logic, and thus its frequency
56 * On several platforms the CDCLK frequency can be changed dynamically
58 * Typically changes to the CDCLK frequency require all the display pipes
61 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
62 * DMC will not change the active CDCLK frequency however, so that part
78 u8 (*calc_voltage_level)(int cdclk);
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
101 int cdclk) in intel_cdclk_calc_voltage_level() argument
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
121 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
127 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
133 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
139 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
154 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
168 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
171 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
174 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
179 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
193 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
199 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
203 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
217 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
223 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
227 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
340 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
346 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", in g33_get_cdclk()
348 cdclk_config->cdclk = 190476; in g33_get_cdclk()
361 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
364 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
367 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
370 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
377 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
380 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
419 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
425 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", in i965gm_get_cdclk()
427 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
447 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
450 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
454 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", in gm45_get_cdclk()
456 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
468 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
470 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
472 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
474 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
476 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
499 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
502 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in vlv_calc_voltage_level()
504 else if (cdclk >= 266667) in vlv_calc_voltage_level()
514 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
527 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
553 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
585 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk() local
589 switch (cdclk) { in vlv_set_cdclk()
597 MISSING_CASE(cdclk); in vlv_set_cdclk()
602 * off and a CDCLK frequency other than the minimum, like when in vlv_set_cdclk()
622 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
625 if (cdclk == 400000) { in vlv_set_cdclk()
629 cdclk) - 1; in vlv_set_cdclk()
631 /* adjust cdclk divider */ in vlv_set_cdclk()
641 "timed out waiting for CDclk change\n"); in vlv_set_cdclk()
652 if (cdclk == 400000) in vlv_set_cdclk()
674 int cdclk = cdclk_config->cdclk; in chv_set_cdclk() local
678 switch (cdclk) { in chv_set_cdclk()
685 MISSING_CASE(cdclk); in chv_set_cdclk()
690 * off and a CDCLK frequency other than the minimum, like when in chv_set_cdclk()
706 "timed out waiting for CDclk change\n"); in chv_set_cdclk()
730 static u8 bdw_calc_voltage_level(int cdclk) in bdw_calc_voltage_level() argument
732 switch (cdclk) { in bdw_calc_voltage_level()
752 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
754 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
756 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
758 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
760 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
762 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
766 * at least what the CDCLK frequency requires. in bdw_get_cdclk()
769 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
772 static u32 bdw_cdclk_freq_sel(int cdclk) in bdw_cdclk_freq_sel() argument
774 switch (cdclk) { in bdw_cdclk_freq_sel()
776 MISSING_CASE(cdclk); in bdw_cdclk_freq_sel()
793 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk() local
802 "trying to change cdclk frequency with cdclk not enabled\n")) in bdw_set_cdclk()
808 "failed to inform pcode about cdclk change\n"); in bdw_set_cdclk()
824 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); in bdw_set_cdclk()
837 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
865 static u8 skl_calc_voltage_level(int cdclk) in skl_calc_voltage_level() argument
867 if (cdclk > 540000) in skl_calc_voltage_level()
869 else if (cdclk > 450000) in skl_calc_voltage_level()
871 else if (cdclk > 337500) in skl_calc_voltage_level()
925 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
935 cdclk_config->cdclk = 432000; in skl_get_cdclk()
938 cdclk_config->cdclk = 308571; in skl_get_cdclk()
941 cdclk_config->cdclk = 540000; in skl_get_cdclk()
944 cdclk_config->cdclk = 617143; in skl_get_cdclk()
953 cdclk_config->cdclk = 450000; in skl_get_cdclk()
956 cdclk_config->cdclk = 337500; in skl_get_cdclk()
959 cdclk_config->cdclk = 540000; in skl_get_cdclk()
962 cdclk_config->cdclk = 675000; in skl_get_cdclk()
973 * at least what the CDCLK frequency requires. in skl_get_cdclk()
976 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
980 static int skl_cdclk_decimal(int cdclk) in skl_cdclk_decimal() argument
982 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1031 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1045 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1049 int cdclk, int vco) in skl_cdclk_freq_sel() argument
1051 switch (cdclk) { in skl_cdclk_freq_sel()
1054 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1075 int cdclk = cdclk_config->cdclk; in skl_set_cdclk() local
1081 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are in skl_set_cdclk()
1086 * minimum 308MHz CDCLK. in skl_set_cdclk()
1097 "Failed to inform PCU about cdclk change (%d)\n", ret); in skl_set_cdclk()
1101 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1103 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1104 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1109 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1112 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1121 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1128 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1156 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1159 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1160 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1171 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1177 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1179 /* force cdclk programming */ in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1182 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1191 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1192 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1199 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1203 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1208 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1209 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1216 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1218 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1220 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1226 u32 cdclk; member
1234 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1235 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1243 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1244 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1245 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1250 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1251 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1252 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1253 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1254 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1255 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1257 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1258 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1259 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1260 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1261 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1262 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1264 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1265 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1266 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1267 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1268 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1269 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1274 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1275 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1276 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1277 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1278 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1279 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1281 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1282 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1283 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1284 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1285 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1286 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1288 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1289 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1290 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1291 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1292 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1293 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1298 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1299 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1300 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1302 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1303 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1304 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1306 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1307 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1308 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1313 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1314 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1315 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1316 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1317 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1319 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1320 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1321 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1322 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1323 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1325 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1326 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1327 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1328 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1329 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1334 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1335 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1336 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1337 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
1338 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1339 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1341 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1342 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1343 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1344 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
1345 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1346 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1348 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1349 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1350 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1351 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
1352 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1353 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1358 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1359 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1360 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1361 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1362 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1363 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1364 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1365 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1366 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1367 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1368 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1369 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1370 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1375 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1376 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1377 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
1378 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
1379 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
1380 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
1386 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1390 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1391 table[i].cdclk >= min_cdclk) in bxt_calc_cdclk()
1392 return table[i].cdclk; in bxt_calc_cdclk()
1395 "Cannot satisfy minimum cdclk %d with refclk %u\n", in bxt_calc_cdclk()
1396 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1400 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1402 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1405 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1409 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1410 table[i].cdclk == cdclk) in bxt_calc_cdclk_pll_vco()
1411 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1413 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1414 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1418 static u8 bxt_calc_voltage_level(int cdclk) in bxt_calc_voltage_level() argument
1420 return DIV_ROUND_UP(cdclk, 25000); in bxt_calc_voltage_level()
1423 static u8 icl_calc_voltage_level(int cdclk) in icl_calc_voltage_level() argument
1425 if (cdclk > 556800) in icl_calc_voltage_level()
1427 else if (cdclk > 312000) in icl_calc_voltage_level()
1433 static u8 ehl_calc_voltage_level(int cdclk) in ehl_calc_voltage_level() argument
1435 if (cdclk > 326400) in ehl_calc_voltage_level()
1437 else if (cdclk > 312000) in ehl_calc_voltage_level()
1439 else if (cdclk > 180000) in ehl_calc_voltage_level()
1445 static u8 tgl_calc_voltage_level(int cdclk) in tgl_calc_voltage_level() argument
1447 if (cdclk > 556800) in tgl_calc_voltage_level()
1449 else if (cdclk > 326400) in tgl_calc_voltage_level()
1451 else if (cdclk > 312000) in tgl_calc_voltage_level()
1457 static u8 rplu_calc_voltage_level(int cdclk) in rplu_calc_voltage_level() argument
1459 if (cdclk > 556800) in rplu_calc_voltage_level()
1461 else if (cdclk > 480000) in rplu_calc_voltage_level()
1463 else if (cdclk > 312000) in rplu_calc_voltage_level()
1506 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but in bxt_de_pll_readout()
1542 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1576 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1579 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1585 * at least what the CDCLK frequency requires. in bxt_get_cdclk()
1588 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1600 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1605 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1617 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1627 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1629 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1634 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1645 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1647 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1652 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1671 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1695 int cdclk, int vco) in bxt_cdclk_cd2x_div_sel() argument
1697 /* cdclk = vco / 2 / div{1,1.5,2,4} */ in bxt_cdclk_cd2x_div_sel()
1698 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in bxt_cdclk_cd2x_div_sel()
1701 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1716 int cdclk) in cdclk_squash_waveform() argument
1718 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1721 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1725 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1726 table[i].cdclk == cdclk) in cdclk_squash_waveform()
1729 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1730 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1737 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1738 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1741 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1747 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1748 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1751 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1799 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1800 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1812 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
1813 * The mid cdclk config should have the new (squash) waveform. in cdclk_compute_crawl_and_squash_midpoint()
1814 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
1815 * The mid cdclk config should have the new vco. in cdclk_compute_crawl_and_squash_midpoint()
1826 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
1831 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
1832 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
1833 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
1834 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1835 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
1844 dev_priv->display.cdclk.hw.vco > 0 && in pll_enable_wa_needed()
1852 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk() local
1858 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1859 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1860 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1871 waveform = cdclk_squash_waveform(dev_priv, cdclk); in _bxt_set_cdclk()
1876 clock = cdclk; in _bxt_set_cdclk()
1883 skl_cdclk_decimal(cdclk); in _bxt_set_cdclk()
1890 cdclk >= 500000) in _bxt_set_cdclk()
1903 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk() local
1930 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", in bxt_set_cdclk()
1931 ret, cdclk); in bxt_set_cdclk()
1935 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
1965 "PCode CDCLK freq set failed, (err %d, freq %d)\n", in bxt_set_cdclk()
1966 ret, cdclk); in bxt_set_cdclk()
1977 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1983 int cdclk, clock, vco; in bxt_sanitize_cdclk() local
1986 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1988 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1989 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
2006 /* Make sure this is a legal cdclk value for the platform */ in bxt_sanitize_cdclk()
2007 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2008 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2011 /* Make sure the VCO is correct for the cdclk */ in bxt_sanitize_cdclk()
2012 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
2013 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2016 expected = skl_cdclk_decimal(cdclk); in bxt_sanitize_cdclk()
2018 /* Figure out what CD2X divider we should be using for this cdclk */ in bxt_sanitize_cdclk()
2020 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
2022 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
2025 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
2032 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
2040 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2042 /* force cdclk programming */ in bxt_sanitize_cdclk()
2043 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2046 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
2055 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2056 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2059 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2063 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2066 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2067 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2069 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2076 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2078 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2081 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2087 * intel_cdclk_init_hw - Initialize CDCLK hardware
2090 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2093 * take care of turning CDCLK off/on as needed.
2104 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2107 * Uninitialize CDCLK. This is done only during the display core
2133 old_waveform = cdclk_squash_waveform(i915, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2134 new_waveform = cdclk_squash_waveform(i915, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2153 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2154 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2175 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2182 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2184 * @a: first CDCLK configuration
2185 * @b: second CDCLK configuration
2188 * True if changing between the two CDCLK configurations
2194 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
2200 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2203 * @a: first CDCLK configuration
2204 * @b: second CDCLK configuration
2207 * True if changing between the two CDCLK configurations
2227 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2234 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2235 * @a: first CDCLK configuration
2236 * @b: second CDCLK configuration
2239 * True if the CDCLK configurations don't match, false if they do.
2253 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2261 u16 cdclk, in intel_pcode_notify() argument
2271 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); in intel_pcode_notify()
2291 * intel_set_cdclk - Push the CDCLK configuration to the hardware
2293 * @cdclk_config: new CDCLK configuration
2296 * Program the hardware based on the passed in CDCLK state,
2305 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2308 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2311 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); in intel_set_cdclk()
2322 * Lock aux/gmbus while we change cdclk in case those in intel_set_cdclk()
2323 * functions use cdclk. Not all platforms/ports do, in intel_set_cdclk()
2352 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2353 "cdclk state doesn't match!\n")) { in intel_set_cdclk()
2354 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2366 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_pre_notify() local
2378 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2384 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, in intel_cdclk_pcode_pre_notify()
2385 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, in intel_cdclk_pcode_pre_notify()
2386 * which basically means we choose the maximum of old and new CDCLK, if we know both in intel_cdclk_pcode_pre_notify()
2389 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2400 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2411 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; in intel_cdclk_pcode_post_notify() local
2417 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2423 * set bits 25:16 to current CDCLK in intel_cdclk_pcode_post_notify()
2426 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2437 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2442 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2446 * new CDCLK state, if necessary.
2470 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2488 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2492 * new CDCLK state, if necessary.
2512 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2564 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ in intel_crtc_compute_min_cdclk()
2568 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, in intel_crtc_compute_min_cdclk()
2570 * there may be audio corruption or screen corruption." This cdclk in intel_crtc_compute_min_cdclk()
2594 * "For DP audio configuration, cdclk frequency shall be set to in intel_crtc_compute_min_cdclk()
2596 * DP Link Frequency(MHz) | Cdclk frequency(MHz) in intel_crtc_compute_min_cdclk()
2613 * On Geminilake once the CDCLK gets as low as 79200 in intel_crtc_compute_min_cdclk()
2627 * cannot be higher than the VDSC clock (cdclk) in intel_crtc_compute_min_cdclk()
2629 * VDSC clock(cdclk) * 2 and so on. in intel_crtc_compute_min_cdclk()
2643 * however in some cases the lowest possible CDCLK in intel_crtc_compute_min_cdclk()
2655 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2711 * CDCLK frequency is always high enough for audio. With a in intel_compute_min_cdclk()
2712 * single active pipe we can always change CDCLK frequency in intel_compute_min_cdclk()
2720 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2722 "required cdclk (%d kHz) exceeds max (%d kHz)\n", in intel_compute_min_cdclk()
2723 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2783 int min_cdclk, cdclk; in vlv_modeset_calc_cdclk() local
2789 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2791 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2793 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2796 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2798 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2800 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2810 int min_cdclk, cdclk; in bdw_modeset_calc_cdclk() local
2816 cdclk = bdw_calc_cdclk(min_cdclk); in bdw_modeset_calc_cdclk()
2818 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2820 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2823 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2825 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2827 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2856 * clock for eDP. This will affect cdclk as well. in skl_dpll0_vco()
2874 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
2882 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
2885 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2887 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
2890 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2893 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2895 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
2907 int min_cdclk, min_voltage_level, cdclk, vco; in bxt_modeset_calc_cdclk() local
2917 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
2918 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2921 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2924 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); in bxt_modeset_calc_cdclk()
2927 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2928 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2931 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2933 intel_cdclk_calc_voltage_level(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2946 * We can't change the cdclk frequency, but we still want to in fixed_modeset_calc_cdclk()
2948 * the actual cdclk frequency. in fixed_modeset_calc_cdclk()
2988 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3007 * planes are part of the state. We can now compute the minimum cdclk in intel_cdclk_atomic_check()
3038 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3121 "Can change cdclk via crawling and squashing\n"); in intel_modeset_calc_cdclk()
3126 "Can change cdclk via squashing\n"); in intel_modeset_calc_cdclk()
3131 "Can change cdclk via crawling\n"); in intel_modeset_calc_cdclk()
3136 "Can change cdclk cd2x divider with pipe %c active\n", in intel_modeset_calc_cdclk()
3140 /* All pipes must be switched off while we change the cdclk. */ in intel_modeset_calc_cdclk()
3141 ret = intel_modeset_all_pipes(state, "CDCLK change"); in intel_modeset_calc_cdclk()
3148 "Modeset required for cdclk change\n"); in intel_modeset_calc_cdclk()
3152 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", in intel_modeset_calc_cdclk()
3153 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3154 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3165 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3181 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3184 * Determine the maximum CDCLK frequency the platform supports, and also
3185 * derive the maximum dot clock frequency the maximum CDCLK frequency
3191 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3192 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3194 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3196 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3197 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3199 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3201 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3203 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3212 * Use the lower (vco 8640) cdclk values as a in intel_update_max_cdclk()
3225 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3234 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3236 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3238 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3240 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3242 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3244 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3246 /* otherwise assume cdclk is fixed */ in intel_update_max_cdclk()
3247 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3253 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3260 * intel_update_cdclk - Determine the current CDCLK frequency
3263 * Determine the current CDCLK frequency.
3267 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3270 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): in intel_update_cdclk()
3272 * of cdclk that generates 4MHz reference clock freq which is used to in intel_update_cdclk()
3273 * generate GMBus clock. This will vary with the cdclk freq. in intel_update_cdclk()
3277 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3428 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in i915_cdclk_info_show()
3429 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3589 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3595 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3596 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3598 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3599 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3603 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3604 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3606 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3607 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3609 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3610 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3613 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3614 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3616 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3617 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3619 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3620 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3622 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3623 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3625 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3627 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3629 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3631 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3633 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3635 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3637 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3639 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3641 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3643 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3645 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3647 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3649 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3651 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3653 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3655 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3657 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3659 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3661 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3663 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3665 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3667 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3669 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3671 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3674 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3676 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()