284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in __read_delay()
300 			if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)  in __read_delay()
326 		rd_interval = dpcd[offset];  in __read_delay()
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_clock_recovery_delay()
342 	return __read_delay(aux, dpcd, dp_phy, uhbr, true);  in drm_dp_read_clock_recovery_delay()
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_channel_eq_delay()
349 	return __read_delay(aux, dpcd, dp_phy, uhbr, false);  in drm_dp_read_channel_eq_delay()
374 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_link_train_clock_recovery_delay()
376 	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_link_train_clock_recovery_delay()
380 	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)  in drm_dp_link_train_clock_recovery_delay()
398 					const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_link_train_channel_eq_delay()
401 					     dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_link_train_channel_eq_delay()
801 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_is_type()
804 	return drm_dp_is_branch(dpcd) &&  in drm_dp_downstream_is_type()
805 		dpcd[DP_DPCD_REV] >= 0x11 &&  in drm_dp_downstream_is_type()
818 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_is_tmds()
822 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_is_tmds()
823 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_is_tmds()
905 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_downstream_port_count()
907 	u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;  in drm_dp_downstream_port_count()
909 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)  in drm_dp_downstream_port_count()
916 					  u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_read_extended_dpcd_caps()
928 	if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &  in drm_dp_read_extended_dpcd_caps()
939 	if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {  in drm_dp_read_extended_dpcd_caps()
942 			    aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);  in drm_dp_read_extended_dpcd_caps()
946 	if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))  in drm_dp_read_extended_dpcd_caps()
949 	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);  in drm_dp_read_extended_dpcd_caps()
951 	memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));  in drm_dp_read_extended_dpcd_caps()
970 			  u8 dpcd[DP_RECEIVER_CAP_SIZE])  in drm_dp_read_dpcd_caps()
974 	ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);  in drm_dp_read_dpcd_caps()
977 	if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)  in drm_dp_read_dpcd_caps()
980 	ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);  in drm_dp_read_dpcd_caps()
984 	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);  in drm_dp_read_dpcd_caps()
1004 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_downstream_info()
1013 	if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)  in drm_dp_read_downstream_info()
1020 	len = drm_dp_downstream_port_count(dpcd);  in drm_dp_read_downstream_info()
1024 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)  in drm_dp_read_downstream_info()
1047 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_dotclock()
1050 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_max_dotclock()
1053 	if (dpcd[DP_DPCD_REV] < 0x11)  in drm_dp_downstream_max_dotclock()
1058 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_dotclock()
1076 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_tmds_clock()
1080 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_max_tmds_clock()
1083 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_max_tmds_clock()
1084 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_max_tmds_clock()
1118 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_tmds_clock()
1122 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_tmds_clock()
1141 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_min_tmds_clock()
1145 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_min_tmds_clock()
1148 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_min_tmds_clock()
1149 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_min_tmds_clock()
1184 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_max_bpc()
1188 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_max_bpc()
1191 	if (dpcd[DP_DPCD_REV] < 0x11) {  in drm_dp_downstream_max_bpc()
1192 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {  in drm_dp_downstream_max_bpc()
1210 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_max_bpc()
1240 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_420_passthrough()
1243 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_420_passthrough()
1246 	if (dpcd[DP_DPCD_REV] < 0x13)  in drm_dp_downstream_420_passthrough()
1253 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_420_passthrough()
1271 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_444_to_420_conversion()
1274 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_444_to_420_conversion()
1277 	if (dpcd[DP_DPCD_REV] < 0x13)  in drm_dp_downstream_444_to_420_conversion()
1282 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_444_to_420_conversion()
1302 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1306 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1309 	if (dpcd[DP_DPCD_REV] < 0x13)  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1314 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1336 		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_mode()
1342 	if (!drm_dp_is_branch(dpcd))  in drm_dp_downstream_mode()
1345 	if (dpcd[DP_DPCD_REV] < 0x11)  in drm_dp_downstream_mode()
1402 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_downstream_debug()
1407 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_downstream_debug()
1415 	bool branch_device = drm_dp_is_branch(dpcd);  in drm_dp_downstream_debug()
1463 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);  in drm_dp_downstream_debug()
1467 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1471 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1475 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1489 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_subconnector_type()
1493 	if (!drm_dp_is_branch(dpcd))  in drm_dp_subconnector_type()
1496 	if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {  in drm_dp_subconnector_type()
1497 		type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in drm_dp_subconnector_type()
1546 				      const u8 *dpcd,  in drm_dp_set_subconnector_property()  argument
1552 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);  in drm_dp_set_subconnector_property()
1572 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_sink_count_cap()
1577 		dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&  in drm_dp_read_sink_count_cap()
1578 		dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&  in drm_dp_read_sink_count_cap()
2499 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,  in drm_dp_read_lttpr_regs()
2507 	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;  in drm_dp_read_lttpr_regs()
2535 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_lttpr_common_caps()
2538 	return drm_dp_read_lttpr_regs(aux, dpcd,  in drm_dp_read_lttpr_common_caps()
2556 			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_read_lttpr_phy_caps()
2560 	return drm_dp_read_lttpr_regs(aux, dpcd,  in drm_dp_read_lttpr_phy_caps()
2927 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],  in drm_dp_get_pcon_max_frl_bw()