drm/bridge/sil-sii8620.h

104 #define BIT_FAST_INTR_STAT_TIMR			8
192 /* Interrupt Source 8, default value: 0x00 */
198 /* Interrupt #8 Mask, default value: 0x00 */
240 /* BIST 8BIT_PATTERN, default value: 0x00 */
506 /* MHL Tx Control 6th, default value: 0xa0 */
730 /* MHL DataPath 4th Ctl, default value: 0x48 */
735 /* MHL DataPath 5th Ctl, default value: 0x48 */
740 /* MHL DataPath 6th Ctl, default value: 0x3f */
814 /* MHL CoC 4th Ctl, default value: 0x00 */
818 /* MHL CoC 5th Ctl, default value: 0x28 */
823 /* MHL CoC 6th Ctl, default value: 0x0d */
833 /* MHL DataPath 7th Ctl, default value: 0x2a */
842 /* MHL DataPath 8th Ctl, default value: 0x06 */
1125 /* CoC 4th Ctl, default value: 0x40 */
1130 /* CoC 7th Ctl, default value: 0x00 */
1136 /* CoC 8th Ctl, default value: 0x06 */
1144 /* CoC 10th Ctl, default value: 0x00 */
1147 /* CoC 11th Ctl, default value: 0x00 */
1150 /* CoC 12th Ctl, default value: 0x00 */
1153 /* CoC 13th Ctl, default value: 0x0f */
1156 /* CoC 14th Ctl, default value: 0x0a */
1161 /* CoC 15th Ctl, default value: 0x0a */
1166 /* CoC 16th Ctl, default value: 0x00 */
1171 /* CoC 18th Ctl, default value: 0x32 */
1199 /* CoC 24th Ctl, default value: 0x00 */
1204 /* CoC 25th Ctl, default value: 0x00 */
1209 /* CoC 26th Ctl, default value: 0x00 */
1214 /* CoC 27th Ctl, default value: 0x00 */
1219 /* DoC 9th Status, default value: 0x00 */
1222 /* DoC 10th Status, default value: 0x00 */
1225 /* DoC 5th CFG, default value: 0x00 */
1232 /* DoC 7th Ctl, default value: 0x00 */
1239 /* DoC 8th Ctl, default value: 0x00 */
1247 /* DoC 9th Ctl, default value: 0x00 */
1254 /* DoC 10th Ctl, default value: 0x00 */
1257 /* DoC 11th Ctl, default value: 0x00 */
1260 /* DoC 15th Ctl, default value: 0x00 */
1276 /* Interrupt Mask 4th, default value: 0x00 */
1403 /* CBUS_Link_Layer Control #8, default value: 0x00 */