Lines Matching +full:p2u +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
15 release_firmware(ast->dp501_fw); in ast_release_firmware()
16 ast->dp501_fw = NULL; in ast_release_firmware()
24 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); in ast_load_dp501_microcode()
28 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); in ast_load_dp501_microcode()
34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
68 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_nack()
69 waitack &= 0x80; in wait_nack()
81 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40); in set_cmd_trigger()
86 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00); in clear_cmd_trigger()
89 #if 0
93 u32 retry = 0;
95 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
96 waitready &= 0x40;
110 int retry = 0; in ast_write_cmd()
113 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_cmd()
135 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_data()
146 #if 0
152 *data = 0;
156 tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
169 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
175 ast_write_cmd(dev, 0x40); in ast_set_dp501_video_output()
183 return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff; in get_fw_base()
192 if (ast->config_mode != ast_use_p2a) in ast_backup_fw()
195 data = ast_mindwm(ast, 0x1e6e2100) & 0x01; in ast_backup_fw()
198 for (i = 0; i < size; i += 4) in ast_backup_fw()
208 u32 i, data, len = 0; in ast_launch_m68k()
213 if (ast->config_mode != ast_use_p2a) in ast_launch_m68k()
216 data = ast_mindwm(ast, 0x1e6e2100) & 0x01; in ast_launch_m68k()
219 if (ast->dp501_fw_addr) { in ast_launch_m68k()
220 fw_addr = ast->dp501_fw_addr; in ast_launch_m68k()
223 if (!ast->dp501_fw && in ast_launch_m68k()
224 ast_load_dp501_microcode(dev) < 0) in ast_launch_m68k()
227 fw_addr = (u8 *)ast->dp501_fw->data; in ast_launch_m68k()
228 len = ast->dp501_fw->size; in ast_launch_m68k()
231 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); in ast_launch_m68k()
232 data = ast_mindwm(ast, 0x1e6e0004); in ast_launch_m68k()
233 switch (data & 0x03) { in ast_launch_m68k()
234 case 0: in ast_launch_m68k()
235 boot_address = 0x44000000; in ast_launch_m68k()
239 boot_address = 0x48000000; in ast_launch_m68k()
242 boot_address = 0x50000000; in ast_launch_m68k()
245 boot_address = 0x60000000; in ast_launch_m68k()
248 boot_address -= 0x200000; /* -2MB */ in ast_launch_m68k()
251 for (i = 0; i < len; i += 4) { in ast_launch_m68k()
257 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8); in ast_launch_m68k()
260 ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address); in ast_launch_m68k()
261 ast_moutdwm(ast, 0x1e6e2100, 1); in ast_launch_m68k()
264 data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */ in ast_launch_m68k()
265 data |= 0x800; in ast_launch_m68k()
266 ast_moutdwm(ast, 0x1e6e2040, data); in ast_launch_m68k()
268 …jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer… in ast_launch_m68k()
269 jreg |= 0x02; in ast_launch_m68k()
270 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg); in ast_launch_m68k()
279 if (ast->config_mode == ast_use_p2a) { in ast_dp501_is_connected()
294 if (!ast->dp501_fw_buf) in ast_dp501_is_connected()
298 offset = 0x0000; in ast_dp501_is_connected()
299 data = readl(ast->dp501_fw_buf + offset); in ast_dp501_is_connected()
303 data = readl(ast->dp501_fw_buf + offset); in ast_dp501_is_connected()
309 data = readl(ast->dp501_fw_buf + offset); in ast_dp501_is_connected()
325 if (ast->config_mode == ast_use_p2a) { in ast_dp501_read_edid()
330 for (i = 0; i < 128; i += 4) { in ast_dp501_read_edid()
338 for (i = 0; i < 128; i += 4) { in ast_dp501_read_edid()
339 data = readl(ast->dp501_fw_buf + offset + i); in ast_dp501_read_edid()
353 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dvo()
354 ast_write32(ast, 0xf000, 0x1); in ast_init_dvo()
355 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_init_dvo()
357 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dvo()
358 if (!(jreg & 0x80)) { in ast_init_dvo()
360 data = ast_read32(ast, 0x12008); in ast_init_dvo()
362 data &= 0xfffff8ff; in ast_init_dvo()
363 data |= 0x00000500; in ast_init_dvo()
364 ast_write32(ast, 0x12008, data); in ast_init_dvo()
367 data = ast_read32(ast, 0x12084); in ast_init_dvo()
368 /* multi-pins for DVO single-edge */ in ast_init_dvo()
369 data |= 0xfffe0000; in ast_init_dvo()
370 ast_write32(ast, 0x12084, data); in ast_init_dvo()
372 data = ast_read32(ast, 0x12088); in ast_init_dvo()
373 /* multi-pins for DVO single-edge */ in ast_init_dvo()
374 data |= 0x000fffff; in ast_init_dvo()
375 ast_write32(ast, 0x12088, data); in ast_init_dvo()
377 data = ast_read32(ast, 0x12090); in ast_init_dvo()
378 /* multi-pins for DVO single-edge */ in ast_init_dvo()
379 data &= 0xffffffcf; in ast_init_dvo()
380 data |= 0x00000020; in ast_init_dvo()
381 ast_write32(ast, 0x12090, data); in ast_init_dvo()
383 data = ast_read32(ast, 0x12088); in ast_init_dvo()
384 /* multi-pins for DVO single-edge */ in ast_init_dvo()
385 data |= 0x30000000; in ast_init_dvo()
386 ast_write32(ast, 0x12088, data); in ast_init_dvo()
388 data = ast_read32(ast, 0x1208c); in ast_init_dvo()
389 /* multi-pins for DVO single-edge */ in ast_init_dvo()
390 data |= 0x000000cf; in ast_init_dvo()
391 ast_write32(ast, 0x1208c, data); in ast_init_dvo()
393 data = ast_read32(ast, 0x120a4); in ast_init_dvo()
394 /* multi-pins for DVO single-edge */ in ast_init_dvo()
395 data |= 0xffff0000; in ast_init_dvo()
396 ast_write32(ast, 0x120a4, data); in ast_init_dvo()
398 data = ast_read32(ast, 0x120a8); in ast_init_dvo()
399 /* multi-pins for DVO single-edge */ in ast_init_dvo()
400 data |= 0x0000000f; in ast_init_dvo()
401 ast_write32(ast, 0x120a8, data); in ast_init_dvo()
403 data = ast_read32(ast, 0x12094); in ast_init_dvo()
404 /* multi-pins for DVO single-edge */ in ast_init_dvo()
405 data |= 0x00000002; in ast_init_dvo()
406 ast_write32(ast, 0x12094, data); in ast_init_dvo()
411 data = ast_read32(ast, 0x1202c); in ast_init_dvo()
412 data &= 0xfffbffff; in ast_init_dvo()
413 ast_write32(ast, 0x1202c, data); in ast_init_dvo()
416 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); in ast_init_dvo()
428 * bridge. First configure the P2U to target the SCU in ast_init_analog()
431 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_analog()
432 ast_write32(ast, 0xf000, 0x1); in ast_init_analog()
435 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_init_analog()
436 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_init_analog()
437 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_init_analog()
440 data = ast_read32(ast, 0x1202c); in ast_init_analog()
441 data &= 0xfffcffff; in ast_init_analog()
442 ast_write32(ast, 0, data); in ast_init_analog()
445 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00); in ast_init_analog()
454 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_init_3rdtx()
455 switch (jreg & 0x0e) { in ast_init_3rdtx()
456 case 0x04: in ast_init_3rdtx()
459 case 0x08: in ast_init_3rdtx()
462 case 0x0c: in ast_init_3rdtx()
466 if (ast->tx_chip_types & BIT(AST_TX_SIL164)) in ast_init_3rdtx()