Lines Matching +full:lvds +full:- +full:4 +full:bits
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
65 #define ATOM_CRTC5 4
82 #define ATOM_PHY_PLL0 4
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
133 #define ATOM_TV_PALM 4
143 #define ATOM_DAC1_PAL 4
186 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
509 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
606 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
611 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
775 ULONG ulReserved[4];
841 // =1: LVDS encoder
844 // =4: SDVO encoder
876 #define ATOM_ENCODER_MODE_SDVO 4
911 // =1: LVDS encoder
914 // =4: SDVO encoder
958 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
963 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
969 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
993 // =1: LVDS encoder
996 // =4: SDVO encoder
1009 //ucTableContentRevision=4
1011 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1016 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
1022 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
1052 // =1: LVDS encoder
1055 // =4: SDVO encoder
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1163 // [0]=0: 4 lane Link,
1171 // [5:4]PCIE lane Sel
1173 // =1: lane 4~7
1178 UCHAR ucReserved[4];
1216 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
1292 UCHAR ucReserved[4];
1301 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1313 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1352 // Bit5:4
1366 // Structures used by UNIPHYTransmitterControlTable V1.4
1369 // ucTableContentRevision=4
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1397 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1409 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1447 // Bit5:4
1479 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI…
1480 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1500 #define ATOM_PHY_ID_UNIPHYE 4
1518 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1545 // Bit6:4
1561 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1566 …UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP…
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1797 //#define ATOM_ENCODER_MODE_SDVO 4
1835 #define MISC_DEVICE_INDEX_SHIFT 4
1848 …UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device i…
1879 // V1.4 for RoadRunner
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1928 // bit[4]= RefClock source for PPLL.
1930 // =1: other external clock source, which is pre-defined
1951 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1954 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1976 // bit[4]= RefClock source for PPLL.
1978 // =1: other external clock source, which is pre-defined
1992 …MI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4)
2025 // bit[5:4]= RefClock source for PPLL.
2046 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: D…
2047 …V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO…
2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO:…
2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO:…
2097 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE:…
2098 …_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO…
2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATI…
2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATI…
2134 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
2148 … DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
2150 …ISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
2156 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
2157 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
2203 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2220 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
2270 /****************************LVDS SS Command Table Definitions**********************/
2279 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2314 // Bits[7:4] reserved
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2339 // Bits[7:4] reserved
2392 /****************************LVDS and other encoder command table definitions *********************…
2439 // =1: Gray level 4
2515 UCHAR ucReseved[4];
2532 // bit1=0: non-coherent mode
2584 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2611 // used by both SetVoltageTable v1.3 and v1.4
2623 #define VOLTAGE_TYPE_VDDCI 4
2646 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID re…
2648 …VEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
2649 …E_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
2742 ULONG ulReserved[4];
2816 …_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2844 …o; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2857 …UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and vid…
2858 …UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and …
2860 …; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio …
2861 …scInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Conf…
2862 …AR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2868 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2884 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memc…
2885 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engc…
2906 USHORT HyperMemory_Size:4;
2926 USHORT HyperMemory_Size:4;
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3141 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3178 …PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID,…
3217 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3224 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[…
3234 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3248 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max …
3249 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min …
3251 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
3252 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the valu…
3254 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the ma…
3255 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min…
3286 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3310 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
3326 Bit[4]=1: CLMC is supported and enabled on current system.
3339 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3342 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
3345 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
3346 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
3349 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
3351 [15:8] - Lane configuration attribute;
3352 [23:16]- Connector type, possible value:
3358 [31:24]- Reserved
3366 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
3370 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
3380 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3393 … if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
3394 … if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
3395 … if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
3396 …if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (…
3409 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3414 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
3445 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This re…
3456 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3464 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3469 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3470 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3473 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3649 // [7:0] - I2C LINE Associate ID
3650 // = 0 - no I2C
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3655 // = 3-7 Reserved for future I2C engines
3656 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3663 UCHAR bfI2C_LineMux:4;
3665 UCHAR bfI2C_LineMux:4;
3761 // usModeMiscInfo-
3773 //usRefreshRate-
3947 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
3952 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3956 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3957 //Bit 6 5 4
3958 // 0 0 0 - Color bit depth is undefined
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
4003 … // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
4013 … // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
4014 // Bit7-3: Reserved
4050 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
4051 //Bit 6 5 4
4052 // 0 0 0 - Color bit depth is undefined
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4067 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set…
4072 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
4076 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4077 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
4103 #define LCD_MODE_CAP_PANEL_OFF 4
4123 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
4158 #define EXEC_SS_DELAY_SHIFT 4
4159 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
4176 //ATOM_TV_PALM 4
4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4221 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAG…
4222 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4236 … (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4237 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
4294 … ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0x…
4309 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
4318 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4368 //ucGPIO_ID pre-define id for multiple usage
4380 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; u…
4382 // Thermal interrupt output->system thermal chip GPIO pin
4399 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
4420 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
4424 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Lette…
4425 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Lette…
4429 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
4430 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
4439 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, whic…
4459 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4476 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4544 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to…
4566 #define EXT_HPDPIN_LUTINDEX_4 4
4576 #define EXT_AUXDDC_LUTINDEX_4 4
4583 //for DP connector, eDP, DP to VGA/LVDS
4586 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: fro…
4606 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4679 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4816 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
4844 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4850 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4864 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4874 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4974 #define CONNECTOR_TYPE_HDMI 4
5019 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
5117 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
5118 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
5119 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
5120 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
5122 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5123 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5124 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5181 // 14:7 - PSI0_VID
5182 // 6 - PSI0_EN
5183 // 5 - PSI1
5184 // 4:2 - load line slope trim.
5185 // 1:0 - offset trim,
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5276 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5277 UCHAR ucEfuseLength; // Efuse bits length,
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5286 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5287 UCHAR ucEfuseLength; // Efuse bits length,
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5740 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5809 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5834 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5835 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5837 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5840 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5843 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5854 Bit[1]=0: DDR-DLL shut-down feature disabled.
5855 1: DDR-DLL shut-down feature enabled.
5856 Bit[2]=0: DDR-PLL Power down feature disabled.
5857 1: DDR-PLL Power down feature enabled.
5863 … supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5869 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5876 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5882 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit…
5883 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit …
5888 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
5889 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5890 …[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower l…
5891 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5892 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
5938 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5993 ULONG ulNbpStateMemclkFreq[4];
5996 ULONG ulNbpStateNClkFreq[4];
6029 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6043 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b…
6044 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6045 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6046 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6047 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6048 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6063 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6064 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6066 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6069 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6072 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6083 Bit[1]=0: DDR-DLL shut-down feature disabled.
6084 1: DDR-DLL shut-down feature enabled.
6085 Bit[2]=0: DDR-PLL Power down feature disabled.
6086 1: DDR-PLL Power down feature enabled.
6094 … supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
6100 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
6107 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6113 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit…
6114 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit …
6119 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
6120 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6121 …[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower l…
6122 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6123 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
6125 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6128 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON…
6129 …ean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->…
6131 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( …
6132 …n use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->…
6135 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from dat…
6136 … VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY…
6139 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from var…
6140 … use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY…
6143 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIG…
6148 …LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal activ…
6153 …LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal of…
6159 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
6170 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
6220 ULONG ulNbpStateMemclkFreq[4];
6222 ULONG ulNbpStateNClkFreq[4];
6223 USHORT usNBPStateVoltage[4];
6231 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6234 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4…
6247 … bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6248 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6249 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6250 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6251 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6252 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6259 bit[4]=0: Disable DFS bypass feature
6265 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6266 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6268 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6271 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6274 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6284 Bit[1]=0: DDR-DLL shut-down feature disabled.
6285 1: DDR-DLL shut-down feature enabled.
6286 Bit[2]=0: DDR-PLL Power down feature disabled.
6287 1: DDR-PLL Power down feature enabled.
6293 … supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
6300 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
6308 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
6314 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit…
6315 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit …
6321 … Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS opti…
6322 ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory.
6323 ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.
6325 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use defa…
6326 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
6327 …[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower l…
6328 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6329 …[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parame…
6331 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
6335 …LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable sig…
6336 …ean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->…
6339 …LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brig…
6340 …n use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->…
6343 …LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCD…
6344 … VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY…
6347 …LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_…
6348 … use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY…
6351 …LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal act…
6355 …LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal activ…
6360 …LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal of…
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6368 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6369 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6370 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6388 …ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid dr…
6441 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6443 ULONG ulNbpStateNClkFreq[4];
6444 USHORT usNBPStateVoltage[4];
6457 #define EDP_VS_SINGLE_VDIFF_MODE 4
6564 ULONG ulNbpStateNClkFreq[4];
6565 USHORT usNBPStateVoltage[4];
6644 #define ASIC_INTERNAL_SS_ON_TMDS 4
6657 … //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
6676 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
6688 … //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
6713 #define ATOM_LCD_INFO_DEF 4
6772 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
7049 #define ATOM_S6_ACC_MODE_SHIFT 4
7146 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
7148 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
7149 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
7153 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
7154 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
7324 #define HDP4_INTERRUPT_ID 4
7364 #define INDIRECT_IO_PCIEP 4
7577 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7606 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
7608 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
7614 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
7615 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7616 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7633 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
7635 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
7641 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
7642 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7643 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7769 …HAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
7775 …UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7779 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7794 … ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7815 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5…
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7820 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7823 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7825 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7857 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5…
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7862 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7865 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7867 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7889 …CHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5…
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7894 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7897 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7899 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7924 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7927 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7928 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7929 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7935 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7955 …UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[…
7965 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
8006 …MemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0]…
8007 UCHAR ucReservde[4];
8109 #define SW_I2C_IO_START 4
8121 #define SW_I2C_CNTL_OPEN 4
8145 UCHAR VbeSignature[4];
8148 UCHAR Capabilities[4];
8209 UCHAR BitsPerPixel; // db ? ; bits per pixel
8217 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
8219 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
8221 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
8223 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
8229 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8230 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8431 … //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
8565 #define SELECT_DCIO_IMPCAL 4
8573 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8574 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8575 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8582 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8583 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8584 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8594 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8595 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8596 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8601 …fset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Lin…
8602 …t of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8603 … of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8604 …set of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Lin…
8605 …f PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8606 …TING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Lin…
8686 UCHAR Rsvd1d_1a[4];
8755 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8760 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8765 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8773 // [7:4] - connector type
8774 // = 1 - VGA connector
8775 // = 2 - DVI-I
8776 // = 3 - DVI-D
8777 // = 4 - DVI-A
8778 // = 5 - SVIDEO
8779 // = 6 - COMPOSITE
8780 // = 7 - LVDS
8781 // = 8 - DIGITAL LINK
8782 // = 9 - SCART
8783 // = 0xA - HDMI_type A
8784 // = 0xB - HDMI_type B
8785 // = 0xE - Special case1 (DVI+DIN)
8787 // [3:0] - DAC Associated
8788 // = 0 - no DAC
8789 // = 1 - DACA
8790 // = 2 - DACB
8791 // = 3 - External DAC
8798 UCHAR bfConnectorType:4;
8799 UCHAR bfAssociatedDAC:4;
8801 UCHAR bfAssociatedDAC:4;
8802 UCHAR bfConnectorType:4;
8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8863 #define ATOM_MAX_MISC_INFO 4
8966 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8976 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
8986 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9277 ULONG Reserved[4]; //0x3C