Lines Matching +full:2 +full:khz
59 #define ATOM_EXT_DAC 2
63 #define ATOM_CRTC3 2
78 #define ATOM_DCPLL 2
79 #define ATOM_PPLL0 2
103 #define ENCODER_REFCLK_SRC_DCPLL 2
109 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
114 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
115 #define ATOM_LCD_BLON (ATOM_ENABLE+2)
131 #define ATOM_TV_NTSCJ 2
141 #define ATOM_DAC1_CV 2
152 #define ATOM_PM_SUSPEND 2
164 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
188 #define HW_ASSISTED_I2C_STATUS_FAILURE 2
418 #define COMPUTE_ENGINE_PLL_PARAM 2
441 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
478 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
508 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
547 ULONG ulReserved[2];
585 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
647 ULONG ulReserved[2];
672 #define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
740 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
741 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit
767 UCHAR ucPadding[2];
774 UCHAR ucPadding[2];
804 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
812 USHORT usPixelClock; // in 10KHz; for bios convenient
828 USHORT usPixelClock; // in 10KHz; for bios convenient
830 // [2] Link Select:
842 // =2: DVI encoder
846 UCHAR ucReserved[2];
874 #define ATOM_ENCODER_MODE_DVI 2
882 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
883 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
889 UCHAR ucReserved1:2;
890 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
898 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
899 UCHAR ucReserved1:2;
906 USHORT usPixelClock; // in 10KHz; for bios convenient
912 // =2: DVI encoder
963 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
969 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
987 USHORT usPixelClock; // in 10KHz; for bios convenient
994 // =2: DVI encoder
1016 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
1017 UCHAR ucReserved:2;
1018 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
1020 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
1021 UCHAR ucReserved:2;
1022 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
1043 USHORT usPixelClock; // in 10KHz; for bios convenient
1053 // =2: DVI encoder
1087 ULONG ulPixelClock; // Pixel Clock in 10Khz
1090 UCHAR ucReserved[2];
1099 ULONG ulSymClock; // Symbol Clock in 10Khz
1102 UCHAR ucReserved[2];
1113 ULONG ulReserved[2];
1120 UCHAR ucReserved[2];
1121 ULONG ulReserved[2];
1158 USHORT usPixelClock; // in 10KHz; for bios convenient
1167 // [2] Link Select:
1174 // =2: lane 8~11 or 8~15
1214 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
1227 // Following are used for DigTransmitterControlTable ver1.2
1231 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1232 // =1 Dig Transmitter 2 ( Uniphy CD )
1233 // =2 Dig Transmitter 3 ( Uniphy EF )
1250 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1251 // =1 Dig Transmitter 2 ( Uniphy CD )
1252 // =2 Dig Transmitter 3 ( Uniphy EF )
1286 USHORT usPixelClock; // in 10KHz; for bios convenient
1298 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1299 // =1 Dig Transmitter 2 ( Uniphy CD )
1300 // =2 Dig Transmitter 3 ( Uniphy EF )
1301 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1313 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1314 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1315 // =1 Dig Transmitter 2 ( Uniphy CD )
1316 // =2 Dig Transmitter 3 ( Uniphy EF )
1325 USHORT usPixelClock; // in 10KHz; for bios convenient
1379 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1381 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1383 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1385 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1394 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1395 // =1 Dig Transmitter 2 ( Uniphy CD )
1396 // =2 Dig Transmitter 3 ( Uniphy EF )
1397 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1409 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1410 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1411 // =1 Dig Transmitter 2 ( Uniphy CD )
1412 // =2 Dig Transmitter 3 ( Uniphy EF )
1420 USHORT usPixelClock; // in 10KHz; for bios convenient
1465 UCHAR ucPhyClkSrcId:2;
1471 UCHAR ucPhyClkSrcId:2;
1479 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI…
1480 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1498 #define ATOM_PHY_ID_UNIPHYC 2
1516 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1537 // Bit3:2
1561 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1569 ULONG ulSymClock; // Symbol Clock in 10Khz
1570 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
1589 #define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2
1613 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1647 ULONG ulReserved[2];
1733 UCHAR ucPadding[2];
1770 UCHAR ucPadding[2];
1795 //#define ATOM_ENCODER_MODE_DVI 2
1819 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1831 //Major revision=1., Minor revision=2, add ucMiscIfno
1839 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1886 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1899 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1927 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1975 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1990 …MI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1)
2007 UCHAR ucReserved[2];
2028 // =2: GENLK
2030 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2031 UCHAR ucReserved[2];
2048 …PCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2049 …PCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2054 …ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequ…
2065 ULONG ulReserved[2];
2073 // SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above
2076 …ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, retur…
2077 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2080 …UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only…
2086 #define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called …
2099 …DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2100 …DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2106 ULONG ulReserved[2];
2137 UCHAR ucReserved[2];
2140 // usDispPllConfig v1.2 for RoadRunner
2158 UCHAR ucReserved[2];
2177 UCHAR ucPadding[2];
2186 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2195 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2218 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
2228 //2bytesPS+offsetPS
2233 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
2279 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2284 //ucTableFormatRevision=1,ucTableContentRevision=2
2313 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2338 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2376 ULONG ulTargetMemoryClock; //In 10Khz unit
2390 #define EXIT_DRAM_SELFRESH_MODE 2
2402 USHORT usPixelClock; // in 10KHz; for bios convenient
2419 //ucTableFormatRevision=1,ucTableContentRevision=2
2422 USHORT usPixelClock; // in 10KHz; for bios convenient
2438 // bit5=0: Gray level 2
2444 // =2: 50FRC_SEL pattern C
2475 UCHAR ucPadding[2];
2582 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2616 … usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2621 #define VOLTAGE_TYPE_MVDDC 2
2672 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2711 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2715 // New in GetVoltageInfo v1.2 ucVoltageMode
2733 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2765 USHORT usPixelClock; // in 10KHz; for bios convenient
2860 …UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM aud…
2861 …Info2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config…
2863 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2864 …UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical co…
2865 …UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical co…
2866 …UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical co…
2867 …UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical co…
2868 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2879 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2952 ULONG ulDefaultEngineClock; //In 10Khz unit
2953 ULONG ulDefaultMemoryClock; //In 10Khz unit
2954 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2955 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2956 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2957 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2958 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2959 ULONG ulASICMaxEngineClock; //In 10Khz unit
2960 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2964 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2965 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2966 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2967 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2968 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2969 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2970 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2971 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2972 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2973 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above…
2975 USHORT usReferenceClock; //In 10Khz unit
2986 ULONG ulDefaultEngineClock; //In 10Khz unit
2987 ULONG ulDefaultMemoryClock; //In 10Khz unit
2988 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2989 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2990 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2991 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2992 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2993 ULONG ulASICMaxEngineClock; //In 10Khz unit
2994 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2997 UCHAR ucPadding[2]; //Don't use them
2998 ULONG aulReservedForBIOS[2]; //Don't use them
2999 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3000 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3001 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3002 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3003 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3004 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3005 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3006 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3007 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3008 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3011 USHORT usReferenceClock; //In 10Khz unit
3022 ULONG ulDefaultEngineClock; //In 10Khz unit
3023 ULONG ulDefaultMemoryClock; //In 10Khz unit
3024 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3025 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3026 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3027 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3028 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3029 ULONG ulASICMaxEngineClock; //In 10Khz unit
3030 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3033 UCHAR ucPadding[2]; //Don't use them
3035 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3036 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3037 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3038 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3039 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3040 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3041 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3042 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3043 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3044 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3045 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3048 USHORT usReferenceClock; //In 10Khz unit
3059 ULONG ulDefaultEngineClock; //In 10Khz unit
3060 ULONG ulDefaultMemoryClock; //In 10Khz unit
3061 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3062 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3063 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3064 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3065 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3066 ULONG ulASICMaxEngineClock; //In 10Khz unit
3067 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3073 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3074 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3075 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3076 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3077 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3078 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3079 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3080 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3081 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3082 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3083 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3086 USHORT usReferenceClock; //In 10Khz unit
3098 ULONG ulDefaultEngineClock; //In 10Khz unit
3099 ULONG ulDefaultMemoryClock; //In 10Khz unit
3102 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3103 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3104 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3106 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3113 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3114 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3115 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3116 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3117 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3118 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3119 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3120 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3121 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3122 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3125 USHORT usCoreReferenceClock; //In 10Khz unit
3126 USHORT usMemoryReferenceClock; //In 10Khz unit
3127 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
3134 //ucTableFormatRevision=2
3135 //ucTableContentRevision=2
3139 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3140 UCHAR ucReserved:2; // Bit[3:2] Reserved
3148 ULONG ulDefaultEngineClock; //In 10Khz unit
3149 ULONG ulDefaultMemoryClock; //In 10Khz unit
3150 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3151 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3152 … ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3153 … ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3154 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3156 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
3163 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3168 …USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz uni…
3169 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3170 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3173 USHORT usCoreReferenceClock; //In 10Khz unit
3174 USHORT usMemoryReferenceClock; //In 10Khz unit
3175 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
3178 … ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved…
3203 ULONG ulBootUpEngineClock; //in 10kHz unit
3204 ULONG ulBootUpMemoryClock; //in 10kHz unit
3205 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3206 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3212 ULONG ulReserved[2];
3216 … //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
3217 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3224 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[…
3275 ULONG ulBootUpEngineClock; //in 10kHz unit
3276 ULONG ulReserved1[2]; //must be 0x0 for the reserved
3277 ULONG ulBootUpUMAClock; //in 10kHz unit
3278 ULONG ulBootUpSidePortClock; //in 10kHz unit
3279 ULONG ulMinSidePortClock; //in 10kHz unit
3286 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3296 ULONG ulHTLinkFreq; //in 10Khz
3303 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3304 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3323 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
3345 … the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1…
3349 …ith PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
3370 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
3383 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
3412 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
3449 ULONG ulBootUpEngineClock; //in 10kHz unit
3450 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
3451 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
3452 ULONG ulBootUpUMAClock; //in 10kHz unit
3470 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3536 #define ATOM_DP_ENCODER 2
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3654 // = 2, HW engine for Multimedia use
3787 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3855 USHORT usPixelClock; //in 10Khz unit
3917 //ucTableContentRevision=2
3938 UCHAR ucReserved[2];
4002 // Bit3:2: {Grey level}
4036 ULONG ulReserved[2];
4045 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
4102 #define LCD_MODE_CAP_CRTC_OFF 2
4121 #define LCD_RTS_RECORD_TYPE 2
4131 //ucTableContentRevision=2
4157 #define EXEC_SS_STEP_SIZE_SHIFT 2
4174 //ATOM_TV_NTSCJ 2
4193 #define MAX_SUPPORTED_TV_TIMING 2
4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4321 if (FB_Size<=2Gb)
4464 //ucTableFormatRevision=2
4525 …USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encode…
4532 UCHAR ucPadding[2];
4564 #define EXT_HPDPIN_LUTINDEX_2 2
4574 #define EXT_AUXDDC_LUTINDEX_2 2
4584 … DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4585 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: fro…
4586 … DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4587 … DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4591 UCHAR ucDP_Lane3_Source:2;
4592 UCHAR ucDP_Lane2_Source:2;
4593 UCHAR ucDP_Lane1_Source:2;
4594 UCHAR ucDP_Lane0_Source:2;
4596 UCHAR ucDP_Lane0_Source:2;
4597 UCHAR ucDP_Lane1_Source:2;
4598 UCHAR ucDP_Lane2_Source:2;
4599 UCHAR ucDP_Lane3_Source:2;
4604 …I connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
4606 …I connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4607 …I connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =…
4611 UCHAR ucDVI_CLK_Source:2;
4612 UCHAR ucDVI_DATA0_Source:2;
4613 UCHAR ucDVI_DATA1_Source:2;
4614 UCHAR ucDVI_DATA2_Source:2;
4616 UCHAR ucDVI_DATA2_Source:2;
4617 UCHAR ucDVI_DATA1_Source:2;
4618 UCHAR ucDVI_DATA0_Source:2;
4619 UCHAR ucDVI_CLK_Source:2;
4648 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip
4649 #define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4677 #define ATOM_HPD_INT_RECORD_TYPE 2
4780 UCHAR ucPadding[2];
4814 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
4827 UCHAR ucPadding[2];
4831 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW…
4833 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualifi…
4845 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4846 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4848 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4849 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4867 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4868 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4871 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4883 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
4914 UCHAR ucMuxState[2]; //for alligment purpose
4922 UCHAR ucMuxState[2]; //for alligment purpose
4972 #define CONNECTOR_TYPE_DVI_I 2
5172 UCHAR ucReserved[2];
5184 // 4:2 - load line slope trim.
5241 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
5247 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
5263 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5267 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5279 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5527 …ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." un…
5528 …ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="1…
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5627 UCHAR ucPostdiv; // divide by 2^n
5713 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5720 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5725 …upportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5809 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5810 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5811 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5840 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5851 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5856 Bit[2]=0: DDR-PLL Power down feature disabled.
5869 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5876 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5877 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5907 ULONG uReserved:2;
5910 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5912 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5915 ULONG uReserved:2;
6029 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
6030 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6031 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6047 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6069 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6080 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
6085 Bit[2]=0: DDR-PLL Power down feature disabled.
6100 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
6107 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
6108 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6159 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
6231 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
6232 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6233 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6251 … bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6256 ulGPUCapInfo: bit[0~2]= Reserved
6271 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6286 Bit[2]=0: DDR-PLL Power down feature disabled.
6300 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
6308 …eed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
6321 … Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS op…
6367 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6410 ULONG ulReserved[2];
6441 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6455 #define EDP_VS_HIGH_VDIFF_MODE 2
6485 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
6561 ULONG ulNbpStateMemclkFreq[2];
6562 ULONG ulReserved7[2];
6596 #define ICS91720 2
6631 … ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6633 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
6636 UCHAR ucReserved[2];
6642 #define ASIC_INTERNAL_ENGINE_SS 2
6656 …rgetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6662 UCHAR ucReserved[2];
6687 …rgetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6693 UCHAR ucReserved[2];
6711 #define ATOM_TV_STANDARD_DEF 2
6770 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
6811 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2
7047 #define ATOM_S6_LID_CHANGE_SHIFT 2
7171 ULONG ulTargetMemoryClock; //In 10Khz unit
7204 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2
7226 UCHAR ucSurface; // Surface 1 or 2
7234 UCHAR ucSurface; // Surface 1 or 2
7236 UCHAR ucPadding[2];
7243 UCHAR ucSurface; // Surface 1 or 2
7255 UCHAR ucSurface; // Surface 1 or 2
7308 #define PALETTE_DATA_READ 2
7322 #define HDP2_INTERRUPT_ID 2
7331 #define INTERRUPT_SERVICE_GET_STATUS 2
7335 #define INTERRUPT_STATUS__HPD_HIGH 2
7362 #define INDIRECT_IO_MC 2
7609 UCHAR ucRow; // Number of Row,in power of 2;
7610 UCHAR ucColumn; // Number of Column,in power of 2;
7612 UCHAR ucRank; // Number of Rank, in power of 2
7614 …elConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7617 UCHAR ucReserved[2];
7636 UCHAR ucRow; // Number of Row,in power of 2;
7637 UCHAR ucColumn; // Number of Column,in power of 2;
7639 UCHAR ucRank; // Number of Rank, in power of 2
7641 …elConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7651 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory…
7687 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memor…
7723 …ULONG ulClkRange; // memory clock in 10kHz unit, when …
7771 UCHAR ucRow; // Number of Row,in power of 2;
7772 UCHAR ucColumn; // Number of Column,in power of 2;
7774 UCHAR ucRank; // Number of Rank, in power of 2
7839 UCHAR ucReserved2[2];
7927 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7955 … ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=…
8005 … // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
8006 … // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... D…
8107 #define SW_I2C_IO_DRIVE 2
8119 #define SW_I2C_CNTL_START 2
8304 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
8365 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
8383 UCHAR ucReserved[2];
8394 CLOCK_SRC_XO_IN2=2,
8431 …UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
8449 UCHAR ucReserved[2];
8465 UCHAR ucReserved[2];
8540 #define ATOM_FEATURE_SUPPORTED 2
8552 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
8563 #define SELECT_DCIO_UNIPHY_LINK0 2
8676 #define GFX_HARVESTING_PRIM_ID 2
8680 UCHAR PciRomSignature[2];
8737 USHORT usMaxFrequency; // in 10kHz unit
8775 // = 2 - DVI-I
8790 // = 2 - DACB
8868 USHORT usMaxFrequency; // in 10Khz
8909 #define ATOM_XTMDS_ASIC_SI178_ID 2
8933 UCHAR ucPadding[2];
8966 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8976 …OWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Bala…
9008 //ucTableFormatRevision=2
9023 //ucTableFormatRevision=2
9024 //ucTableContentRevision=2
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )