Lines Matching +full:3 +full:base +full:- +full:x
38 #include "atom-names.h"
39 #include "atom-bits.h"
45 #define ATOM_COND_BELOW 3
58 #define PLL_DATA 3
84 {1, 2, 3, 0},
85 {1, 2, 3, 0},
86 {1, 2, 3, 0},
92 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
98 while (n--) in debug_print_spaces()
109 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, in atom_iio_execute() argument
115 switch (CU8(base)) { in atom_iio_execute()
117 base++; in atom_iio_execute()
120 temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); in atom_iio_execute()
121 base += 3; in atom_iio_execute()
124 ctx->card->reg_write(ctx->card, CU16(base + 1), temp); in atom_iio_execute()
125 base += 3; in atom_iio_execute()
129 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << in atom_iio_execute()
130 CU8(base + 2)); in atom_iio_execute()
131 base += 3; in atom_iio_execute()
135 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + in atom_iio_execute()
137 base += 3; in atom_iio_execute()
141 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << in atom_iio_execute()
142 CU8(base + 3)); in atom_iio_execute()
144 ((index >> CU8(base + 2)) & in atom_iio_execute()
145 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + in atom_iio_execute()
146 3); in atom_iio_execute()
147 base += 4; in atom_iio_execute()
151 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << in atom_iio_execute()
152 CU8(base + 3)); in atom_iio_execute()
154 ((data >> CU8(base + 2)) & in atom_iio_execute()
155 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + in atom_iio_execute()
156 3); in atom_iio_execute()
157 base += 4; in atom_iio_execute()
161 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << in atom_iio_execute()
162 CU8(base + 3)); in atom_iio_execute()
164 ((ctx-> in atom_iio_execute()
165 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - in atom_iio_execute()
167 (base in atom_iio_execute()
170 << CU8(base + 3); in atom_iio_execute()
171 base += 4; in atom_iio_execute()
185 struct atom_context *gctx = ctx->ctx; in atom_get_src_int()
187 align = (attr >> 3) & 7; in atom_get_src_int()
193 DEBUG("REG[0x%04X]", idx); in atom_get_src_int()
194 idx += gctx->reg_block; in atom_get_src_int()
195 switch (gctx->io_mode) { in atom_get_src_int()
197 val = gctx->card->reg_read(gctx->card, idx); in atom_get_src_int()
206 if (!(gctx->io_mode & 0x80)) { in atom_get_src_int()
210 if (!gctx->iio[gctx->io_mode & 0x7F]) { in atom_get_src_int()
212 gctx->io_mode & 0x7F); in atom_get_src_int()
217 gctx->iio[gctx->io_mode & 0x7F], in atom_get_src_int()
226 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); in atom_get_src_int()
228 DEBUG("PS[0x%02X,0x%04X]", idx, val); in atom_get_src_int()
234 DEBUG("WS[0x%02X]", idx); in atom_get_src_int()
237 val = gctx->divmul[0]; in atom_get_src_int()
240 val = gctx->divmul[1]; in atom_get_src_int()
243 val = gctx->data_block; in atom_get_src_int()
246 val = gctx->shift; in atom_get_src_int()
249 val = 1 << gctx->shift; in atom_get_src_int()
252 val = ~(1 << gctx->shift); in atom_get_src_int()
255 val = gctx->fb_base; in atom_get_src_int()
258 val = gctx->io_attr; in atom_get_src_int()
261 val = gctx->reg_block; in atom_get_src_int()
264 val = ctx->ws[idx]; in atom_get_src_int()
271 if (gctx->data_block) in atom_get_src_int()
272 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); in atom_get_src_int()
274 DEBUG("ID[0x%04X]", idx); in atom_get_src_int()
276 val = U32(idx + gctx->data_block); in atom_get_src_int()
281 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { in atom_get_src_int()
283 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); in atom_get_src_int()
286 val = gctx->scratch[(gctx->fb_base / 4) + idx]; in atom_get_src_int()
288 DEBUG("FB[0x%02X]", idx); in atom_get_src_int()
296 DEBUG("IMM 0x%08X\n", val); in atom_get_src_int()
304 DEBUG("IMM 0x%04X\n", val); in atom_get_src_int()
313 DEBUG("IMM 0x%02X\n", val); in atom_get_src_int()
321 DEBUG("PLL[0x%02X]", idx); in atom_get_src_int()
322 val = gctx->card->pll_read(gctx->card, idx); in atom_get_src_int()
328 DEBUG("MC[0x%02X]", idx); in atom_get_src_int()
329 val = gctx->card->mc_read(gctx->card, idx); in atom_get_src_int()
339 DEBUG(".[31:0] -> 0x%08X\n", val); in atom_get_src_int()
342 DEBUG(".[15:0] -> 0x%04X\n", val); in atom_get_src_int()
345 DEBUG(".[23:8] -> 0x%04X\n", val); in atom_get_src_int()
348 DEBUG(".[31:16] -> 0x%04X\n", val); in atom_get_src_int()
351 DEBUG(".[7:0] -> 0x%02X\n", val); in atom_get_src_int()
354 DEBUG(".[15:8] -> 0x%02X\n", val); in atom_get_src_int()
357 DEBUG(".[23:16] -> 0x%02X\n", val); in atom_get_src_int()
360 DEBUG(".[31:24] -> 0x%02X\n", val); in atom_get_src_int()
368 uint32_t align = (attr >> 3) & 7, arg = attr & 7; in atom_skip_src_int()
437 arg | atom_dst_to_src[(attr >> 3) & in atom_get_dst()
438 7][(attr >> 6) & 3] << 3, in atom_get_dst()
445 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & in atom_skip_dst()
446 3] << 3, ptr); in atom_skip_dst()
453 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = in atom_put_dst()
455 struct atom_context *gctx = ctx->ctx; in atom_put_dst()
465 DEBUG("REG[0x%04X]", idx); in atom_put_dst()
466 idx += gctx->reg_block; in atom_put_dst()
467 switch (gctx->io_mode) { in atom_put_dst()
470 gctx->card->reg_write(gctx->card, idx, in atom_put_dst()
473 gctx->card->reg_write(gctx->card, idx, val); in atom_put_dst()
482 if (!(gctx->io_mode & 0x80)) { in atom_put_dst()
486 if (!gctx->iio[gctx->io_mode & 0xFF]) { in atom_put_dst()
488 gctx->io_mode & 0x7F); in atom_put_dst()
491 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], in atom_put_dst()
498 DEBUG("PS[0x%02X]", idx); in atom_put_dst()
499 ctx->ps[idx] = cpu_to_le32(val); in atom_put_dst()
504 DEBUG("WS[0x%02X]", idx); in atom_put_dst()
507 gctx->divmul[0] = val; in atom_put_dst()
510 gctx->divmul[1] = val; in atom_put_dst()
513 gctx->data_block = val; in atom_put_dst()
516 gctx->shift = val; in atom_put_dst()
522 gctx->fb_base = val; in atom_put_dst()
525 gctx->io_attr = val; in atom_put_dst()
528 gctx->reg_block = val; in atom_put_dst()
531 ctx->ws[idx] = val; in atom_put_dst()
537 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { in atom_put_dst()
539 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); in atom_put_dst()
541 gctx->scratch[(gctx->fb_base / 4) + idx] = val; in atom_put_dst()
542 DEBUG("FB[0x%02X]", idx); in atom_put_dst()
547 DEBUG("PLL[0x%02X]", idx); in atom_put_dst()
548 gctx->card->pll_write(gctx->card, idx, val); in atom_put_dst()
553 DEBUG("MC[0x%02X]", idx); in atom_put_dst()
554 gctx->card->mc_write(gctx->card, idx, val); in atom_put_dst()
559 DEBUG(".[31:0] <- 0x%08X\n", old_val); in atom_put_dst()
562 DEBUG(".[15:0] <- 0x%04X\n", old_val); in atom_put_dst()
565 DEBUG(".[23:8] <- 0x%04X\n", old_val); in atom_put_dst()
568 DEBUG(".[31:16] <- 0x%04X\n", old_val); in atom_put_dst()
571 DEBUG(".[7:0] <- 0x%02X\n", old_val); in atom_put_dst()
574 DEBUG(".[15:8] <- 0x%02X\n", old_val); in atom_put_dst()
577 DEBUG(".[23:16] <- 0x%02X\n", old_val); in atom_put_dst()
580 DEBUG(".[31:24] <- 0x%02X\n", old_val); in atom_put_dst()
627 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) in atom_op_calltable()
628 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); in atom_op_calltable()
630 ctx->abort = true; in atom_op_calltable()
640 attr |= atom_def_dst[attr >> 3] << 6; in atom_op_clear()
654 ctx->ctx->cs_equal = (dst == src); in atom_op_compare()
655 ctx->ctx->cs_above = (dst > src); in atom_op_compare()
656 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", in atom_op_compare()
657 ctx->ctx->cs_above ? "GT" : "LE"); in atom_op_compare()
681 ctx->ctx->divmul[0] = dst / src; in atom_op_div()
682 ctx->ctx->divmul[1] = dst % src; in atom_op_div()
684 ctx->ctx->divmul[0] = 0; in atom_op_div()
685 ctx->ctx->divmul[1] = 0; in atom_op_div()
700 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; in atom_op_div32()
702 ctx->ctx->divmul[0] = lower_32_bits(val64); in atom_op_div32()
703 ctx->ctx->divmul[1] = upper_32_bits(val64); in atom_op_div32()
705 ctx->ctx->divmul[0] = 0; in atom_op_div32()
706 ctx->ctx->divmul[1] = 0; in atom_op_div32()
723 execute = ctx->ctx->cs_above; in atom_op_jump()
726 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; in atom_op_jump()
732 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); in atom_op_jump()
735 execute = !ctx->ctx->cs_above; in atom_op_jump()
738 execute = ctx->ctx->cs_equal; in atom_op_jump()
741 execute = !ctx->ctx->cs_equal; in atom_op_jump()
746 SDEBUG(" target: 0x%04X\n", target); in atom_op_jump()
748 if (ctx->last_jump == (ctx->start + target)) { in atom_op_jump()
750 if (time_after(cjiffies, ctx->last_jump_jiffies)) { in atom_op_jump()
751 cjiffies -= ctx->last_jump_jiffies; in atom_op_jump()
755 ctx->abort = true; in atom_op_jump()
759 ctx->last_jump_jiffies = jiffies; in atom_op_jump()
762 ctx->last_jump = ctx->start + target; in atom_op_jump()
763 ctx->last_jump_jiffies = jiffies; in atom_op_jump()
765 *ptr = ctx->start + target; in atom_op_jump()
776 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); in atom_op_mask()
777 SDEBUG(" mask: 0x%08x", mask); in atom_op_mask()
791 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) in atom_op_move()
811 ctx->ctx->divmul[0] = dst * src; in atom_op_mul()
824 ctx->ctx->divmul[0] = lower_32_bits(val64); in atom_op_mul32()
825 ctx->ctx->divmul[1] = upper_32_bits(val64); in atom_op_mul32()
850 SDEBUG("POST card output: 0x%02X\n", val); in atom_op_postcard()
874 ctx->ctx->data_block = 0; in atom_op_setdatablock()
876 ctx->ctx->data_block = ctx->start; in atom_op_setdatablock()
878 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); in atom_op_setdatablock()
879 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); in atom_op_setdatablock()
886 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); in atom_op_setfbbase()
900 ctx->ctx->io_mode = ATOM_IO_MM; in atom_op_setport()
902 ctx->ctx->io_mode = ATOM_IO_IIO | port; in atom_op_setport()
906 ctx->ctx->io_mode = ATOM_IO_PCI; in atom_op_setport()
910 ctx->ctx->io_mode = ATOM_IO_SYSIO; in atom_op_setport()
918 ctx->ctx->reg_block = U16(*ptr); in atom_op_setregblock()
920 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); in atom_op_setregblock()
929 attr |= atom_def_dst[attr >> 3] << 6; in atom_op_shift_left()
945 attr |= atom_def_dst[attr >> 3] << 6; in atom_op_shift_right()
960 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; in atom_op_shl()
979 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; in atom_op_shr()
1002 dst -= src; in atom_op_sub()
1022 SDEBUG(" target: %04X\n", target); in atom_op_switch()
1023 *ptr = ctx->start + target; in atom_op_switch()
1042 ctx->ctx->cs_equal = ((dst & src) == 0); in atom_op_test()
1043 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); in atom_op_test()
1063 SDEBUG("DEBUG output: 0x%02X\n", val); in atom_op_debug()
1070 SDEBUG("PROCESSDS output: 0x%02X\n", val); in atom_op_processds()
1209 int base = CU16(ctx->cmd_table + 4 + 2 * index); in amdgpu_atom_execute_table_locked() local
1215 if (!base) in amdgpu_atom_execute_table_locked()
1216 return -EINVAL; in amdgpu_atom_execute_table_locked()
1218 len = CU16(base + ATOM_CT_SIZE_PTR); in amdgpu_atom_execute_table_locked()
1219 ws = CU8(base + ATOM_CT_WS_PTR); in amdgpu_atom_execute_table_locked()
1220 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; in amdgpu_atom_execute_table_locked()
1221 ptr = base + ATOM_CT_CODE_PTR; in amdgpu_atom_execute_table_locked()
1223 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); in amdgpu_atom_execute_table_locked()
1227 ectx.start = base; in amdgpu_atom_execute_table_locked()
1240 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); in amdgpu_atom_execute_table_locked()
1242 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); in amdgpu_atom_execute_table_locked()
1244 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", in amdgpu_atom_execute_table_locked()
1245 base, len, ws, ps, ptr - 1); in amdgpu_atom_execute_table_locked()
1246 ret = -EINVAL; in amdgpu_atom_execute_table_locked()
1259 debug_depth--; in amdgpu_atom_execute_table_locked()
1272 mutex_lock(&ctx->mutex); in amdgpu_atom_execute_table()
1274 ctx->data_block = 0; in amdgpu_atom_execute_table()
1276 ctx->reg_block = 0; in amdgpu_atom_execute_table()
1278 ctx->fb_base = 0; in amdgpu_atom_execute_table()
1280 ctx->io_mode = ATOM_IO_MM; in amdgpu_atom_execute_table()
1282 ctx->divmul[0] = 0; in amdgpu_atom_execute_table()
1283 ctx->divmul[1] = 0; in amdgpu_atom_execute_table()
1285 mutex_unlock(&ctx->mutex); in amdgpu_atom_execute_table()
1289 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1291 static void atom_index_iio(struct atom_context *ctx, int base) in atom_index_iio() argument
1293 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); in atom_index_iio()
1294 if (!ctx->iio) in atom_index_iio()
1296 while (CU8(base) == ATOM_IIO_START) { in atom_index_iio()
1297 ctx->iio[CU8(base + 1)] = base + 2; in atom_index_iio()
1298 base += 2; in atom_index_iio()
1299 while (CU8(base) != ATOM_IIO_END) in atom_index_iio()
1300 base += atom_iio_len[CU8(base)]; in atom_index_iio()
1301 base += 3; in atom_index_iio()
1314 const char *na = "--N/A--"; in atom_get_vbios_name()
1317 p_rom = ctx->bios; in atom_get_vbios_name()
1327 memcpy(ctx->name, na, 7); in atom_get_vbios_name()
1328 ctx->name[7] = 0; in atom_get_vbios_name()
1334 * 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type in atom_get_vbios_name()
1345 name_size = strnlen(c_ptr, STRLEN_LONG - 1); in atom_get_vbios_name()
1346 memcpy(ctx->name, c_ptr, name_size); in atom_get_vbios_name()
1347 back = ctx->name + name_size; in atom_get_vbios_name()
1348 while ((*--back) == ' ') in atom_get_vbios_name()
1358 p_rom = ctx->bios; in atom_get_vbios_date()
1362 ctx->date[0] = '2'; in atom_get_vbios_date()
1363 ctx->date[1] = '0'; in atom_get_vbios_date()
1364 ctx->date[2] = date_in_rom[6]; in atom_get_vbios_date()
1365 ctx->date[3] = date_in_rom[7]; in atom_get_vbios_date()
1366 ctx->date[4] = '/'; in atom_get_vbios_date()
1367 ctx->date[5] = date_in_rom[0]; in atom_get_vbios_date()
1368 ctx->date[6] = date_in_rom[1]; in atom_get_vbios_date()
1369 ctx->date[7] = '/'; in atom_get_vbios_date()
1370 ctx->date[8] = date_in_rom[3]; in atom_get_vbios_date()
1371 ctx->date[9] = date_in_rom[4]; in atom_get_vbios_date()
1372 ctx->date[10] = ' '; in atom_get_vbios_date()
1373 ctx->date[11] = date_in_rom[9]; in atom_get_vbios_date()
1374 ctx->date[12] = date_in_rom[10]; in atom_get_vbios_date()
1375 ctx->date[13] = date_in_rom[11]; in atom_get_vbios_date()
1376 ctx->date[14] = date_in_rom[12]; in atom_get_vbios_date()
1377 ctx->date[15] = date_in_rom[13]; in atom_get_vbios_date()
1378 ctx->date[16] = '\0'; in atom_get_vbios_date()
1390 p_rom = ctx->bios; in atom_find_str_in_rom()
1412 p_rom = ctx->bios; in atom_get_vbios_pn()
1424 vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64); in atom_get_vbios_pn()
1426 vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1; in atom_get_vbios_pn()
1435 ctx->vbios_pn[count] = vbios_str[count]; in atom_get_vbios_pn()
1439 ctx->vbios_pn[count] = 0; in atom_get_vbios_pn()
1442 pr_info("ATOM BIOS: %s\n", ctx->vbios_pn); in atom_get_vbios_pn()
1449 /* find anchor ATOMBIOSBK-AMD */ in atom_get_vbios_version()
1450 vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64); in atom_get_vbios_version()
1452 /* skip ATOMBIOSBK-AMD VER */ in atom_get_vbios_version()
1454 memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL); in atom_get_vbios_version()
1456 ctx->vbios_ver_str[0] = '\0'; in atom_get_vbios_version()
1462 int base; in amdgpu_atom_parse() local
1472 ctx->card = card; in amdgpu_atom_parse()
1473 ctx->bios = bios; in amdgpu_atom_parse()
1488 base = CU16(ATOM_ROM_TABLE_PTR); in amdgpu_atom_parse()
1490 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, in amdgpu_atom_parse()
1497 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); in amdgpu_atom_parse()
1498 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); in amdgpu_atom_parse()
1499 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); in amdgpu_atom_parse()
1500 if (!ctx->iio) { in amdgpu_atom_parse()
1505 atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base); in amdgpu_atom_parse()
1506 if (atom_rom_header->usMasterDataTableOffset != 0) { in amdgpu_atom_parse()
1508 CSTR(atom_rom_header->usMasterDataTableOffset); in amdgpu_atom_parse()
1509 if (master_table->ListOfDataTables.FirmwareInfo != 0) { in amdgpu_atom_parse()
1511 CSTR(master_table->ListOfDataTables.FirmwareInfo); in amdgpu_atom_parse()
1512 ctx->version = atom_fw_info->ulFirmwareRevision; in amdgpu_atom_parse()
1526 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); in amdgpu_atom_asic_init()
1537 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) in amdgpu_atom_asic_init()
1550 kfree(ctx->iio); in amdgpu_atom_destroy()
1559 int idx = CU16(ctx->data_table + offset); in amdgpu_atom_parse_data_header()
1560 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); in amdgpu_atom_parse_data_header()
1570 *crev = CU8(idx + 3); in amdgpu_atom_parse_data_header()
1579 int idx = CU16(ctx->cmd_table + offset); in amdgpu_atom_parse_cmd_header()
1580 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); in amdgpu_atom_parse_cmd_header()
1588 *crev = CU8(idx + 3); in amdgpu_atom_parse_cmd_header()