Lines Matching refs:bank
78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
136 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_mask() argument
139 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, in omap_set_gpio_dataout_mask()
143 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) in omap_gpio_dbck_enable() argument
145 if (bank->dbck_enable_mask && !bank->dbck_enabled) { in omap_gpio_dbck_enable()
146 clk_enable(bank->dbck); in omap_gpio_dbck_enable()
147 bank->dbck_enabled = true; in omap_gpio_dbck_enable()
149 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable()
150 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable()
154 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) in omap_gpio_dbck_disable() argument
156 if (bank->dbck_enable_mask && bank->dbck_enabled) { in omap_gpio_dbck_disable()
162 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
164 clk_disable(bank->dbck); in omap_gpio_dbck_disable()
165 bank->dbck_enabled = false; in omap_gpio_dbck_disable()
181 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, in omap2_set_gpio_debounce() argument
188 if (!bank->dbck_flag) in omap2_set_gpio_debounce()
199 clk_enable(bank->dbck); in omap2_set_gpio_debounce()
200 writel_relaxed(debounce, bank->base + bank->regs->debounce); in omap2_set_gpio_debounce()
202 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); in omap2_set_gpio_debounce()
203 bank->dbck_enable_mask = val; in omap2_set_gpio_debounce()
205 clk_disable(bank->dbck); in omap2_set_gpio_debounce()
214 omap_gpio_dbck_enable(bank); in omap2_set_gpio_debounce()
215 if (bank->dbck_enable_mask) { in omap2_set_gpio_debounce()
216 bank->context.debounce = debounce; in omap2_set_gpio_debounce()
217 bank->context.debounce_en = val; in omap2_set_gpio_debounce()
233 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) in omap_clear_gpio_debounce() argument
237 if (!bank->dbck_flag) in omap_clear_gpio_debounce()
240 if (!(bank->dbck_enable_mask & gpio_bit)) in omap_clear_gpio_debounce()
243 bank->dbck_enable_mask &= ~gpio_bit; in omap_clear_gpio_debounce()
244 bank->context.debounce_en &= ~gpio_bit; in omap_clear_gpio_debounce()
245 writel_relaxed(bank->context.debounce_en, in omap_clear_gpio_debounce()
246 bank->base + bank->regs->debounce_en); in omap_clear_gpio_debounce()
248 if (!bank->dbck_enable_mask) { in omap_clear_gpio_debounce()
249 bank->context.debounce = 0; in omap_clear_gpio_debounce()
250 writel_relaxed(bank->context.debounce, bank->base + in omap_clear_gpio_debounce()
251 bank->regs->debounce); in omap_clear_gpio_debounce()
252 clk_disable(bank->dbck); in omap_clear_gpio_debounce()
253 bank->dbck_enabled = false; in omap_clear_gpio_debounce()
263 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) in omap_gpio_is_off_wakeup_capable() argument
265 u32 no_wake = bank->non_wakeup_gpios; in omap_gpio_is_off_wakeup_capable()
273 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, in omap_set_gpio_trigger() argument
276 void __iomem *base = bank->base; in omap_set_gpio_trigger()
279 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, in omap_set_gpio_trigger()
281 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, in omap_set_gpio_trigger()
289 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, in omap_set_gpio_trigger()
291 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, in omap_set_gpio_trigger()
294 bank->context.leveldetect0 = in omap_set_gpio_trigger()
295 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
296 bank->context.leveldetect1 = in omap_set_gpio_trigger()
297 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
298 bank->context.risingdetect = in omap_set_gpio_trigger()
299 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
300 bank->context.fallingdetect = in omap_set_gpio_trigger()
301 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
303 bank->level_mask = bank->context.leveldetect0 | in omap_set_gpio_trigger()
304 bank->context.leveldetect1; in omap_set_gpio_trigger()
307 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { in omap_set_gpio_trigger()
315 bank->enabled_non_wakeup_gpios |= gpio_bit; in omap_set_gpio_trigger()
317 bank->enabled_non_wakeup_gpios &= ~gpio_bit; in omap_set_gpio_trigger()
325 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) in omap_toggle_gpio_edge_triggering() argument
327 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { in omap_toggle_gpio_edge_triggering()
328 void __iomem *reg = bank->base + bank->regs->irqctrl; in omap_toggle_gpio_edge_triggering()
334 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, in omap_set_gpio_triggering() argument
337 void __iomem *reg = bank->base; in omap_set_gpio_triggering()
340 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { in omap_set_gpio_triggering()
341 omap_set_gpio_trigger(bank, gpio, trigger); in omap_set_gpio_triggering()
342 } else if (bank->regs->irqctrl) { in omap_set_gpio_triggering()
343 reg += bank->regs->irqctrl; in omap_set_gpio_triggering()
347 bank->toggle_mask |= BIT(gpio); in omap_set_gpio_triggering()
356 } else if (bank->regs->edgectrl1) { in omap_set_gpio_triggering()
358 reg += bank->regs->edgectrl2; in omap_set_gpio_triggering()
360 reg += bank->regs->edgectrl1; in omap_set_gpio_triggering()
374 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) in omap_enable_gpio_module() argument
376 if (bank->regs->pinctrl) { in omap_enable_gpio_module()
377 void __iomem *reg = bank->base + bank->regs->pinctrl; in omap_enable_gpio_module()
383 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_enable_gpio_module()
384 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_enable_gpio_module()
391 bank->context.ctrl = ctrl; in omap_enable_gpio_module()
395 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) in omap_disable_gpio_module() argument
397 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_disable_gpio_module()
398 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_disable_gpio_module()
405 bank->context.ctrl = ctrl; in omap_disable_gpio_module()
409 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) in omap_gpio_is_input() argument
411 void __iomem *reg = bank->base + bank->regs->direction; in omap_gpio_is_input()
416 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) in omap_gpio_init_irq() argument
418 if (!LINE_USED(bank->mod_usage, offset)) { in omap_gpio_init_irq()
419 omap_enable_gpio_module(bank, offset); in omap_gpio_init_irq()
420 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_init_irq()
422 bank->irq_usage |= BIT(offset); in omap_gpio_init_irq()
427 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_type() local
435 if (!bank->regs->leveldetect0 && in omap_gpio_irq_type()
439 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_type()
440 retval = omap_set_gpio_triggering(bank, offset, type); in omap_gpio_irq_type()
442 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
445 omap_gpio_init_irq(bank, offset); in omap_gpio_irq_type()
446 if (!omap_gpio_is_input(bank, offset)) { in omap_gpio_irq_type()
447 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
451 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
470 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) in omap_clear_gpio_irqbank() argument
472 void __iomem *reg = bank->base; in omap_clear_gpio_irqbank()
474 reg += bank->regs->irqstatus; in omap_clear_gpio_irqbank()
478 if (bank->regs->irqstatus2) { in omap_clear_gpio_irqbank()
479 reg = bank->base + bank->regs->irqstatus2; in omap_clear_gpio_irqbank()
487 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, in omap_clear_gpio_irqstatus() argument
490 omap_clear_gpio_irqbank(bank, BIT(offset)); in omap_clear_gpio_irqstatus()
493 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) in omap_get_gpio_irqbank_mask() argument
495 void __iomem *reg = bank->base; in omap_get_gpio_irqbank_mask()
497 u32 mask = (BIT(bank->width)) - 1; in omap_get_gpio_irqbank_mask()
499 reg += bank->regs->irqenable; in omap_get_gpio_irqbank_mask()
501 if (bank->regs->irqenable_inv) in omap_get_gpio_irqbank_mask()
507 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, in omap_set_gpio_irqenable() argument
510 void __iomem *reg = bank->base; in omap_set_gpio_irqenable()
513 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { in omap_set_gpio_irqenable()
515 reg += bank->regs->set_irqenable; in omap_set_gpio_irqenable()
516 bank->context.irqenable1 |= gpio_mask; in omap_set_gpio_irqenable()
518 reg += bank->regs->clr_irqenable; in omap_set_gpio_irqenable()
519 bank->context.irqenable1 &= ~gpio_mask; in omap_set_gpio_irqenable()
523 bank->context.irqenable1 = in omap_set_gpio_irqenable()
524 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, in omap_set_gpio_irqenable()
525 enable ^ bank->regs->irqenable_inv); in omap_set_gpio_irqenable()
534 if (bank->regs->wkup_en && in omap_set_gpio_irqenable()
535 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { in omap_set_gpio_irqenable()
536 bank->context.wake_en = in omap_set_gpio_irqenable()
537 omap_gpio_rmw(bank->base + bank->regs->wkup_en, in omap_set_gpio_irqenable()
545 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_wake_enable() local
547 return irq_set_irq_wake(bank->irq, enable); in omap_gpio_wake_enable()
564 struct gpio_bank *bank = gpiobank; in omap_gpio_irq_handler() local
568 isr_reg = bank->base + bank->regs->irqstatus; in omap_gpio_irq_handler()
572 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), in omap_gpio_irq_handler()
577 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
579 enabled = omap_get_gpio_irqbank_mask(bank); in omap_gpio_irq_handler()
587 edge = isr & ~bank->level_mask; in omap_gpio_irq_handler()
589 omap_clear_gpio_irqbank(bank, edge); in omap_gpio_irq_handler()
591 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
600 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
608 if (bank->toggle_mask & (BIT(bit))) in omap_gpio_irq_handler()
609 omap_toggle_gpio_edge_triggering(bank, bit); in omap_gpio_irq_handler()
611 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
613 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); in omap_gpio_irq_handler()
615 generic_handle_domain_irq(bank->chip.irq.domain, bit); in omap_gpio_irq_handler()
617 raw_spin_unlock_irqrestore(&bank->wa_lock, in omap_gpio_irq_handler()
627 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_startup() local
631 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_startup()
633 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_startup()
634 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_irq_startup()
635 omap_enable_gpio_module(bank, offset); in omap_gpio_irq_startup()
636 bank->irq_usage |= BIT(offset); in omap_gpio_irq_startup()
638 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_startup()
646 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_shutdown() local
650 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_shutdown()
651 bank->irq_usage &= ~(BIT(offset)); in omap_gpio_irq_shutdown()
652 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); in omap_gpio_irq_shutdown()
653 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_irq_shutdown()
654 omap_set_gpio_irqenable(bank, offset, 0); in omap_gpio_irq_shutdown()
655 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_shutdown()
656 omap_clear_gpio_debounce(bank, offset); in omap_gpio_irq_shutdown()
657 omap_disable_gpio_module(bank, offset); in omap_gpio_irq_shutdown()
658 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_shutdown()
663 struct gpio_bank *bank = omap_irq_data_get_bank(data); in omap_gpio_irq_bus_lock() local
665 pm_runtime_get_sync(bank->chip.parent); in omap_gpio_irq_bus_lock()
670 struct gpio_bank *bank = omap_irq_data_get_bank(data); in gpio_irq_bus_sync_unlock() local
672 pm_runtime_put(bank->chip.parent); in gpio_irq_bus_sync_unlock()
677 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_mask_irq() local
681 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_mask_irq()
682 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); in omap_gpio_mask_irq()
683 omap_set_gpio_irqenable(bank, offset, 0); in omap_gpio_mask_irq()
684 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_mask_irq()
685 gpiochip_disable_irq(&bank->chip, offset); in omap_gpio_mask_irq()
690 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_unmask_irq() local
695 gpiochip_enable_irq(&bank->chip, offset); in omap_gpio_unmask_irq()
696 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_unmask_irq()
697 omap_set_gpio_irqenable(bank, offset, 1); in omap_gpio_unmask_irq()
704 if (bank->regs->leveldetect0 && bank->regs->wkup_en && in omap_gpio_unmask_irq()
706 omap_clear_gpio_irqstatus(bank, offset); in omap_gpio_unmask_irq()
709 omap_set_gpio_triggering(bank, offset, trigger); in omap_gpio_unmask_irq()
711 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_unmask_irq()
716 struct gpio_bank *bank = omap_irq_data_get_bank(d); in omap_gpio_irq_print_chip() local
718 seq_printf(p, dev_name(bank->dev)); in omap_gpio_irq_print_chip()
752 struct gpio_bank *bank = dev_get_drvdata(dev); in omap_mpuio_suspend_noirq() local
753 void __iomem *mask_reg = bank->base + in omap_mpuio_suspend_noirq()
754 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_suspend_noirq()
757 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_suspend_noirq()
758 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); in omap_mpuio_suspend_noirq()
759 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_suspend_noirq()
766 struct gpio_bank *bank = dev_get_drvdata(dev); in omap_mpuio_resume_noirq() local
767 void __iomem *mask_reg = bank->base + in omap_mpuio_resume_noirq()
768 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_resume_noirq()
771 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_resume_noirq()
772 writel_relaxed(bank->context.wake_en, mask_reg); in omap_mpuio_resume_noirq()
773 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_resume_noirq()
800 static inline void omap_mpuio_init(struct gpio_bank *bank) in omap_mpuio_init() argument
802 platform_set_drvdata(&omap_mpuio_device, bank); in omap_mpuio_init()
812 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_request() local
817 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_request()
818 omap_enable_gpio_module(bank, offset); in omap_gpio_request()
819 bank->mod_usage |= BIT(offset); in omap_gpio_request()
820 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_request()
827 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_free() local
830 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_free()
831 bank->mod_usage &= ~(BIT(offset)); in omap_gpio_free()
832 if (!LINE_USED(bank->irq_usage, offset)) { in omap_gpio_free()
833 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_free()
834 omap_clear_gpio_debounce(bank, offset); in omap_gpio_free()
836 omap_disable_gpio_module(bank, offset); in omap_gpio_free()
837 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_free()
844 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_get_direction() local
846 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset)) in omap_gpio_get_direction()
854 struct gpio_bank *bank; in omap_gpio_input() local
857 bank = gpiochip_get_data(chip); in omap_gpio_input()
858 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_input()
859 omap_set_gpio_direction(bank, offset, 1); in omap_gpio_input()
860 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_input()
866 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_get() local
869 if (omap_gpio_is_input(bank, offset)) in omap_gpio_get()
870 reg = bank->base + bank->regs->datain; in omap_gpio_get()
872 reg = bank->base + bank->regs->dataout; in omap_gpio_get()
879 struct gpio_bank *bank; in omap_gpio_output() local
882 bank = gpiochip_get_data(chip); in omap_gpio_output()
883 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_output()
884 bank->set_dataout(bank, offset, value); in omap_gpio_output()
885 omap_set_gpio_direction(bank, offset, 0); in omap_gpio_output()
886 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_output()
893 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_get_multiple() local
894 void __iomem *base = bank->base; in omap_gpio_get_multiple()
897 direction = readl_relaxed(base + bank->regs->direction); in omap_gpio_get_multiple()
901 val |= readl_relaxed(base + bank->regs->datain) & m; in omap_gpio_get_multiple()
905 val |= readl_relaxed(base + bank->regs->dataout) & m; in omap_gpio_get_multiple()
915 struct gpio_bank *bank; in omap_gpio_debounce() local
919 bank = gpiochip_get_data(chip); in omap_gpio_debounce()
921 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_debounce()
922 ret = omap2_set_gpio_debounce(bank, offset, debounce); in omap_gpio_debounce()
923 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_debounce()
958 struct gpio_bank *bank; in omap_gpio_set() local
961 bank = gpiochip_get_data(chip); in omap_gpio_set()
962 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set()
963 bank->set_dataout(bank, offset, value); in omap_gpio_set()
964 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set()
970 struct gpio_bank *bank = gpiochip_get_data(chip); in omap_gpio_set_multiple() local
971 void __iomem *reg = bank->base + bank->regs->dataout; in omap_gpio_set_multiple()
975 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set_multiple()
978 bank->context.dataout = l; in omap_gpio_set_multiple()
979 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set_multiple()
984 static void omap_gpio_show_rev(struct gpio_bank *bank) in omap_gpio_show_rev() argument
989 if (called || bank->regs->revision == USHRT_MAX) in omap_gpio_show_rev()
992 rev = readw_relaxed(bank->base + bank->regs->revision); in omap_gpio_show_rev()
999 static void omap_gpio_mod_init(struct gpio_bank *bank) in omap_gpio_mod_init() argument
1001 void __iomem *base = bank->base; in omap_gpio_mod_init()
1004 if (bank->width == 16) in omap_gpio_mod_init()
1007 if (bank->is_mpuio) { in omap_gpio_mod_init()
1008 writel_relaxed(l, bank->base + bank->regs->irqenable); in omap_gpio_mod_init()
1012 omap_gpio_rmw(base + bank->regs->irqenable, l, in omap_gpio_mod_init()
1013 bank->regs->irqenable_inv); in omap_gpio_mod_init()
1014 omap_gpio_rmw(base + bank->regs->irqstatus, l, in omap_gpio_mod_init()
1015 !bank->regs->irqenable_inv); in omap_gpio_mod_init()
1016 if (bank->regs->debounce_en) in omap_gpio_mod_init()
1017 writel_relaxed(0, base + bank->regs->debounce_en); in omap_gpio_mod_init()
1020 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); in omap_gpio_mod_init()
1022 if (bank->regs->ctrl) in omap_gpio_mod_init()
1023 writel_relaxed(0, base + bank->regs->ctrl); in omap_gpio_mod_init()
1026 static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev) in omap_gpio_chip_init() argument
1037 bank->chip.request = omap_gpio_request; in omap_gpio_chip_init()
1038 bank->chip.free = omap_gpio_free; in omap_gpio_chip_init()
1039 bank->chip.get_direction = omap_gpio_get_direction; in omap_gpio_chip_init()
1040 bank->chip.direction_input = omap_gpio_input; in omap_gpio_chip_init()
1041 bank->chip.get = omap_gpio_get; in omap_gpio_chip_init()
1042 bank->chip.get_multiple = omap_gpio_get_multiple; in omap_gpio_chip_init()
1043 bank->chip.direction_output = omap_gpio_output; in omap_gpio_chip_init()
1044 bank->chip.set_config = omap_gpio_set_config; in omap_gpio_chip_init()
1045 bank->chip.set = omap_gpio_set; in omap_gpio_chip_init()
1046 bank->chip.set_multiple = omap_gpio_set_multiple; in omap_gpio_chip_init()
1047 if (bank->is_mpuio) { in omap_gpio_chip_init()
1048 bank->chip.label = "mpuio"; in omap_gpio_chip_init()
1049 if (bank->regs->wkup_en) in omap_gpio_chip_init()
1050 bank->chip.parent = &omap_mpuio_device.dev; in omap_gpio_chip_init()
1051 bank->chip.base = OMAP_MPUIO(0); in omap_gpio_chip_init()
1053 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", in omap_gpio_chip_init()
1054 gpio, gpio + bank->width - 1); in omap_gpio_chip_init()
1057 bank->chip.label = label; in omap_gpio_chip_init()
1058 bank->chip.base = -1; in omap_gpio_chip_init()
1060 bank->chip.ngpio = bank->width; in omap_gpio_chip_init()
1062 irq = &bank->chip.irq; in omap_gpio_chip_init()
1064 if (bank->is_mpuio && !bank->regs->wkup_en) in omap_gpio_chip_init()
1071 irq->parents = &bank->irq; in omap_gpio_chip_init()
1073 ret = gpiochip_add_data(&bank->chip, bank); in omap_gpio_chip_init()
1075 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n"); in omap_gpio_chip_init()
1077 irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev); in omap_gpio_chip_init()
1078 ret = devm_request_irq(bank->chip.parent, bank->irq, in omap_gpio_chip_init()
1080 0, dev_name(bank->chip.parent), bank); in omap_gpio_chip_init()
1082 gpiochip_remove(&bank->chip); in omap_gpio_chip_init()
1084 if (!bank->is_mpuio) in omap_gpio_chip_init()
1085 gpio += bank->width; in omap_gpio_chip_init()
1110 static void omap_gpio_restore_context(struct gpio_bank *bank) in omap_gpio_restore_context() argument
1112 const struct omap_gpio_reg_offs *regs = bank->regs; in omap_gpio_restore_context()
1113 void __iomem *base = bank->base; in omap_gpio_restore_context()
1115 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig); in omap_gpio_restore_context()
1116 writel_relaxed(bank->context.wake_en, base + regs->wkup_en); in omap_gpio_restore_context()
1117 writel_relaxed(bank->context.ctrl, base + regs->ctrl); in omap_gpio_restore_context()
1118 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); in omap_gpio_restore_context()
1119 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); in omap_gpio_restore_context()
1120 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); in omap_gpio_restore_context()
1121 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); in omap_gpio_restore_context()
1122 writel_relaxed(bank->context.dataout, base + regs->dataout); in omap_gpio_restore_context()
1123 writel_relaxed(bank->context.oe, base + regs->direction); in omap_gpio_restore_context()
1125 if (bank->dbck_enable_mask) { in omap_gpio_restore_context()
1126 writel_relaxed(bank->context.debounce, base + regs->debounce); in omap_gpio_restore_context()
1127 writel_relaxed(bank->context.debounce_en, in omap_gpio_restore_context()
1131 writel_relaxed(bank->context.irqenable1, base + regs->irqenable); in omap_gpio_restore_context()
1132 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); in omap_gpio_restore_context()
1135 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) in omap_gpio_idle() argument
1137 struct device *dev = bank->chip.parent; in omap_gpio_idle()
1138 void __iomem *base = bank->base; in omap_gpio_idle()
1141 bank->saved_datain = readl_relaxed(base + bank->regs->datain); in omap_gpio_idle()
1144 if (bank->loses_context) in omap_gpio_idle()
1145 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig); in omap_gpio_idle()
1147 if (!bank->enabled_non_wakeup_gpios) in omap_gpio_idle()
1151 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; in omap_gpio_idle()
1152 mask &= ~bank->context.risingdetect; in omap_gpio_idle()
1153 bank->saved_datain |= mask; in omap_gpio_idle()
1156 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; in omap_gpio_idle()
1157 mask &= ~bank->context.fallingdetect; in omap_gpio_idle()
1158 bank->saved_datain &= ~mask; in omap_gpio_idle()
1168 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { in omap_gpio_idle()
1169 nowake = bank->enabled_non_wakeup_gpios; in omap_gpio_idle()
1170 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); in omap_gpio_idle()
1171 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); in omap_gpio_idle()
1175 if (bank->get_context_loss_count) in omap_gpio_idle()
1176 bank->context_loss_count = in omap_gpio_idle()
1177 bank->get_context_loss_count(dev); in omap_gpio_idle()
1179 omap_gpio_dbck_disable(bank); in omap_gpio_idle()
1182 static void omap_gpio_unidle(struct gpio_bank *bank) in omap_gpio_unidle() argument
1184 struct device *dev = bank->chip.parent; in omap_gpio_unidle()
1193 if (bank->loses_context && !bank->context_valid) { in omap_gpio_unidle()
1194 omap_gpio_init_context(bank); in omap_gpio_unidle()
1196 if (bank->get_context_loss_count) in omap_gpio_unidle()
1197 bank->context_loss_count = in omap_gpio_unidle()
1198 bank->get_context_loss_count(dev); in omap_gpio_unidle()
1201 omap_gpio_dbck_enable(bank); in omap_gpio_unidle()
1203 if (bank->loses_context) { in omap_gpio_unidle()
1204 if (!bank->get_context_loss_count) { in omap_gpio_unidle()
1205 omap_gpio_restore_context(bank); in omap_gpio_unidle()
1207 c = bank->get_context_loss_count(dev); in omap_gpio_unidle()
1208 if (c != bank->context_loss_count) { in omap_gpio_unidle()
1209 omap_gpio_restore_context(bank); in omap_gpio_unidle()
1216 writel_relaxed(bank->context.fallingdetect, in omap_gpio_unidle()
1217 bank->base + bank->regs->fallingdetect); in omap_gpio_unidle()
1218 writel_relaxed(bank->context.risingdetect, in omap_gpio_unidle()
1219 bank->base + bank->regs->risingdetect); in omap_gpio_unidle()
1222 l = readl_relaxed(bank->base + bank->regs->datain); in omap_gpio_unidle()
1230 l ^= bank->saved_datain; in omap_gpio_unidle()
1231 l &= bank->enabled_non_wakeup_gpios; in omap_gpio_unidle()
1237 gen0 = l & bank->context.fallingdetect; in omap_gpio_unidle()
1238 gen0 &= bank->saved_datain; in omap_gpio_unidle()
1240 gen1 = l & bank->context.risingdetect; in omap_gpio_unidle()
1241 gen1 &= ~(bank->saved_datain); in omap_gpio_unidle()
1244 gen = l & (~(bank->context.fallingdetect) & in omap_gpio_unidle()
1245 ~(bank->context.risingdetect)); in omap_gpio_unidle()
1252 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_gpio_unidle()
1253 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_gpio_unidle()
1255 if (!bank->regs->irqstatus_raw0) { in omap_gpio_unidle()
1256 writel_relaxed(old0 | gen, bank->base + in omap_gpio_unidle()
1257 bank->regs->leveldetect0); in omap_gpio_unidle()
1258 writel_relaxed(old1 | gen, bank->base + in omap_gpio_unidle()
1259 bank->regs->leveldetect1); in omap_gpio_unidle()
1262 if (bank->regs->irqstatus_raw0) { in omap_gpio_unidle()
1263 writel_relaxed(old0 | l, bank->base + in omap_gpio_unidle()
1264 bank->regs->leveldetect0); in omap_gpio_unidle()
1265 writel_relaxed(old1 | l, bank->base + in omap_gpio_unidle()
1266 bank->regs->leveldetect1); in omap_gpio_unidle()
1268 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); in omap_gpio_unidle()
1269 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); in omap_gpio_unidle()
1276 struct gpio_bank *bank; in gpio_omap_cpu_notifier() local
1281 bank = container_of(nb, struct gpio_bank, nb); in gpio_omap_cpu_notifier()
1283 raw_spin_lock_irqsave(&bank->lock, flags); in gpio_omap_cpu_notifier()
1284 if (bank->is_suspended) in gpio_omap_cpu_notifier()
1289 mask = omap_get_gpio_irqbank_mask(bank); in gpio_omap_cpu_notifier()
1290 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask; in gpio_omap_cpu_notifier()
1295 omap_gpio_idle(bank, true); in gpio_omap_cpu_notifier()
1299 omap_gpio_unidle(bank); in gpio_omap_cpu_notifier()
1304 raw_spin_unlock_irqrestore(&bank->lock, flags); in gpio_omap_cpu_notifier()
1399 struct gpio_bank *bank; in omap_gpio_probe() local
1408 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); in omap_gpio_probe()
1409 if (!bank) in omap_gpio_probe()
1412 bank->dev = dev; in omap_gpio_probe()
1414 bank->irq = platform_get_irq(pdev, 0); in omap_gpio_probe()
1415 if (bank->irq < 0) in omap_gpio_probe()
1416 return bank->irq; in omap_gpio_probe()
1418 bank->chip.parent = dev; in omap_gpio_probe()
1419 bank->chip.owner = THIS_MODULE; in omap_gpio_probe()
1420 bank->dbck_flag = pdata->dbck_flag; in omap_gpio_probe()
1421 bank->stride = pdata->bank_stride; in omap_gpio_probe()
1422 bank->width = pdata->bank_width; in omap_gpio_probe()
1423 bank->is_mpuio = pdata->is_mpuio; in omap_gpio_probe()
1424 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; in omap_gpio_probe()
1425 bank->regs = pdata->regs; in omap_gpio_probe()
1429 bank->loses_context = true; in omap_gpio_probe()
1431 bank->loses_context = pdata->loses_context; in omap_gpio_probe()
1433 if (bank->loses_context) in omap_gpio_probe()
1434 bank->get_context_loss_count = in omap_gpio_probe()
1438 if (bank->regs->set_dataout && bank->regs->clr_dataout) in omap_gpio_probe()
1439 bank->set_dataout = omap_set_gpio_dataout_reg; in omap_gpio_probe()
1441 bank->set_dataout = omap_set_gpio_dataout_mask; in omap_gpio_probe()
1443 raw_spin_lock_init(&bank->lock); in omap_gpio_probe()
1444 raw_spin_lock_init(&bank->wa_lock); in omap_gpio_probe()
1447 bank->base = devm_platform_ioremap_resource(pdev, 0); in omap_gpio_probe()
1448 if (IS_ERR(bank->base)) { in omap_gpio_probe()
1449 return PTR_ERR(bank->base); in omap_gpio_probe()
1452 if (bank->dbck_flag) { in omap_gpio_probe()
1453 bank->dbck = devm_clk_get(dev, "dbclk"); in omap_gpio_probe()
1454 if (IS_ERR(bank->dbck)) { in omap_gpio_probe()
1457 bank->dbck_flag = false; in omap_gpio_probe()
1459 clk_prepare(bank->dbck); in omap_gpio_probe()
1463 platform_set_drvdata(pdev, bank); in omap_gpio_probe()
1468 if (bank->is_mpuio) in omap_gpio_probe()
1469 omap_mpuio_init(bank); in omap_gpio_probe()
1471 omap_gpio_mod_init(bank); in omap_gpio_probe()
1473 ret = omap_gpio_chip_init(bank, dev); in omap_gpio_probe()
1477 if (bank->dbck_flag) in omap_gpio_probe()
1478 clk_unprepare(bank->dbck); in omap_gpio_probe()
1482 omap_gpio_show_rev(bank); in omap_gpio_probe()
1484 bank->nb.notifier_call = gpio_omap_cpu_notifier; in omap_gpio_probe()
1485 cpu_pm_register_notifier(&bank->nb); in omap_gpio_probe()
1494 struct gpio_bank *bank = platform_get_drvdata(pdev); in omap_gpio_remove() local
1496 cpu_pm_unregister_notifier(&bank->nb); in omap_gpio_remove()
1497 gpiochip_remove(&bank->chip); in omap_gpio_remove()
1499 if (bank->dbck_flag) in omap_gpio_remove()
1500 clk_unprepare(bank->dbck); in omap_gpio_remove()
1507 struct gpio_bank *bank = dev_get_drvdata(dev); in omap_gpio_runtime_suspend() local
1510 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_suspend()
1511 omap_gpio_idle(bank, true); in omap_gpio_runtime_suspend()
1512 bank->is_suspended = true; in omap_gpio_runtime_suspend()
1513 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_suspend()
1520 struct gpio_bank *bank = dev_get_drvdata(dev); in omap_gpio_runtime_resume() local
1523 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_resume()
1524 omap_gpio_unidle(bank); in omap_gpio_runtime_resume()
1525 bank->is_suspended = false; in omap_gpio_runtime_resume()
1526 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_resume()
1533 struct gpio_bank *bank = dev_get_drvdata(dev); in omap_gpio_suspend() local
1535 if (bank->is_suspended) in omap_gpio_suspend()
1538 bank->needs_resume = 1; in omap_gpio_suspend()
1545 struct gpio_bank *bank = dev_get_drvdata(dev); in omap_gpio_resume() local
1547 if (!bank->needs_resume) in omap_gpio_resume()
1550 bank->needs_resume = 0; in omap_gpio_resume()