Lines Matching +full:port +full:- +full:level
1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "gpiolib-acpi.h"
47 #define DWAPB_DRIVER_NAME "gpio-dwapb"
83 /* Store GPIO context across system-wide suspend/resume transitions */
112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) in gpio_reg_convert()
152 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_read()
153 void __iomem *reg_base = gpio->regs; in dwapb_read()
155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); in dwapb_read()
161 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_write()
162 void __iomem *reg_base = gpio->regs; in dwapb_write()
164 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); in dwapb_write()
169 struct dwapb_gpio_port *port; in dwapb_offs_to_port() local
172 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_offs_to_port()
173 port = &gpio->ports[i]; in dwapb_offs_to_port()
174 if (port->idx == offs / DWAPB_MAX_GPIOS) in dwapb_offs_to_port()
175 return port; in dwapb_offs_to_port()
183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); in dwapb_toggle_trigger() local
188 if (!port) in dwapb_toggle_trigger()
190 gc = &port->gc; in dwapb_toggle_trigger()
194 val = gc->get(gc, offs % DWAPB_MAX_GPIOS); in dwapb_toggle_trigger()
205 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_do_irq()
211 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); in dwapb_do_irq()
245 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_ack()
247 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_ack()
258 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_mask()
261 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_mask()
276 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_unmask()
279 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_unmask()
290 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_enable()
295 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_enable()
306 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_disable()
311 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_disable()
319 unsigned long level, polarity, flags; in dwapb_irq_set_type() local
321 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_irq_set_type()
322 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); in dwapb_irq_set_type()
327 level |= BIT(bit); in dwapb_irq_set_type()
331 level |= BIT(bit); in dwapb_irq_set_type()
335 level |= BIT(bit); in dwapb_irq_set_type()
339 level &= ~BIT(bit); in dwapb_irq_set_type()
343 level &= ~BIT(bit); in dwapb_irq_set_type()
353 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); in dwapb_irq_set_type()
356 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_irq_set_type()
366 struct dwapb_context *ctx = gpio->ports[0].ctx; in dwapb_irq_set_wake()
370 ctx->wake_en |= BIT(bit); in dwapb_irq_set_wake()
372 ctx->wake_en &= ~BIT(bit); in dwapb_irq_set_wake()
396 struct dwapb_gpio_port *port = gpiochip_get_data(gc); in dwapb_gpio_set_debounce() local
397 struct dwapb_gpio *gpio = port->gpio; in dwapb_gpio_set_debounce()
401 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_gpio_set_debounce()
410 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_gpio_set_debounce()
421 return -ENOTSUPP; in dwapb_gpio_set_config()
433 for (i = 0; i < pp->ngpio; ++i) { in dwapb_convert_irqs()
434 if (!pp->irq[i]) in dwapb_convert_irqs()
437 pirq->irq[pirq->nr_irqs++] = pp->irq[i]; in dwapb_convert_irqs()
440 return pirq->nr_irqs ? 0 : -ENOENT; in dwapb_convert_irqs()
444 struct dwapb_gpio_port *port, in dwapb_configure_irqs() argument
448 struct gpio_chip *gc = &port->gc; in dwapb_configure_irqs()
452 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); in dwapb_configure_irqs()
457 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); in dwapb_configure_irqs()
461 girq = &gc->irq; in dwapb_configure_irqs()
462 girq->handler = handle_bad_irq; in dwapb_configure_irqs()
463 girq->default_type = IRQ_TYPE_NONE; in dwapb_configure_irqs()
465 port->pirq = pirq; in dwapb_configure_irqs()
468 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO in dwapb_configure_irqs()
473 if (has_acpi_companion(gpio->dev)) { in dwapb_configure_irqs()
474 girq->num_parents = 0; in dwapb_configure_irqs()
475 girq->parents = NULL; in dwapb_configure_irqs()
476 girq->parent_handler = NULL; in dwapb_configure_irqs()
478 err = devm_request_irq(gpio->dev, pp->irq[0], in dwapb_configure_irqs()
482 dev_err(gpio->dev, "error requesting IRQ\n"); in dwapb_configure_irqs()
486 girq->num_parents = pirq->nr_irqs; in dwapb_configure_irqs()
487 girq->parents = pirq->irq; in dwapb_configure_irqs()
488 girq->parent_handler_data = gpio; in dwapb_configure_irqs()
489 girq->parent_handler = dwapb_irq_handler; in dwapb_configure_irqs()
497 devm_kfree(gpio->dev, pirq); in dwapb_configure_irqs()
504 struct dwapb_gpio_port *port; in dwapb_gpio_add_port() local
508 port = &gpio->ports[offs]; in dwapb_gpio_add_port()
509 port->gpio = gpio; in dwapb_gpio_add_port()
510 port->idx = pp->idx; in dwapb_gpio_add_port()
513 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); in dwapb_gpio_add_port()
514 if (!port->ctx) in dwapb_gpio_add_port()
515 return -ENOMEM; in dwapb_gpio_add_port()
518 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; in dwapb_gpio_add_port()
519 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; in dwapb_gpio_add_port()
520 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; in dwapb_gpio_add_port()
522 /* This registers 32 GPIO lines per port */ in dwapb_gpio_add_port()
523 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, in dwapb_gpio_add_port()
526 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", in dwapb_gpio_add_port()
527 port->idx); in dwapb_gpio_add_port()
531 port->gc.fwnode = pp->fwnode; in dwapb_gpio_add_port()
532 port->gc.ngpio = pp->ngpio; in dwapb_gpio_add_port()
533 port->gc.base = pp->gpio_base; in dwapb_gpio_add_port()
535 /* Only port A support debounce */ in dwapb_gpio_add_port()
536 if (pp->idx == 0) in dwapb_gpio_add_port()
537 port->gc.set_config = dwapb_gpio_set_config; in dwapb_gpio_add_port()
539 /* Only port A can provide interrupts in all configurations of the IP */ in dwapb_gpio_add_port()
540 if (pp->idx == 0) in dwapb_gpio_add_port()
541 dwapb_configure_irqs(gpio, port, pp); in dwapb_gpio_add_port()
543 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); in dwapb_gpio_add_port()
545 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", in dwapb_gpio_add_port()
546 port->idx); in dwapb_gpio_add_port()
558 for (j = 0; j < pp->ngpio; j++) { in dwapb_get_irq()
564 pp->irq[j] = irq; in dwapb_get_irq()
578 return ERR_PTR(-ENODEV); in dwapb_gpio_get_pdata()
582 return ERR_PTR(-ENOMEM); in dwapb_gpio_get_pdata()
584 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); in dwapb_gpio_get_pdata()
585 if (!pdata->properties) in dwapb_gpio_get_pdata()
586 return ERR_PTR(-ENOMEM); in dwapb_gpio_get_pdata()
588 pdata->nports = nports; in dwapb_gpio_get_pdata()
592 pp = &pdata->properties[i++]; in dwapb_gpio_get_pdata()
593 pp->fwnode = fwnode; in dwapb_gpio_get_pdata()
595 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || in dwapb_gpio_get_pdata()
596 pp->idx >= DWAPB_MAX_PORTS) { in dwapb_gpio_get_pdata()
598 "missing/invalid port index for port%d\n", i); in dwapb_gpio_get_pdata()
600 return ERR_PTR(-EINVAL); in dwapb_gpio_get_pdata()
603 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && in dwapb_gpio_get_pdata()
604 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { in dwapb_gpio_get_pdata()
606 "failed to get number of gpios for port%d\n", in dwapb_gpio_get_pdata()
608 pp->ngpio = DWAPB_MAX_GPIOS; in dwapb_gpio_get_pdata()
611 pp->gpio_base = -1; in dwapb_gpio_get_pdata()
615 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base); in dwapb_gpio_get_pdata()
618 * Only port A can provide interrupts in all configurations of in dwapb_gpio_get_pdata()
621 if (pp->idx == 0) in dwapb_gpio_get_pdata()
632 reset_control_assert(gpio->rst); in dwapb_assert_reset()
639 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); in dwapb_get_reset()
640 if (IS_ERR(gpio->rst)) in dwapb_get_reset()
641 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), in dwapb_get_reset()
644 err = reset_control_deassert(gpio->rst); in dwapb_get_reset()
646 dev_err(gpio->dev, "Cannot deassert reset lane\n"); in dwapb_get_reset()
650 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); in dwapb_get_reset()
657 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_disable_clks()
665 gpio->clks[0].id = "bus"; in dwapb_get_clks()
666 gpio->clks[1].id = "db"; in dwapb_get_clks()
667 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, in dwapb_get_clks()
668 gpio->clks); in dwapb_get_clks()
670 return dev_err_probe(gpio->dev, err, in dwapb_get_clks()
673 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_get_clks()
675 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); in dwapb_get_clks()
679 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); in dwapb_get_clks()
683 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
684 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
703 struct device *dev = &pdev->dev; in dwapb_gpio_probe()
709 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in dwapb_gpio_probe()
711 return -ENOMEM; in dwapb_gpio_probe()
713 gpio->dev = &pdev->dev; in dwapb_gpio_probe()
714 gpio->nr_ports = pdata->nports; in dwapb_gpio_probe()
720 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, in dwapb_gpio_probe()
721 sizeof(*gpio->ports), GFP_KERNEL); in dwapb_gpio_probe()
722 if (!gpio->ports) in dwapb_gpio_probe()
723 return -ENOMEM; in dwapb_gpio_probe()
725 gpio->regs = devm_platform_ioremap_resource(pdev, 0); in dwapb_gpio_probe()
726 if (IS_ERR(gpio->regs)) in dwapb_gpio_probe()
727 return PTR_ERR(gpio->regs); in dwapb_gpio_probe()
733 gpio->flags = (uintptr_t)device_get_match_data(dev); in dwapb_gpio_probe()
735 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_probe()
736 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); in dwapb_gpio_probe()
750 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_gpio_suspend()
754 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_gpio_suspend()
755 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_suspend()
757 unsigned int idx = gpio->ports[i].idx; in dwapb_gpio_suspend()
758 struct dwapb_context *ctx = gpio->ports[i].ctx; in dwapb_gpio_suspend()
761 ctx->dir = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
764 ctx->data = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
767 ctx->ext = dwapb_read(gpio, offset); in dwapb_gpio_suspend()
769 /* Only port A can provide interrupts */ in dwapb_gpio_suspend()
771 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); in dwapb_gpio_suspend()
772 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); in dwapb_gpio_suspend()
773 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_gpio_suspend()
774 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); in dwapb_gpio_suspend()
775 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); in dwapb_gpio_suspend()
778 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); in dwapb_gpio_suspend()
781 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_gpio_suspend()
783 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_gpio_suspend()
791 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_gpio_resume()
795 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); in dwapb_gpio_resume()
797 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); in dwapb_gpio_resume()
801 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in dwapb_gpio_resume()
802 for (i = 0; i < gpio->nr_ports; i++) { in dwapb_gpio_resume()
804 unsigned int idx = gpio->ports[i].idx; in dwapb_gpio_resume()
805 struct dwapb_context *ctx = gpio->ports[i].ctx; in dwapb_gpio_resume()
808 dwapb_write(gpio, offset, ctx->data); in dwapb_gpio_resume()
811 dwapb_write(gpio, offset, ctx->dir); in dwapb_gpio_resume()
814 dwapb_write(gpio, offset, ctx->ext); in dwapb_gpio_resume()
816 /* Only port A can provide interrupts */ in dwapb_gpio_resume()
818 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); in dwapb_gpio_resume()
819 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); in dwapb_gpio_resume()
820 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); in dwapb_gpio_resume()
821 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); in dwapb_gpio_resume()
822 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); in dwapb_gpio_resume()
828 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in dwapb_gpio_resume()