Lines Matching refs:sw_desc
506 struct xilinx_dpdma_sw_desc *sw_desc, in xilinx_dpdma_sw_desc_set_dma_addrs() argument
511 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; in xilinx_dpdma_sw_desc_set_dma_addrs()
538 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr); in xilinx_dpdma_sw_desc_set_dma_addrs()
542 upper_32_bits(sw_desc->dma_addr)); in xilinx_dpdma_sw_desc_set_dma_addrs()
556 struct xilinx_dpdma_sw_desc *sw_desc; in xilinx_dpdma_chan_alloc_sw_desc() local
559 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr); in xilinx_dpdma_chan_alloc_sw_desc()
560 if (!sw_desc) in xilinx_dpdma_chan_alloc_sw_desc()
563 sw_desc->dma_addr = dma_addr; in xilinx_dpdma_chan_alloc_sw_desc()
565 return sw_desc; in xilinx_dpdma_chan_alloc_sw_desc()
577 struct xilinx_dpdma_sw_desc *sw_desc) in xilinx_dpdma_chan_free_sw_desc() argument
579 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr); in xilinx_dpdma_chan_free_sw_desc()
592 struct xilinx_dpdma_sw_desc *sw_desc; in xilinx_dpdma_chan_dump_tx_desc() local
599 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) { in xilinx_dpdma_chan_dump_tx_desc()
600 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; in xilinx_dpdma_chan_dump_tx_desc()
603 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr); in xilinx_dpdma_chan_dump_tx_desc()
657 struct xilinx_dpdma_sw_desc *sw_desc, *next; in xilinx_dpdma_chan_free_tx_desc() local
665 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) { in xilinx_dpdma_chan_free_tx_desc()
666 list_del(&sw_desc->node); in xilinx_dpdma_chan_free_tx_desc()
667 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc); in xilinx_dpdma_chan_free_tx_desc()
689 struct xilinx_dpdma_sw_desc *sw_desc; in xilinx_dpdma_chan_prep_interleaved_dma() local
705 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan); in xilinx_dpdma_chan_prep_interleaved_dma()
706 if (!sw_desc) { in xilinx_dpdma_chan_prep_interleaved_dma()
711 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc, in xilinx_dpdma_chan_prep_interleaved_dma()
714 hw_desc = &sw_desc->hw; in xilinx_dpdma_chan_prep_interleaved_dma()
726 list_add_tail(&sw_desc->node, &tx_desc->descriptors); in xilinx_dpdma_chan_prep_interleaved_dma()
829 struct xilinx_dpdma_sw_desc *sw_desc; in xilinx_dpdma_chan_queue_transfer() local
859 list_for_each_entry(sw_desc, &desc->descriptors, node) in xilinx_dpdma_chan_queue_transfer()
860 sw_desc->hw.desc_id = desc->vdesc.tx.cookie in xilinx_dpdma_chan_queue_transfer()
863 sw_desc = list_first_entry(&desc->descriptors, in xilinx_dpdma_chan_queue_transfer()
866 lower_32_bits(sw_desc->dma_addr)); in xilinx_dpdma_chan_queue_transfer()
870 upper_32_bits(sw_desc->dma_addr))); in xilinx_dpdma_chan_queue_transfer()
1074 struct xilinx_dpdma_sw_desc *sw_desc; in xilinx_dpdma_chan_vsync_irq() local
1088 sw_desc = list_first_entry(&pending->descriptors, in xilinx_dpdma_chan_vsync_irq()
1090 if (sw_desc->hw.desc_id != desc_id) { in xilinx_dpdma_chan_vsync_irq()
1093 chan->id, sw_desc->hw.desc_id, desc_id); in xilinx_dpdma_chan_vsync_irq()