1 /* SPDX-License-Identifier: GPL-2.0-only */
18  * (port-driver, region-driver, nvdimm object-drivers... etc).
82 		return -EINVAL;  in eig_to_granularity()
87 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
95 		*ways = 3 << (eiw - 8);  in eiw_to_ways()
98 		return -EINVAL;  in eiw_to_ways()
108 		return -EINVAL;  in granularity_to_eig()
109 	*eig = ilog2(granularity) - 8;  in granularity_to_eig()
116 		return -EINVAL;  in ways_to_eiw()
122 		return -EINVAL;  in ways_to_eiw()
125 		return -EINVAL;  in ways_to_eiw()
174 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
200  * Using struct_group() allows for per register-block-type helper routines,
201  * without requiring block-type agnostic code to include the prefix.
251  * struct cxl_register_map - DVSEC harvested register block mapping parameters
253  * @base: virtual base of the register-block-BAR + @block_offset
255  * @max_size: maximum mapping size to perform register search
297 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
328  * struct cxl_decoder - Common CXL HDM Decoder Attributes
337  * @commit: device/decoder-type specific callback to commit settings to hw
338  * @reset: device/decoder-type specific callback to reset hw settings
365 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode)  in cxl_decoder_mode_name()  argument
374 	if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED)  in cxl_decoder_mode_name()
375 		return names[mode];  in cxl_decoder_mode_name()
389  * struct cxl_endpoint_decoder - Endpoint  / SPA to DPA decoder
393  * @mode: which memory type / access-mode-partition this decoder targets
401 	enum cxl_decoder_mode mode;  member
407  * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
414  * come in two flavors, root-level decoders, statically defined by platform
415  * firmware, and mid-level decoders, where interleave-granularity,
416  * interleave-width, and the target list are mutable.
429  * struct cxl_root_decoder - Static platform CXL address decoder
447  * enum cxl_config_state - State machine for region configuration
454  * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
465  * struct cxl_region_params - region settings
502  * struct cxl_region - CXL region
505  * @mode: Endpoint decoder allocation / access mode
515 	enum cxl_decoder_mode mode;  member
526 	struct cxl_port *port;  member
553 	struct cxl_pmem_region_mapping mapping[];  member
563  * struct cxl_port - logical collection of upstream port devices and
564  *		     downstream port devices to construct a CXL memory
566  * @dev: this port's device
567  * @uport_dev: PCI or platform device implementing the upstream port capability
568  * @host_bridge: Shortcut to the platform attach point for this port
569  * @id: id for port device-name
571  * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
572  * @regions: cxl_region_ref instances, regions mapped by this port
573  * @parent_dport: dport that points to this port in the parent
580  * @dead: last ep has been removed, force port re-creation
581  * @depth: How deep this port is relative to the root. depth 0 is the root.
610 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)  in cxl_find_dport_by_dev()  argument
612 	return xa_load(&port->dports, (unsigned long)dport_dev);  in cxl_find_dport_by_dev()
621  * struct cxl_dport - CXL downstream port
626  * @rch: Indicate whether this dport was enumerated in RCH or VH mode
627  * @port: reference to cxl_port that contains this downstream port
635 	struct cxl_port *port;  member
639  * struct cxl_ep - track an endpoint's interest in a port
641  * @dport: which dport routes to this endpoint on @port
642  * @next: cxl switch port across the link attached to @dport NULL if
652  * struct cxl_region_ref - track a region's interest in a port
653  * @port: point in topology to install this reference
654  * @decoder: decoder assigned for @region in @port
656  * @endpoints: cxl_ep references for region members beneath @port
658  * @nr_eps: number of endpoints beneath @port
662 	struct cxl_port *port;  member
673  * CXL port topology. All other CXL ports have another CXL port as their
674  * parent and their ->uport_dev / host device is out-of-line of the port
677 static inline bool is_cxl_root(struct cxl_port *port)  in is_cxl_root()  argument
679 	return port->uport_dev == port->dev.parent;  in is_cxl_root()
682 int cxl_num_decoders_committed(struct cxl_port *port);
689 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
694 struct cxl_port *find_cxl_root(struct cxl_port *port);
704 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
707 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
718 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
722 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
725 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
731  * struct cxl_endpoint_dvsec_info - Cached DVSEC info
734  * @port: endpoint port associated with this info instance
740 	struct cxl_port *port;  member
745 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
749 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
793 						     struct cxl_port *port);