Lines Matching +full:inline +full:- +full:crypto +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
12 #include <crypto/hmac.h>
13 #include <crypto/md5.h>
14 #include <crypto/sha1.h>
15 #include <crypto/sha2.h>
17 #include <linux/dma-mapping.h>
26 static inline void
31 unsigned int len = req->nbytes + creq->cache_ptr; in mv_cesa_ahash_req_iter_init()
33 if (!creq->last_req) in mv_cesa_ahash_req_iter_init()
36 mv_cesa_req_dma_iter_init(&iter->base, len); in mv_cesa_ahash_req_iter_init()
37 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE); in mv_cesa_ahash_req_iter_init()
38 iter->src.op_offset = creq->cache_ptr; in mv_cesa_ahash_req_iter_init()
41 static inline bool
44 iter->src.op_offset = 0; in mv_cesa_ahash_req_iter_next_op()
46 return mv_cesa_req_dma_iter_next_op(&iter->base); in mv_cesa_ahash_req_iter_next_op()
49 static inline int
52 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags, in mv_cesa_ahash_dma_alloc_cache()
53 &req->cache_dma); in mv_cesa_ahash_dma_alloc_cache()
54 if (!req->cache) in mv_cesa_ahash_dma_alloc_cache()
55 return -ENOMEM; in mv_cesa_ahash_dma_alloc_cache()
60 static inline void
63 if (!req->cache) in mv_cesa_ahash_dma_free_cache()
66 dma_pool_free(cesa_dev->dma->cache_pool, req->cache, in mv_cesa_ahash_dma_free_cache()
67 req->cache_dma); in mv_cesa_ahash_dma_free_cache()
73 if (req->padding) in mv_cesa_ahash_dma_alloc_padding()
76 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags, in mv_cesa_ahash_dma_alloc_padding()
77 &req->padding_dma); in mv_cesa_ahash_dma_alloc_padding()
78 if (!req->padding) in mv_cesa_ahash_dma_alloc_padding()
79 return -ENOMEM; in mv_cesa_ahash_dma_alloc_padding()
86 if (!req->padding) in mv_cesa_ahash_dma_free_padding()
89 dma_pool_free(cesa_dev->dma->padding_pool, req->padding, in mv_cesa_ahash_dma_free_padding()
90 req->padding_dma); in mv_cesa_ahash_dma_free_padding()
91 req->padding = NULL; in mv_cesa_ahash_dma_free_padding()
94 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req) in mv_cesa_ahash_dma_last_cleanup()
98 mv_cesa_ahash_dma_free_padding(&creq->req.dma); in mv_cesa_ahash_dma_last_cleanup()
101 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req) in mv_cesa_ahash_dma_cleanup()
105 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE); in mv_cesa_ahash_dma_cleanup()
106 mv_cesa_ahash_dma_free_cache(&creq->req.dma); in mv_cesa_ahash_dma_cleanup()
107 mv_cesa_dma_cleanup(&creq->base); in mv_cesa_ahash_dma_cleanup()
110 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req) in mv_cesa_ahash_cleanup()
114 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) in mv_cesa_ahash_cleanup()
122 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) in mv_cesa_ahash_last_cleanup()
130 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK; in mv_cesa_ahash_pad_len()
131 padlen = (index < 56) ? (56 - index) : (64 + 56 - index); in mv_cesa_ahash_pad_len()
143 memset(buf + 1, 0, padlen - 1); in mv_cesa_ahash_pad_req()
145 if (creq->algo_le) { in mv_cesa_ahash_pad_req()
146 __le64 bits = cpu_to_le64(creq->len << 3); in mv_cesa_ahash_pad_req()
150 __be64 bits = cpu_to_be64(creq->len << 3); in mv_cesa_ahash_pad_req()
161 struct mv_cesa_ahash_std_req *sreq = &creq->req.std; in mv_cesa_ahash_std_step()
162 struct mv_cesa_engine *engine = creq->base.engine; in mv_cesa_ahash_std_step() local
170 mv_cesa_adjust_op(engine, &creq->op_tmpl); in mv_cesa_ahash_std_step()
171 if (engine->pool) in mv_cesa_ahash_std_step()
172 memcpy(engine->sram_pool, &creq->op_tmpl, in mv_cesa_ahash_std_step()
173 sizeof(creq->op_tmpl)); in mv_cesa_ahash_std_step()
175 memcpy_toio(engine->sram, &creq->op_tmpl, in mv_cesa_ahash_std_step()
176 sizeof(creq->op_tmpl)); in mv_cesa_ahash_std_step()
178 if (!sreq->offset) { in mv_cesa_ahash_std_step()
181 writel_relaxed(creq->state[i], in mv_cesa_ahash_std_step()
182 engine->regs + CESA_IVDIG(i)); in mv_cesa_ahash_std_step()
185 if (creq->cache_ptr) { in mv_cesa_ahash_std_step()
186 if (engine->pool) in mv_cesa_ahash_std_step()
187 memcpy(engine->sram_pool + CESA_SA_DATA_SRAM_OFFSET, in mv_cesa_ahash_std_step()
188 creq->cache, creq->cache_ptr); in mv_cesa_ahash_std_step()
190 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET, in mv_cesa_ahash_std_step()
191 creq->cache, creq->cache_ptr); in mv_cesa_ahash_std_step()
194 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset, in mv_cesa_ahash_std_step()
197 if (!creq->last_req) { in mv_cesa_ahash_std_step()
202 if (len - creq->cache_ptr) in mv_cesa_ahash_std_step()
203 sreq->offset += mv_cesa_sg_copy_to_sram( in mv_cesa_ahash_std_step()
204 engine, req->src, creq->src_nents, in mv_cesa_ahash_std_step()
205 CESA_SA_DATA_SRAM_OFFSET + creq->cache_ptr, in mv_cesa_ahash_std_step()
206 len - creq->cache_ptr, sreq->offset); in mv_cesa_ahash_std_step()
208 op = &creq->op_tmpl; in mv_cesa_ahash_std_step()
212 if (creq->last_req && sreq->offset == req->nbytes && in mv_cesa_ahash_std_step()
213 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) { in mv_cesa_ahash_std_step()
223 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) { in mv_cesa_ahash_std_step()
224 mv_cesa_set_mac_op_total_len(op, creq->len); in mv_cesa_ahash_std_step()
230 new_cache_ptr = 64 - trailerlen; in mv_cesa_ahash_std_step()
231 if (engine->pool) in mv_cesa_ahash_std_step()
232 memcpy(creq->cache, in mv_cesa_ahash_std_step()
233 engine->sram_pool + in mv_cesa_ahash_std_step()
237 memcpy_fromio(creq->cache, in mv_cesa_ahash_std_step()
238 engine->sram + in mv_cesa_ahash_std_step()
243 i = mv_cesa_ahash_pad_req(creq, creq->cache); in mv_cesa_ahash_std_step()
245 if (engine->pool) in mv_cesa_ahash_std_step()
246 memcpy(engine->sram_pool + len + in mv_cesa_ahash_std_step()
248 creq->cache, i); in mv_cesa_ahash_std_step()
250 memcpy_toio(engine->sram + len + in mv_cesa_ahash_std_step()
252 creq->cache, i); in mv_cesa_ahash_std_step()
266 if (engine->pool) in mv_cesa_ahash_std_step()
267 memcpy(engine->sram_pool, op, sizeof(*op)); in mv_cesa_ahash_std_step()
269 memcpy_toio(engine->sram, op, sizeof(*op)); in mv_cesa_ahash_std_step()
275 creq->cache_ptr = new_cache_ptr; in mv_cesa_ahash_std_step()
277 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE); in mv_cesa_ahash_std_step()
278 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG); in mv_cesa_ahash_std_step()
279 WARN_ON(readl(engine->regs + CESA_SA_CMD) & in mv_cesa_ahash_std_step()
281 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD); in mv_cesa_ahash_std_step()
287 struct mv_cesa_ahash_std_req *sreq = &creq->req.std; in mv_cesa_ahash_std_process()
289 if (sreq->offset < (req->nbytes - creq->cache_ptr)) in mv_cesa_ahash_std_process()
290 return -EINPROGRESS; in mv_cesa_ahash_std_process()
295 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req) in mv_cesa_ahash_dma_prepare()
298 struct mv_cesa_req *basereq = &creq->base; in mv_cesa_ahash_dma_prepare()
300 mv_cesa_dma_prepare(basereq, basereq->engine); in mv_cesa_ahash_dma_prepare()
306 struct mv_cesa_ahash_std_req *sreq = &creq->req.std; in mv_cesa_ahash_std_prepare()
308 sreq->offset = 0; in mv_cesa_ahash_std_prepare()
314 struct mv_cesa_req *base = &creq->base; in mv_cesa_ahash_dma_step()
317 if (base->chain.first->flags & CESA_TDMA_SET_STATE) { in mv_cesa_ahash_dma_step()
318 struct mv_cesa_engine *engine = base->engine; in mv_cesa_ahash_dma_step() local
322 for (i = 0; i < ARRAY_SIZE(creq->state); i++) in mv_cesa_ahash_dma_step()
323 writel_relaxed(creq->state[i], engine->regs + in mv_cesa_ahash_dma_step()
335 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) in mv_cesa_ahash_step()
346 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) in mv_cesa_ahash_process()
347 return mv_cesa_dma_process(&creq->base, status); in mv_cesa_ahash_process()
356 struct mv_cesa_engine *engine = creq->base.engine; in mv_cesa_ahash_complete() local
362 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ && in mv_cesa_ahash_complete()
363 (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) == in mv_cesa_ahash_complete()
371 data = creq->base.chain.last->op->ctx.hash.hash; in mv_cesa_ahash_complete()
373 creq->state[i] = le32_to_cpu(data[i]); in mv_cesa_ahash_complete()
375 memcpy(ahashreq->result, data, digsize); in mv_cesa_ahash_complete()
378 creq->state[i] = readl_relaxed(engine->regs + in mv_cesa_ahash_complete()
380 if (creq->last_req) { in mv_cesa_ahash_complete()
385 if (creq->algo_le) { in mv_cesa_ahash_complete()
386 __le32 *result = (void *)ahashreq->result; in mv_cesa_ahash_complete()
389 result[i] = cpu_to_le32(creq->state[i]); in mv_cesa_ahash_complete()
391 __be32 *result = (void *)ahashreq->result; in mv_cesa_ahash_complete()
394 result[i] = cpu_to_be32(creq->state[i]); in mv_cesa_ahash_complete()
399 atomic_sub(ahashreq->nbytes, &engine->load); in mv_cesa_ahash_complete()
403 struct mv_cesa_engine *engine) in mv_cesa_ahash_prepare() argument
408 creq->base.engine = engine; in mv_cesa_ahash_prepare()
410 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ) in mv_cesa_ahash_prepare()
421 if (creq->last_req) in mv_cesa_ahash_req_cleanup()
426 if (creq->cache_ptr) in mv_cesa_ahash_req_cleanup()
427 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents, in mv_cesa_ahash_req_cleanup()
428 creq->cache, in mv_cesa_ahash_req_cleanup()
429 creq->cache_ptr, in mv_cesa_ahash_req_cleanup()
430 ahashreq->nbytes - creq->cache_ptr); in mv_cesa_ahash_req_cleanup()
453 creq->op_tmpl = *tmpl; in mv_cesa_ahash_init()
454 creq->len = 0; in mv_cesa_ahash_init()
455 creq->algo_le = algo_le; in mv_cesa_ahash_init()
458 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm) in mv_cesa_ahash_cra_init()
462 ctx->base.ops = &mv_cesa_ahash_req_ops; in mv_cesa_ahash_cra_init()
474 if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE && in mv_cesa_ahash_cache_req()
475 !creq->last_req) { in mv_cesa_ahash_cache_req()
478 if (!req->nbytes) in mv_cesa_ahash_cache_req()
481 sg_pcopy_to_buffer(req->src, creq->src_nents, in mv_cesa_ahash_cache_req()
482 creq->cache + creq->cache_ptr, in mv_cesa_ahash_cache_req()
483 req->nbytes, 0); in mv_cesa_ahash_cache_req()
485 creq->cache_ptr += req->nbytes; in mv_cesa_ahash_cache_req()
524 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma; in mv_cesa_ahash_dma_add_cache()
527 if (!creq->cache_ptr) in mv_cesa_ahash_dma_add_cache()
534 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr); in mv_cesa_ahash_dma_add_cache()
538 ahashdreq->cache_dma, in mv_cesa_ahash_dma_add_cache()
539 creq->cache_ptr, in mv_cesa_ahash_dma_add_cache()
550 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma; in mv_cesa_ahash_dma_last_req()
557 * some data outstanding, we can ask the engine to finish the hash. in mv_cesa_ahash_dma_last_req()
559 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) { in mv_cesa_ahash_dma_last_req()
560 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len, in mv_cesa_ahash_dma_last_req()
565 mv_cesa_set_mac_op_total_len(op, creq->len); in mv_cesa_ahash_dma_last_req()
576 return ERR_PTR(-ENOMEM); in mv_cesa_ahash_dma_last_req()
581 * The request is longer than the engine can handle, or we have in mv_cesa_ahash_dma_last_req()
589 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding); in mv_cesa_ahash_dma_last_req()
591 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen); in mv_cesa_ahash_dma_last_req()
596 ahashdreq->padding_dma, in mv_cesa_ahash_dma_last_req()
602 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len, in mv_cesa_ahash_dma_last_req()
615 ahashdreq->padding_dma + in mv_cesa_ahash_dma_last_req()
617 trailerlen - padoff, in mv_cesa_ahash_dma_last_req()
623 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff, in mv_cesa_ahash_dma_last_req()
630 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ? in mv_cesa_ahash_dma_req_init()
632 struct mv_cesa_req *basereq = &creq->base; in mv_cesa_ahash_dma_req_init()
640 basereq->chain.first = NULL; in mv_cesa_ahash_dma_req_init()
641 basereq->chain.last = NULL; in mv_cesa_ahash_dma_req_init()
643 if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl)) in mv_cesa_ahash_dma_req_init()
646 if (creq->src_nents) { in mv_cesa_ahash_dma_req_init()
647 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents, in mv_cesa_ahash_dma_req_init()
650 ret = -ENOMEM; in mv_cesa_ahash_dma_req_init()
655 mv_cesa_tdma_desc_iter_init(&basereq->chain); in mv_cesa_ahash_dma_req_init()
659 * Add the cache (left-over data from a previous block) first. in mv_cesa_ahash_dma_req_init()
662 ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags); in mv_cesa_ahash_dma_req_init()
669 * launch command between each full SRAM block-worth of in mv_cesa_ahash_dma_req_init()
673 ret = mv_cesa_dma_add_op_transfers(&basereq->chain, in mv_cesa_ahash_dma_req_init()
684 op = mv_cesa_dma_add_frag(&basereq->chain, in mv_cesa_ahash_dma_req_init()
685 &creq->op_tmpl, in mv_cesa_ahash_dma_req_init()
702 if (creq->last_req) in mv_cesa_ahash_dma_req_init()
703 op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq, in mv_cesa_ahash_dma_req_init()
706 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl, in mv_cesa_ahash_dma_req_init()
716 * request can be directly processed by the engine, in mv_cesa_ahash_dma_req_init()
720 type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK; in mv_cesa_ahash_dma_req_init()
723 /* Add dummy desc to wait for crypto operation end */ in mv_cesa_ahash_dma_req_init()
724 ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags); in mv_cesa_ahash_dma_req_init()
729 if (!creq->last_req) in mv_cesa_ahash_dma_req_init()
730 creq->cache_ptr = req->nbytes + creq->cache_ptr - in mv_cesa_ahash_dma_req_init()
733 creq->cache_ptr = 0; in mv_cesa_ahash_dma_req_init()
735 basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ; in mv_cesa_ahash_dma_req_init()
738 basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN; in mv_cesa_ahash_dma_req_init()
746 basereq->chain.first->flags |= CESA_TDMA_SET_STATE; in mv_cesa_ahash_dma_req_init()
753 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE); in mv_cesa_ahash_dma_req_init()
765 creq->src_nents = sg_nents_for_len(req->src, req->nbytes); in mv_cesa_ahash_req_init()
766 if (creq->src_nents < 0) { in mv_cesa_ahash_req_init()
767 dev_err(cesa_dev->dev, "Invalid number of src SG"); in mv_cesa_ahash_req_init()
768 return creq->src_nents; in mv_cesa_ahash_req_init()
776 if (cesa_dev->caps->has_tdma) in mv_cesa_ahash_req_init()
785 struct mv_cesa_engine *engine; in mv_cesa_ahash_queue_req() local
796 engine = mv_cesa_select_engine(req->nbytes); in mv_cesa_ahash_queue_req()
797 mv_cesa_ahash_prepare(&req->base, engine); in mv_cesa_ahash_queue_req()
799 ret = mv_cesa_queue_req(&req->base, &creq->base); in mv_cesa_ahash_queue_req()
801 if (mv_cesa_req_needs_cleanup(&req->base, ret)) in mv_cesa_ahash_queue_req()
811 creq->len += req->nbytes; in mv_cesa_ahash_update()
819 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl; in mv_cesa_ahash_final()
821 mv_cesa_set_mac_op_total_len(tmpl, creq->len); in mv_cesa_ahash_final()
822 creq->last_req = true; in mv_cesa_ahash_final()
823 req->nbytes = 0; in mv_cesa_ahash_final()
831 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl; in mv_cesa_ahash_finup()
833 creq->len += req->nbytes; in mv_cesa_ahash_finup()
834 mv_cesa_set_mac_op_total_len(tmpl, creq->len); in mv_cesa_ahash_finup()
835 creq->last_req = true; in mv_cesa_ahash_finup()
850 *len = creq->len; in mv_cesa_ahash_export()
851 memcpy(hash, creq->state, digsize); in mv_cesa_ahash_export()
853 memcpy(cache, creq->cache, creq->cache_ptr); in mv_cesa_ahash_export()
874 mv_cesa_update_op_cfg(&creq->op_tmpl, in mv_cesa_ahash_import()
878 creq->len = len; in mv_cesa_ahash_import()
879 memcpy(creq->state, hash, digsize); in mv_cesa_ahash_import()
880 creq->cache_ptr = 0; in mv_cesa_ahash_import()
886 memcpy(creq->cache, cache, cache_ptr); in mv_cesa_ahash_import()
887 creq->cache_ptr = cache_ptr; in mv_cesa_ahash_import()
901 creq->state[0] = MD5_H0; in mv_cesa_md5_init()
902 creq->state[1] = MD5_H1; in mv_cesa_md5_init()
903 creq->state[2] = MD5_H2; in mv_cesa_md5_init()
904 creq->state[3] = MD5_H3; in mv_cesa_md5_init()
913 return mv_cesa_ahash_export(req, out_state->hash, in mv_cesa_md5_export()
914 &out_state->byte_count, out_state->block); in mv_cesa_md5_export()
921 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count, in mv_cesa_md5_import()
922 in_state->block); in mv_cesa_md5_import()
949 .cra_driver_name = "mv-md5",
971 creq->state[0] = SHA1_H0; in mv_cesa_sha1_init()
972 creq->state[1] = SHA1_H1; in mv_cesa_sha1_init()
973 creq->state[2] = SHA1_H2; in mv_cesa_sha1_init()
974 creq->state[3] = SHA1_H3; in mv_cesa_sha1_init()
975 creq->state[4] = SHA1_H4; in mv_cesa_sha1_init()
984 return mv_cesa_ahash_export(req, out_state->state, &out_state->count, in mv_cesa_sha1_export()
985 out_state->buffer); in mv_cesa_sha1_export()
992 return mv_cesa_ahash_import(req, in_state->state, in_state->count, in mv_cesa_sha1_import()
993 in_state->buffer); in mv_cesa_sha1_import()
1020 .cra_driver_name = "mv-sha1",
1042 creq->state[0] = SHA256_H0; in mv_cesa_sha256_init()
1043 creq->state[1] = SHA256_H1; in mv_cesa_sha256_init()
1044 creq->state[2] = SHA256_H2; in mv_cesa_sha256_init()
1045 creq->state[3] = SHA256_H3; in mv_cesa_sha256_init()
1046 creq->state[4] = SHA256_H4; in mv_cesa_sha256_init()
1047 creq->state[5] = SHA256_H5; in mv_cesa_sha256_init()
1048 creq->state[6] = SHA256_H6; in mv_cesa_sha256_init()
1049 creq->state[7] = SHA256_H7; in mv_cesa_sha256_init()
1069 return mv_cesa_ahash_export(req, out_state->state, &out_state->count, in mv_cesa_sha256_export()
1070 out_state->buf); in mv_cesa_sha256_export()
1077 return mv_cesa_ahash_import(req, in_state->state, in_state->count, in mv_cesa_sha256_import()
1078 in_state->buf); in mv_cesa_sha256_import()
1094 .cra_driver_name = "mv-sha256",
1152 return -ENOMEM; in mv_cesa_ahmac_pad_init()
1171 memset(ipad + keylen, 0, blocksize - keylen); in mv_cesa_ahmac_pad_init()
1199 ret = -ENOMEM; in mv_cesa_ahmac_setkey()
1209 ret = -ENOMEM; in mv_cesa_ahmac_setkey()
1239 ctx->base.ops = &mv_cesa_ahash_req_ops; in mv_cesa_ahmac_cra_init()
1248 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); in mv_cesa_ahmac_md5_init()
1252 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); in mv_cesa_ahmac_md5_init()
1266 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate); in mv_cesa_ahmac_md5_setkey()
1271 ctx->iv[i] = cpu_to_be32(istate.hash[i]); in mv_cesa_ahmac_md5_setkey()
1274 ctx->iv[i + 8] = cpu_to_be32(ostate.hash[i]); in mv_cesa_ahmac_md5_setkey()
1304 .cra_driver_name = "mv-hmac-md5",
1319 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); in mv_cesa_ahmac_sha1_init()
1323 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); in mv_cesa_ahmac_sha1_init()
1337 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate); in mv_cesa_ahmac_sha1_setkey()
1342 ctx->iv[i] = cpu_to_be32(istate.state[i]); in mv_cesa_ahmac_sha1_setkey()
1345 ctx->iv[i + 8] = cpu_to_be32(ostate.state[i]); in mv_cesa_ahmac_sha1_setkey()
1375 .cra_driver_name = "mv-hmac-sha1",
1395 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate); in mv_cesa_ahmac_sha256_setkey()
1400 ctx->iv[i] = cpu_to_be32(istate.state[i]); in mv_cesa_ahmac_sha256_setkey()
1403 ctx->iv[i + 8] = cpu_to_be32(ostate.state[i]); in mv_cesa_ahmac_sha256_setkey()
1410 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm); in mv_cesa_ahmac_sha256_init()
1414 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv)); in mv_cesa_ahmac_sha256_init()
1446 .cra_driver_name = "mv-hmac-sha256",