75 	void __iomem *base_addr;  member
116 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
118 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
120 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
128 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
145 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
161 	return (u64)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
199 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
201 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
221 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
223 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
266 			readl_relaxed(ttccs->ttc.base_addr +  in ttc_rate_change_clocksource_cb()
292 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
302 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
312 			       ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_rate_change_clocksource_cb()
350 	ttccs->ttc.base_addr = base;  in ttc_setup_clocksource()
362 	writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clocksource()
364 		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clocksource()
366 		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clocksource()
433 	ttcce->ttc.base_addr = base;  in ttc_setup_clockevent()
450 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_setup_clockevent()
452 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);  in ttc_setup_clockevent()
453 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);  in ttc_setup_clockevent()