Lines Matching +full:clk +full:- +full:provider
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
14 #include <linux/clk/ti.h>
50 struct clk_hw *clk; member
94 * one is during suspend-resume cycle while timekeeping is in _omap4_is_timeout()
103 if (time->cycles++ < timeout) { in _omap4_is_timeout()
108 if (!ktime_to_ns(time->start)) { in _omap4_is_timeout()
109 time->start = ktime_get(); in _omap4_is_timeout()
113 if (ktime_us_delta(ktime_get(), time->start) < timeout) { in _omap4_is_timeout()
132 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in _omap4_clkctrl_clk_enable() local
137 if (clk->clkdm) { in _omap4_clkctrl_clk_enable()
138 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in _omap4_clkctrl_clk_enable()
143 clk->clkdm_name, ret); in _omap4_clkctrl_clk_enable()
148 if (!clk->enable_bit) in _omap4_clkctrl_clk_enable()
151 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_enable()
154 val |= clk->enable_bit; in _omap4_clkctrl_clk_enable()
156 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); in _omap4_clkctrl_clk_enable()
158 if (test_bit(NO_IDLEST, &clk->flags)) in _omap4_clkctrl_clk_enable()
162 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_enable()
165 return -EBUSY; in _omap4_clkctrl_clk_enable()
174 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in _omap4_clkctrl_clk_disable() local
178 if (!clk->enable_bit) in _omap4_clkctrl_clk_disable()
181 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_disable()
185 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); in _omap4_clkctrl_clk_disable()
187 if (test_bit(NO_IDLEST, &clk->flags)) in _omap4_clkctrl_clk_disable()
191 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_disable()
200 if (clk->clkdm) in _omap4_clkctrl_clk_disable()
201 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in _omap4_clkctrl_clk_disable()
206 struct clk_hw_omap *clk = to_clk_hw_omap(hw); in _omap4_clkctrl_clk_is_enabled() local
209 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_is_enabled()
211 if (val & clk->enable_bit) in _omap4_clkctrl_clk_is_enabled()
227 struct omap_clkctrl_provider *provider = data; in _ti_omap4_clkctrl_xlate() local
230 if (clkspec->args_count != 2) in _ti_omap4_clkctrl_xlate()
231 return ERR_PTR(-EINVAL); in _ti_omap4_clkctrl_xlate()
234 clkspec->args[0], clkspec->args[1]); in _ti_omap4_clkctrl_xlate()
236 list_for_each_entry(iter, &provider->clocks, node) { in _ti_omap4_clkctrl_xlate()
237 if (iter->reg_offset == clkspec->args[0] && in _ti_omap4_clkctrl_xlate()
238 iter->bit_offset == clkspec->args[1]) { in _ti_omap4_clkctrl_xlate()
245 return ERR_PTR(-EINVAL); in _ti_omap4_clkctrl_xlate()
247 return entry->clk; in _ti_omap4_clkctrl_xlate()
258 /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */ in clkctrl_get_clock_name()
260 clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d", in clkctrl_get_clock_name()
265 strreplace(clock_name, '_', '-'); in clkctrl_get_clock_name()
272 return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d", in clkctrl_get_clock_name()
277 return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d", in clkctrl_get_clock_name()
278 np->parent, offset, index); in clkctrl_get_clock_name()
280 /* l4per-clkctrl:1234:0 style naming based on node name */ in clkctrl_get_clock_name()
285 _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider, in _ti_clkctrl_clk_register() argument
292 struct clk *clk; in _ti_clkctrl_clk_register() local
297 ti_clk_get_features()->flags & in _ti_clkctrl_clk_register()
302 ret = -ENOMEM; in _ti_clkctrl_clk_register()
306 clk_hw->init = &init; in _ti_clkctrl_clk_register()
312 clk = of_ti_clk_register(node, clk_hw, init.name); in _ti_clkctrl_clk_register()
313 if (IS_ERR_OR_NULL(clk)) { in _ti_clkctrl_clk_register()
314 ret = -EINVAL; in _ti_clkctrl_clk_register()
318 clkctrl_clk->reg_offset = offset; in _ti_clkctrl_clk_register()
319 clkctrl_clk->bit_offset = bit; in _ti_clkctrl_clk_register()
320 clkctrl_clk->clk = clk_hw; in _ti_clkctrl_clk_register()
322 list_add(&clkctrl_clk->node, &provider->clocks); in _ti_clkctrl_clk_register()
333 _ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider, in _ti_clkctrl_setup_gate() argument
344 clk_hw->enable_bit = data->bit; in _ti_clkctrl_setup_gate()
345 clk_hw->enable_reg.ptr = reg; in _ti_clkctrl_setup_gate()
347 if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset, in _ti_clkctrl_setup_gate()
348 data->bit, data->parents, 1, in _ti_clkctrl_setup_gate()
354 _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider, in _ti_clkctrl_setup_mux() argument
367 pname = data->parents; in _ti_clkctrl_setup_mux()
373 mux->mask = num_parents; in _ti_clkctrl_setup_mux()
374 if (!(mux->flags & CLK_MUX_INDEX_ONE)) in _ti_clkctrl_setup_mux()
375 mux->mask--; in _ti_clkctrl_setup_mux()
377 mux->mask = (1 << fls(mux->mask)) - 1; in _ti_clkctrl_setup_mux()
379 mux->shift = data->bit; in _ti_clkctrl_setup_mux()
380 mux->reg.ptr = reg; in _ti_clkctrl_setup_mux()
382 if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset, in _ti_clkctrl_setup_mux()
383 data->bit, data->parents, num_parents, in _ti_clkctrl_setup_mux()
389 _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider, in _ti_clkctrl_setup_div() argument
395 const struct omap_clkctrl_div_data *div_data = data->data; in _ti_clkctrl_setup_div()
402 div->reg.ptr = reg; in _ti_clkctrl_setup_div()
403 div->shift = data->bit; in _ti_clkctrl_setup_div()
404 div->flags = div_data->flags; in _ti_clkctrl_setup_div()
406 if (div->flags & CLK_DIVIDER_POWER_OF_TWO) in _ti_clkctrl_setup_div()
409 if (ti_clk_parse_divider_data((int *)div_data->dividers, 0, in _ti_clkctrl_setup_div()
410 div_data->max_div, div_flags, in _ti_clkctrl_setup_div()
413 node, offset, data->bit); in _ti_clkctrl_setup_div()
418 if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset, in _ti_clkctrl_setup_div()
419 data->bit, data->parents, 1, in _ti_clkctrl_setup_div()
425 _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider, in _ti_clkctrl_setup_subclks() argument
430 const struct omap_clkctrl_bit_data *bits = data->bit_data; in _ti_clkctrl_setup_subclks()
435 while (bits->bit) { in _ti_clkctrl_setup_subclks()
436 switch (bits->type) { in _ti_clkctrl_setup_subclks()
438 _ti_clkctrl_setup_gate(provider, node, data->offset, in _ti_clkctrl_setup_subclks()
443 _ti_clkctrl_setup_div(provider, node, data->offset, in _ti_clkctrl_setup_subclks()
448 _ti_clkctrl_setup_mux(provider, node, data->offset, in _ti_clkctrl_setup_subclks()
454 bits->type); in _ti_clkctrl_setup_subclks()
468 * Get clock name based on "clock-output-names" property or the
480 if (!of_property_read_string_index(np, "clock-output-names", 0, in clkctrl_get_name()
487 len -= strlen(end); in clkctrl_get_name()
494 if (!strncmp("ti,clkctrl-", compat, prefix_len)) { in clkctrl_get_name()
499 name = kstrdup_and_replace(end, '-', '_', GFP_KERNEL); in clkctrl_get_name()
512 struct omap_clkctrl_provider *provider; in _ti_omap4_clkctrl_setup() local
517 struct clk *clk; in _ti_omap4_clkctrl_setup() local
567 if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP) in _ti_omap4_clkctrl_setup()
570 while (data->addr) { in _ti_omap4_clkctrl_setup()
571 if (addr == data->addr) in _ti_omap4_clkctrl_setup()
577 if (!data->addr) { in _ti_omap4_clkctrl_setup()
582 provider = kzalloc(sizeof(*provider), GFP_KERNEL); in _ti_omap4_clkctrl_setup()
583 if (!provider) in _ti_omap4_clkctrl_setup()
586 provider->base = of_iomap(node, 0); in _ti_omap4_clkctrl_setup()
588 legacy_naming = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT; in _ti_omap4_clkctrl_setup()
591 provider->clkdm_name = kasprintf(GFP_KERNEL, in _ti_omap4_clkctrl_setup()
593 if (!provider->clkdm_name) { in _ti_omap4_clkctrl_setup()
594 kfree(provider); in _ti_omap4_clkctrl_setup()
605 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent); in _ti_omap4_clkctrl_setup()
606 if (!provider->clkdm_name) { in _ti_omap4_clkctrl_setup()
607 kfree(provider); in _ti_omap4_clkctrl_setup()
615 provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0; in _ti_omap4_clkctrl_setup()
617 provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node); in _ti_omap4_clkctrl_setup()
618 if (!provider->clkdm_name) { in _ti_omap4_clkctrl_setup()
619 kfree(provider); in _ti_omap4_clkctrl_setup()
627 provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0; in _ti_omap4_clkctrl_setup()
630 strcat(provider->clkdm_name, "clkdm"); in _ti_omap4_clkctrl_setup()
633 c = provider->clkdm_name; in _ti_omap4_clkctrl_setup()
636 if (*c == '-') in _ti_omap4_clkctrl_setup()
641 INIT_LIST_HEAD(&provider->clocks); in _ti_omap4_clkctrl_setup()
644 reg_data = data->regs; in _ti_omap4_clkctrl_setup()
646 while (reg_data->parent) { in _ti_omap4_clkctrl_setup()
647 if ((reg_data->flags & CLKF_SOC_MASK) && in _ti_omap4_clkctrl_setup()
648 (reg_data->flags & soc_mask) == 0) { in _ti_omap4_clkctrl_setup()
657 hw->enable_reg.ptr = provider->base + reg_data->offset; in _ti_omap4_clkctrl_setup()
659 _ti_clkctrl_setup_subclks(provider, node, reg_data, in _ti_omap4_clkctrl_setup()
660 hw->enable_reg.ptr, clkctrl_name); in _ti_omap4_clkctrl_setup()
662 if (reg_data->flags & CLKF_SW_SUP) in _ti_omap4_clkctrl_setup()
663 hw->enable_bit = MODULEMODE_SWCTRL; in _ti_omap4_clkctrl_setup()
664 if (reg_data->flags & CLKF_HW_SUP) in _ti_omap4_clkctrl_setup()
665 hw->enable_bit = MODULEMODE_HWCTRL; in _ti_omap4_clkctrl_setup()
666 if (reg_data->flags & CLKF_NO_IDLEST) in _ti_omap4_clkctrl_setup()
667 set_bit(NO_IDLEST, &hw->flags); in _ti_omap4_clkctrl_setup()
669 if (reg_data->clkdm_name) in _ti_omap4_clkctrl_setup()
670 hw->clkdm_name = reg_data->clkdm_name; in _ti_omap4_clkctrl_setup()
672 hw->clkdm_name = provider->clkdm_name; in _ti_omap4_clkctrl_setup()
674 init.parent_names = ®_data->parent; in _ti_omap4_clkctrl_setup()
677 if (reg_data->flags & CLKF_SET_RATE_PARENT) in _ti_omap4_clkctrl_setup()
681 reg_data->offset, 0, in _ti_omap4_clkctrl_setup()
691 hw->hw.init = &init; in _ti_omap4_clkctrl_setup()
693 clk = of_ti_clk_register_omap_hw(node, &hw->hw, init.name); in _ti_omap4_clkctrl_setup()
694 if (IS_ERR_OR_NULL(clk)) in _ti_omap4_clkctrl_setup()
697 clkctrl_clk->reg_offset = reg_data->offset; in _ti_omap4_clkctrl_setup()
698 clkctrl_clk->clk = &hw->hw; in _ti_omap4_clkctrl_setup()
700 list_add(&clkctrl_clk->node, &provider->clocks); in _ti_omap4_clkctrl_setup()
705 ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider); in _ti_omap4_clkctrl_setup()
706 if (ret == -EPROBE_DEFER) in _ti_omap4_clkctrl_setup()
707 ti_clk_retry_init(node, provider, _clkctrl_add_provider); in _ti_omap4_clkctrl_setup()
723 * ti_clk_is_in_standby - Check if clkctrl clock is in standby or not
724 * @clk: clock to check standby status for
730 bool ti_clk_is_in_standby(struct clk *clk) in ti_clk_is_in_standby() argument
736 hw = __clk_get_hw(clk); in ti_clk_is_in_standby()
743 val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); in ti_clk_is_in_standby()