1231 	p = DIV_ROUND_UP(pll->params->vco_min, rate);  in _calc_dynamic_ramp_rate()
1261 static unsigned long _clip_vco_min(unsigned long vco_min,  in _clip_vco_min()  argument
1264 	return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;  in _clip_vco_min()
2065 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc()
2068 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllxc()
2116 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre()
2119 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllre()
2137 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
2177 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllm()
2180 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllm()
2221 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc()
2238 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
2361 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss()
2366 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()
2420 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre_tegra210()
2423 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllre_tegra210()
2620 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc_tegra210()
2623 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllc_tegra210()
2668 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss_tegra210()
2671 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllss_tegra210()
2710 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllmb()
2713 		pll_params->vco_min = pll_params->adjust_vco(pll_params,  in tegra_clk_register_pllmb()