Lines Matching +full:0 +full:x3150
44 .l_reg = 0x0004,
45 .m_reg = 0x0008,
46 .n_reg = 0x000c,
47 .config_reg = 0x0014,
48 .mode_reg = 0x0000,
49 .status_reg = 0x001c,
62 .enable_reg = 0x0100,
63 .enable_mask = BIT(0),
75 .l_reg = 0x0044,
76 .m_reg = 0x0048,
77 .n_reg = 0x004c,
78 .config_reg = 0x0050,
79 .mode_reg = 0x0040,
80 .status_reg = 0x005c,
93 .enable_reg = 0x0100,
106 .l_reg = 0x4104,
107 .m_reg = 0x4108,
108 .n_reg = 0x410c,
109 .config_reg = 0x4110,
110 .mode_reg = 0x4100,
111 .status_reg = 0x411c,
123 .l_reg = 0x0084,
124 .m_reg = 0x0088,
125 .n_reg = 0x008c,
126 .config_reg = 0x0090,
127 .mode_reg = 0x0080,
128 .status_reg = 0x009c,
141 .l_reg = 0x00a4,
142 .m_reg = 0x00a8,
143 .n_reg = 0x00ac,
144 .config_reg = 0x00b0,
145 .mode_reg = 0x0080,
146 .status_reg = 0x00bc,
158 { P_XO, 0 },
172 { P_XO, 0 },
190 { P_XO, 0 },
206 { P_XO, 0 },
222 { P_XO, 0 },
240 { P_XO, 0 },
258 { P_XO, 0 },
276 { P_XO, 0 },
292 { P_XO, 0 },
310 { P_XO, 0 },
330 .cmd_rcgr = 0x5000,
342 F(19200000, P_XO, 1, 0, 0),
343 F(37500000, P_GPLL0, 16, 0, 0),
344 F(50000000, P_GPLL0, 12, 0, 0),
345 F(75000000, P_GPLL0, 8, 0, 0),
346 F(100000000, P_GPLL0, 6, 0, 0),
347 F(150000000, P_GPLL0, 4, 0, 0),
348 F(333430000, P_MMPLL1, 3.5, 0, 0),
349 F(400000000, P_MMPLL0, 2, 0, 0),
350 F(466800000, P_MMPLL1, 2.5, 0, 0),
355 .cmd_rcgr = 0x5040,
368 F(19200000, P_XO, 1, 0, 0),
369 F(37500000, P_GPLL0, 16, 0, 0),
370 F(50000000, P_GPLL0, 12, 0, 0),
371 F(75000000, P_GPLL0, 8, 0, 0),
372 F(109090000, P_GPLL0, 5.5, 0, 0),
373 F(150000000, P_GPLL0, 4, 0, 0),
374 F(228570000, P_MMPLL0, 3.5, 0, 0),
375 F(320000000, P_MMPLL0, 2.5, 0, 0),
380 .cmd_rcgr = 0x5090,
393 F(100000000, P_GPLL0, 6, 0, 0),
394 F(200000000, P_MMPLL0, 4, 0, 0),
399 .cmd_rcgr = 0x3090,
412 .cmd_rcgr = 0x3100,
425 .cmd_rcgr = 0x3160,
438 .cmd_rcgr = 0x31c0,
451 F(37500000, P_GPLL0, 16, 0, 0),
452 F(50000000, P_GPLL0, 12, 0, 0),
453 F(60000000, P_GPLL0, 10, 0, 0),
454 F(80000000, P_GPLL0, 7.5, 0, 0),
455 F(100000000, P_GPLL0, 6, 0, 0),
456 F(109090000, P_GPLL0, 5.5, 0, 0),
457 F(133330000, P_GPLL0, 4.5, 0, 0),
458 F(200000000, P_GPLL0, 3, 0, 0),
459 F(228570000, P_MMPLL0, 3.5, 0, 0),
460 F(266670000, P_MMPLL0, 3, 0, 0),
461 F(320000000, P_MMPLL0, 2.5, 0, 0),
462 F(465000000, P_MMPLL4, 2, 0, 0),
463 F(600000000, P_GPLL0, 1, 0, 0),
468 .cmd_rcgr = 0x3600,
481 .cmd_rcgr = 0x3620,
494 F(37500000, P_GPLL0, 16, 0, 0),
495 F(60000000, P_GPLL0, 10, 0, 0),
496 F(75000000, P_GPLL0, 8, 0, 0),
497 F(85710000, P_GPLL0, 7, 0, 0),
498 F(100000000, P_GPLL0, 6, 0, 0),
499 F(150000000, P_GPLL0, 4, 0, 0),
500 F(160000000, P_MMPLL0, 5, 0, 0),
501 F(200000000, P_MMPLL0, 4, 0, 0),
502 F(228570000, P_MMPLL0, 3.5, 0, 0),
503 F(300000000, P_GPLL0, 2, 0, 0),
504 F(320000000, P_MMPLL0, 2.5, 0, 0),
509 .cmd_rcgr = 0x2040,
522 .cmd_rcgr = 0x4000,
534 F(75000000, P_GPLL0, 8, 0, 0),
535 F(133330000, P_GPLL0, 4.5, 0, 0),
536 F(200000000, P_GPLL0, 3, 0, 0),
537 F(228570000, P_MMPLL0, 3.5, 0, 0),
538 F(266670000, P_MMPLL0, 3, 0, 0),
539 F(320000000, P_MMPLL0, 2.5, 0, 0),
544 .cmd_rcgr = 0x3500,
557 .cmd_rcgr = 0x3520,
570 .cmd_rcgr = 0x3540,
583 .cmd_rcgr = 0x2000,
597 .cmd_rcgr = 0x2020,
611 F(50000000, P_GPLL0, 12, 0, 0),
612 F(100000000, P_GPLL0, 6, 0, 0),
613 F(133330000, P_GPLL0, 4.5, 0, 0),
614 F(200000000, P_MMPLL0, 4, 0, 0),
615 F(266670000, P_MMPLL0, 3, 0, 0),
616 F(465000000, P_MMPLL3, 2, 0, 0),
621 .cmd_rcgr = 0x1000,
635 F(150000000, P_GPLL0, 4, 0, 0),
636 F(320000000, P_MMPLL0, 2.5, 0, 0),
641 .cmd_rcgr = 0x2430,
654 F(19200000, P_XO, 1, 0, 0),
659 .cmd_rcgr = 0x3300,
683 .cmd_rcgr = 0x3420,
697 .cmd_rcgr = 0x3450,
711 F(4800000, P_XO, 4, 0, 0),
714 F(9600000, P_XO, 2, 0, 0),
716 F(19200000, P_XO, 1, 0, 0),
719 F(48000000, P_GPLL0, 12.5, 0, 0),
720 F(64000000, P_MMPLL0, 12.5, 0, 0),
725 .cmd_rcgr = 0x3360,
739 .cmd_rcgr = 0x3390,
753 .cmd_rcgr = 0x33c0,
767 .cmd_rcgr = 0x33f0,
781 F(100000000, P_GPLL0, 6, 0, 0),
782 F(200000000, P_MMPLL0, 4, 0, 0),
787 .cmd_rcgr = 0x3000,
800 .cmd_rcgr = 0x3030,
813 .cmd_rcgr = 0x3060,
826 F(133330000, P_GPLL0, 4.5, 0, 0),
827 F(266670000, P_MMPLL0, 3, 0, 0),
828 F(320000000, P_MMPLL0, 2.5, 0, 0),
829 F(372000000, P_MMPLL4, 2.5, 0, 0),
830 F(465000000, P_MMPLL4, 2, 0, 0),
831 F(600000000, P_GPLL0, 1, 0, 0),
836 .cmd_rcgr = 0x3640,
849 .cmd_rcgr = 0x2120,
862 .cmd_rcgr = 0x2140,
875 F(19200000, P_XO, 1, 0, 0),
880 .cmd_rcgr = 0x20e0,
893 F(135000000, P_EDPLINK, 2, 0, 0),
894 F(270000000, P_EDPLINK, 11, 0, 0),
899 .cmd_rcgr = 0x20c0,
918 .cmd_rcgr = 0x20a0,
932 F(19200000, P_XO, 1, 0, 0),
937 .cmd_rcgr = 0x2160,
950 .cmd_rcgr = 0x2180,
968 .cmd_rcgr = 0x2060,
982 F(19200000, P_XO, 1, 0, 0),
987 .cmd_rcgr = 0x2100,
1000 F(19200000, P_XO, 1, 0, 0),
1005 .cmd_rcgr = 0x2080,
1018 F(50000000, P_GPLL0, 12, 0, 0),
1023 .cmd_rcgr = 0x4060,
1036 F(19200000, P_XO, 1, 0, 0),
1041 .cmd_rcgr = 0x4090,
1054 F(50000000, P_GPLL0, 12, 0, 0),
1055 F(100000000, P_GPLL0, 6, 0, 0),
1056 F(133330000, P_GPLL0, 4.5, 0, 0),
1057 F(200000000, P_MMPLL0, 4, 0, 0),
1058 F(266670000, P_MMPLL0, 3, 0, 0),
1059 F(465000000, P_MMPLL3, 2, 0, 0),
1064 .cmd_rcgr = 0x1320,
1077 F(50000000, P_GPLL0, 12, 0, 0),
1078 F(100000000, P_GPLL0, 6, 0, 0),
1079 F(200000000, P_MMPLL0, 4, 0, 0),
1080 F(320000000, P_MMPLL0, 2.5, 0, 0),
1081 F(400000000, P_MMPLL0, 2, 0, 0),
1086 .cmd_rcgr = 0x1300,
1099 F(40000000, P_GPLL0, 15, 0, 0),
1100 F(80000000, P_MMPLL0, 10, 0, 0),
1105 .cmd_rcgr = 0x1340,
1118 .halt_reg = 0x5104,
1120 .enable_reg = 0x5104,
1121 .enable_mask = BIT(0),
1135 .halt_reg = 0x5100,
1137 .enable_reg = 0x5100,
1138 .enable_mask = BIT(0),
1152 .halt_reg = 0x2414,
1154 .enable_reg = 0x2414,
1155 .enable_mask = BIT(0),
1169 .halt_reg = 0x2418,
1171 .enable_reg = 0x2418,
1172 .enable_mask = BIT(0),
1186 .halt_reg = 0x2410,
1188 .enable_reg = 0x2410,
1189 .enable_mask = BIT(0),
1203 .halt_reg = 0x241c,
1205 .enable_reg = 0x241c,
1206 .enable_mask = BIT(0),
1220 .halt_reg = 0x2420,
1222 .enable_reg = 0x2420,
1223 .enable_mask = BIT(0),
1237 .halt_reg = 0x2404,
1239 .enable_reg = 0x2404,
1240 .enable_mask = BIT(0),
1254 .halt_reg = 0x348c,
1256 .enable_reg = 0x348c,
1257 .enable_mask = BIT(0),
1271 .halt_reg = 0x3348,
1273 .enable_reg = 0x3348,
1274 .enable_mask = BIT(0),
1287 .halt_reg = 0x3344,
1289 .enable_reg = 0x3344,
1290 .enable_mask = BIT(0),
1304 .halt_reg = 0x30bc,
1306 .enable_reg = 0x30bc,
1307 .enable_mask = BIT(0),
1320 .halt_reg = 0x30b4,
1322 .enable_reg = 0x30b4,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0x30c4,
1339 .enable_reg = 0x30c4,
1340 .enable_mask = BIT(0),
1354 .halt_reg = 0x30e4,
1356 .enable_reg = 0x30e4,
1357 .enable_mask = BIT(0),
1371 .halt_reg = 0x30d4,
1373 .enable_reg = 0x30d4,
1374 .enable_mask = BIT(0),
1388 .halt_reg = 0x3128,
1390 .enable_reg = 0x3128,
1391 .enable_mask = BIT(0),
1405 .halt_reg = 0x3124,
1407 .enable_reg = 0x3124,
1408 .enable_mask = BIT(0),
1422 .halt_reg = 0x3134,
1424 .enable_reg = 0x3134,
1425 .enable_mask = BIT(0),
1439 .halt_reg = 0x3154,
1441 .enable_reg = 0x3154,
1442 .enable_mask = BIT(0),
1456 .halt_reg = 0x3144,
1458 .enable_reg = 0x3144,
1459 .enable_mask = BIT(0),
1473 .halt_reg = 0x3188,
1475 .enable_reg = 0x3188,
1476 .enable_mask = BIT(0),
1489 .halt_reg = 0x3184,
1491 .enable_reg = 0x3184,
1492 .enable_mask = BIT(0),
1506 .halt_reg = 0x3194,
1508 .enable_reg = 0x3194,
1509 .enable_mask = BIT(0),
1523 .halt_reg = 0x31b4,
1525 .enable_reg = 0x31b4,
1526 .enable_mask = BIT(0),
1540 .halt_reg = 0x31a4,
1542 .enable_reg = 0x31a4,
1543 .enable_mask = BIT(0),
1557 .halt_reg = 0x31e8,
1559 .enable_reg = 0x31e8,
1560 .enable_mask = BIT(0),
1573 .halt_reg = 0x31e4,
1575 .enable_reg = 0x31e4,
1576 .enable_mask = BIT(0),
1590 .halt_reg = 0x31f4,
1592 .enable_reg = 0x31f4,
1593 .enable_mask = BIT(0),
1607 .halt_reg = 0x3214,
1609 .enable_reg = 0x3214,
1610 .enable_mask = BIT(0),
1624 .halt_reg = 0x3204,
1626 .enable_reg = 0x3204,
1627 .enable_mask = BIT(0),
1641 .halt_reg = 0x3704,
1643 .enable_reg = 0x3704,
1644 .enable_mask = BIT(0),
1658 .halt_reg = 0x3714,
1660 .enable_reg = 0x3714,
1661 .enable_mask = BIT(0),
1675 .halt_reg = 0x3444,
1677 .enable_reg = 0x3444,
1678 .enable_mask = BIT(0),
1692 .halt_reg = 0x3474,
1694 .enable_reg = 0x3474,
1695 .enable_mask = BIT(0),
1709 .halt_reg = 0x3224,
1711 .enable_reg = 0x3224,
1712 .enable_mask = BIT(0),
1726 .halt_reg = 0x35a8,
1728 .enable_reg = 0x35a8,
1729 .enable_mask = BIT(0),
1743 .halt_reg = 0x35ac,
1745 .enable_reg = 0x35ac,
1746 .enable_mask = BIT(0),
1760 .halt_reg = 0x35b0,
1762 .enable_reg = 0x35b0,
1763 .enable_mask = BIT(0),
1777 .halt_reg = 0x35b4,
1779 .enable_reg = 0x35b4,
1780 .enable_mask = BIT(0),
1793 .halt_reg = 0x35b8,
1795 .enable_reg = 0x35b8,
1796 .enable_mask = BIT(0),
1809 .halt_reg = 0x3384,
1811 .enable_reg = 0x3384,
1812 .enable_mask = BIT(0),
1826 .halt_reg = 0x33b4,
1828 .enable_reg = 0x33b4,
1829 .enable_mask = BIT(0),
1843 .halt_reg = 0x33e4,
1845 .enable_reg = 0x33e4,
1846 .enable_mask = BIT(0),
1860 .halt_reg = 0x3414,
1862 .enable_reg = 0x3414,
1863 .enable_mask = BIT(0),
1877 .halt_reg = 0x3494,
1879 .enable_reg = 0x3494,
1880 .enable_mask = BIT(0),
1893 .halt_reg = 0x3024,
1895 .enable_reg = 0x3024,
1896 .enable_mask = BIT(0),
1910 .halt_reg = 0x3054,
1912 .enable_reg = 0x3054,
1913 .enable_mask = BIT(0),
1927 .halt_reg = 0x3084,
1929 .enable_reg = 0x3084,
1930 .enable_mask = BIT(0),
1944 .halt_reg = 0x3484,
1946 .enable_reg = 0x3484,
1947 .enable_mask = BIT(0),
1961 .halt_reg = 0x36b4,
1963 .enable_reg = 0x36b4,
1964 .enable_mask = BIT(0),
1978 .halt_reg = 0x36b0,
1980 .enable_reg = 0x36b0,
1981 .enable_mask = BIT(0),
1995 .halt_reg = 0x36a8,
1997 .enable_reg = 0x36a8,
1998 .enable_mask = BIT(0),
2012 .halt_reg = 0x36ac,
2014 .enable_reg = 0x36ac,
2015 .enable_mask = BIT(0),
2029 .halt_reg = 0x36b8,
2031 .enable_reg = 0x36b8,
2032 .enable_mask = BIT(0),
2046 .halt_reg = 0x36bc,
2048 .enable_reg = 0x36bc,
2049 .enable_mask = BIT(0),
2063 .halt_reg = 0x2308,
2065 .enable_reg = 0x2308,
2066 .enable_mask = BIT(0),
2080 .halt_reg = 0x2310,
2082 .enable_reg = 0x2310,
2083 .enable_mask = BIT(0),
2097 .halt_reg = 0x233c,
2099 .enable_reg = 0x233c,
2100 .enable_mask = BIT(0),
2114 .halt_reg = 0x2340,
2116 .enable_reg = 0x2340,
2117 .enable_mask = BIT(0),
2131 .halt_reg = 0x2334,
2133 .enable_reg = 0x2334,
2134 .enable_mask = BIT(0),
2148 .halt_reg = 0x2330,
2150 .enable_reg = 0x2330,
2151 .enable_mask = BIT(0),
2165 .halt_reg = 0x232c,
2167 .enable_reg = 0x232c,
2168 .enable_mask = BIT(0),
2182 .halt_reg = 0x2344,
2184 .enable_reg = 0x2344,
2185 .enable_mask = BIT(0),
2199 .halt_reg = 0x2348,
2201 .enable_reg = 0x2348,
2202 .enable_mask = BIT(0),
2216 .halt_reg = 0x2324,
2218 .enable_reg = 0x2324,
2219 .enable_mask = BIT(0),
2233 .halt_reg = 0x230c,
2235 .enable_reg = 0x230c,
2236 .enable_mask = BIT(0),
2250 .halt_reg = 0x2338,
2252 .enable_reg = 0x2338,
2253 .enable_mask = BIT(0),
2267 .halt_reg = 0x231c,
2269 .enable_reg = 0x231c,
2270 .enable_mask = BIT(0),
2284 .halt_reg = 0x2320,
2286 .enable_reg = 0x2320,
2287 .enable_mask = BIT(0),
2301 .halt_reg = 0x2314,
2303 .enable_reg = 0x2314,
2304 .enable_mask = BIT(0),
2318 .halt_reg = 0x2318,
2320 .enable_reg = 0x2318,
2321 .enable_mask = BIT(0),
2335 .halt_reg = 0x2328,
2337 .enable_reg = 0x2328,
2338 .enable_mask = BIT(0),
2352 .halt_reg = 0x4088,
2354 .enable_reg = 0x4088,
2355 .enable_mask = BIT(0),
2369 .halt_reg = 0x4084,
2371 .enable_reg = 0x4084,
2372 .enable_mask = BIT(0),
2386 .halt_reg = 0x502c,
2388 .enable_reg = 0x502c,
2389 .enable_mask = BIT(0),
2403 .halt_reg = 0x5024,
2405 .enable_reg = 0x5024,
2406 .enable_mask = BIT(0),
2420 .halt_reg = 0x5028,
2422 .enable_reg = 0x5028,
2423 .enable_mask = BIT(0),
2437 .halt_reg = 0x506c,
2439 .enable_reg = 0x506c,
2440 .enable_mask = BIT(0),
2454 .halt_reg = 0x5064,
2456 .enable_reg = 0x5064,
2457 .enable_mask = BIT(0),
2471 .halt_reg = 0x405c,
2473 .enable_reg = 0x405c,
2474 .enable_mask = BIT(0),
2488 .halt_reg = 0x4058,
2490 .enable_reg = 0x4058,
2491 .enable_mask = BIT(0),
2505 .halt_reg = 0x402c,
2507 .enable_reg = 0x402c,
2508 .enable_mask = BIT(0),
2522 .halt_reg = 0x4028,
2524 .enable_reg = 0x4028,
2525 .enable_mask = BIT(0),
2539 .halt_reg = 0x40b0,
2541 .enable_reg = 0x40b0,
2542 .enable_mask = BIT(0),
2556 .halt_reg = 0x403c,
2558 .enable_reg = 0x403c,
2559 .enable_mask = BIT(0),
2573 .halt_reg = 0x1030,
2575 .enable_reg = 0x1030,
2576 .enable_mask = BIT(0),
2590 .halt_reg = 0x1034,
2592 .enable_reg = 0x1034,
2593 .enable_mask = BIT(0),
2607 .halt_reg = 0x1048,
2609 .enable_reg = 0x1048,
2610 .enable_mask = BIT(0),
2624 .halt_reg = 0x104c,
2626 .enable_reg = 0x104c,
2627 .enable_mask = BIT(0),
2641 .halt_reg = 0x1038,
2643 .enable_reg = 0x1038,
2644 .enable_mask = BIT(0),
2658 .halt_reg = 0x1028,
2660 .enable_reg = 0x1028,
2661 .enable_mask = BIT(0),
2675 .halt_reg = 0x1430,
2677 .enable_reg = 0x1430,
2678 .enable_mask = BIT(0),
2692 .halt_reg = 0x143c,
2694 .enable_reg = 0x143c,
2695 .enable_mask = BIT(0),
2709 .halt_reg = 0x1440,
2711 .enable_reg = 0x1440,
2712 .enable_mask = BIT(0),
2726 .halt_reg = 0x1434,
2728 .enable_reg = 0x1434,
2729 .enable_mask = BIT(0),
2743 .halt_reg = 0x142c,
2745 .enable_reg = 0x142c,
2746 .enable_mask = BIT(0),
2760 .halt_reg = 0x1438,
2762 .enable_reg = 0x1438,
2763 .enable_mask = BIT(0),
2777 .halt_reg = 0x1428,
2779 .enable_reg = 0x1428,
2780 .enable_mask = BIT(0),
2797 .vco_val = 0x0,
2798 .vco_mask = 0x3 << 20,
2799 .pre_div_val = 0x0,
2800 .pre_div_mask = 0x7 << 12,
2801 .post_div_val = 0x0,
2802 .post_div_mask = 0x3 << 8,
2804 .main_output_mask = BIT(0),
2811 .vco_val = 0x0,
2812 .vco_mask = 0x3 << 20,
2813 .pre_div_val = 0x0,
2814 .pre_div_mask = 0x7 << 12,
2815 .post_div_val = 0x0,
2816 .post_div_mask = 0x3 << 8,
2818 .main_output_mask = BIT(0),
2823 .gdscr = 0x1024,
2831 .gdscr = 0x1040,
2839 .gdscr = 0x1044,
2847 .gdscr = 0x2304,
2848 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2857 .gdscr = 0x35a4,
2865 .gdscr = 0x36a4,
2866 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
2875 .gdscr = 0x4024,
2876 .cxcs = (unsigned int []){ 0x4028 },
2885 .gdscr = 0x4034,
3046 [MMSS_SPDM_RESET] = { 0x0200 },
3047 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3048 [VENUS0_RESET] = { 0x1020 },
3049 [VPU_RESET] = { 0x1400 },
3050 [MDSS_RESET] = { 0x2300 },
3051 [AVSYNC_RESET] = { 0x2400 },
3052 [CAMSS_PHY0_RESET] = { 0x3020 },
3053 [CAMSS_PHY1_RESET] = { 0x3050 },
3054 [CAMSS_PHY2_RESET] = { 0x3080 },
3055 [CAMSS_CSI0_RESET] = { 0x30b0 },
3056 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3057 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3058 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3059 [CAMSS_CSI1_RESET] = { 0x3120 },
3060 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3061 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3062 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3063 [CAMSS_CSI2_RESET] = { 0x3180 },
3064 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3065 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3066 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3067 [CAMSS_CSI3_RESET] = { 0x31e0 },
3068 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3069 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3070 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3071 [CAMSS_ISPIF_RESET] = { 0x3220 },
3072 [CAMSS_CCI_RESET] = { 0x3340 },
3073 [CAMSS_MCLK0_RESET] = { 0x3380 },
3074 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3075 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3076 [CAMSS_MCLK3_RESET] = { 0x3410 },
3077 [CAMSS_GP0_RESET] = { 0x3440 },
3078 [CAMSS_GP1_RESET] = { 0x3470 },
3079 [CAMSS_TOP_RESET] = { 0x3480 },
3080 [CAMSS_AHB_RESET] = { 0x3488 },
3081 [CAMSS_MICRO_RESET] = { 0x3490 },
3082 [CAMSS_JPEG_RESET] = { 0x35a0 },
3083 [CAMSS_VFE_RESET] = { 0x36a0 },
3084 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3085 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3086 [OXILI_RESET] = { 0x4020 },
3087 [OXILICX_RESET] = { 0x4030 },
3088 [OCMEMCX_RESET] = { 0x4050 },
3089 [MMSS_RBCRP_RESET] = { 0x4080 },
3090 [MMSSNOCAHB_RESET] = { 0x5020 },
3091 [MMSSNOCAXI_RESET] = { 0x5060 },
3109 .max_register = 0x5104,
3142 return 0; in mmcc_apq8084_probe()