Lines Matching +full:0 +full:x33000
36 .offset = 0x0,
39 .enable_reg = 0x52000,
40 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
79 .offset = 0x1a000,
82 .enable_reg = 0x52000,
97 .offset = 0x1c000,
100 .enable_reg = 0x52000,
115 { P_BI_TCXO, 0 },
127 { P_BI_TCXO, 0 },
141 { P_BI_TCXO, 0 },
151 { P_BI_TCXO, 0 },
161 { P_BI_TCXO, 0 },
169 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
197 { P_BI_TCXO, 0 },
211 F(19200000, P_BI_TCXO, 1, 0, 0),
212 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
213 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
218 .cmd_rcgr = 0x48014,
219 .mnd_width = 0,
233 F(19200000, P_BI_TCXO, 1, 0, 0),
234 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
235 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
236 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
241 .cmd_rcgr = 0x6038,
242 .mnd_width = 0,
258 F(19200000, P_BI_TCXO, 1, 0, 0),
259 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
260 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
261 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
262 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
267 .cmd_rcgr = 0x601c,
282 F(19200000, P_BI_TCXO, 1, 0, 0),
283 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
284 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
285 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
286 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
291 .cmd_rcgr = 0x64004,
306 .cmd_rcgr = 0x65004,
321 .cmd_rcgr = 0x66004,
336 F(9600000, P_BI_TCXO, 2, 0, 0),
337 F(19200000, P_BI_TCXO, 1, 0, 0),
342 .cmd_rcgr = 0x6b02c,
357 .cmd_rcgr = 0x8d02c,
372 F(19200000, P_BI_TCXO, 1, 0, 0),
373 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
378 .cmd_rcgr = 0x6f014,
379 .mnd_width = 0,
393 F(9600000, P_BI_TCXO, 2, 0, 0),
394 F(19200000, P_BI_TCXO, 1, 0, 0),
395 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
400 .cmd_rcgr = 0x33010,
401 .mnd_width = 0,
415 F(19200000, P_BI_TCXO, 1, 0, 0),
416 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
417 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
418 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
423 .cmd_rcgr = 0x4b008,
424 .mnd_width = 0,
440 F(19200000, P_BI_TCXO, 1, 0, 0),
447 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
451 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
457 .cmd_rcgr = 0x17148,
472 .cmd_rcgr = 0x17278,
487 .cmd_rcgr = 0x173a8,
502 .cmd_rcgr = 0x174d8,
517 .cmd_rcgr = 0x17608,
532 .cmd_rcgr = 0x17738,
547 .cmd_rcgr = 0x17868,
562 .cmd_rcgr = 0x17998,
577 .cmd_rcgr = 0x18148,
592 .cmd_rcgr = 0x18278,
607 .cmd_rcgr = 0x183a8,
622 .cmd_rcgr = 0x184d8,
637 .cmd_rcgr = 0x18608,
652 .cmd_rcgr = 0x18738,
667 .cmd_rcgr = 0x1e148,
682 .cmd_rcgr = 0x1e278,
697 .cmd_rcgr = 0x1e3a8,
712 .cmd_rcgr = 0x1e4d8,
727 .cmd_rcgr = 0x1e608,
742 .cmd_rcgr = 0x1e738,
758 F(9600000, P_BI_TCXO, 2, 0, 0),
759 F(19200000, P_BI_TCXO, 1, 0, 0),
761 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
762 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
763 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
768 .cmd_rcgr = 0x1400c,
784 F(9600000, P_BI_TCXO, 2, 0, 0),
785 F(19200000, P_BI_TCXO, 1, 0, 0),
787 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
788 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
793 .cmd_rcgr = 0x1600c,
813 .cmd_rcgr = 0x36010,
828 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
829 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
830 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
831 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
832 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
837 .cmd_rcgr = 0x75020,
852 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
853 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
854 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
855 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
860 .cmd_rcgr = 0x75060,
861 .mnd_width = 0,
875 F(19200000, P_BI_TCXO, 1, 0, 0),
880 .cmd_rcgr = 0x75094,
881 .mnd_width = 0,
895 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
896 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
897 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
902 .cmd_rcgr = 0x75078,
903 .mnd_width = 0,
917 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
918 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
919 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
920 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
921 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
926 .cmd_rcgr = 0x77020,
941 .cmd_rcgr = 0x77060,
942 .mnd_width = 0,
956 .cmd_rcgr = 0x77094,
957 .mnd_width = 0,
971 .cmd_rcgr = 0x77078,
972 .mnd_width = 0,
986 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
987 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
988 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
989 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
990 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
995 .cmd_rcgr = 0xf01c,
1010 F(19200000, P_BI_TCXO, 1, 0, 0),
1011 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1012 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1017 .cmd_rcgr = 0xf034,
1018 .mnd_width = 0,
1032 .cmd_rcgr = 0x1001c,
1047 .cmd_rcgr = 0x10034,
1048 .mnd_width = 0,
1062 .cmd_rcgr = 0xf060,
1063 .mnd_width = 0,
1077 .cmd_rcgr = 0x10060,
1078 .mnd_width = 0,
1092 .halt_reg = 0x90018,
1095 .enable_reg = 0x90018,
1096 .enable_mask = BIT(0),
1105 .halt_reg = 0x750c0,
1107 .hwcg_reg = 0x750c0,
1110 .enable_reg = 0x750c0,
1111 .enable_mask = BIT(0),
1124 .halt_reg = 0x750c0,
1126 .hwcg_reg = 0x750c0,
1129 .enable_reg = 0x750c0,
1143 .halt_reg = 0x770c0,
1145 .hwcg_reg = 0x770c0,
1148 .enable_reg = 0x770c0,
1149 .enable_mask = BIT(0),
1162 .halt_reg = 0x770c0,
1164 .hwcg_reg = 0x770c0,
1167 .enable_reg = 0x770c0,
1181 .halt_reg = 0xf07c,
1184 .enable_reg = 0xf07c,
1185 .enable_mask = BIT(0),
1198 .halt_reg = 0x1007c,
1201 .enable_reg = 0x1007c,
1202 .enable_mask = BIT(0),
1215 .halt_reg = 0x38004,
1217 .hwcg_reg = 0x38004,
1220 .enable_reg = 0x52004,
1234 .halt_reg = 0xb008,
1236 .hwcg_reg = 0xb008,
1239 .enable_reg = 0xb008,
1240 .enable_mask = BIT(0),
1250 .halt_reg = 0xb030,
1253 .enable_reg = 0xb030,
1254 .enable_mask = BIT(0),
1263 .halt_reg = 0xb034,
1266 .enable_reg = 0xb034,
1267 .enable_mask = BIT(0),
1277 .halt_reg = 0xb044,
1280 .enable_reg = 0xb044,
1281 .enable_mask = BIT(0),
1291 .halt_reg = 0xf078,
1294 .enable_reg = 0xf078,
1295 .enable_mask = BIT(0),
1308 .halt_reg = 0x10078,
1311 .enable_reg = 0x10078,
1312 .enable_mask = BIT(0),
1325 .halt_reg = 0x48000,
1328 .enable_reg = 0x52004,
1343 .halt_reg = 0x48190,
1346 .enable_reg = 0x48190,
1347 .enable_mask = BIT(0),
1358 .halt_reg = 0x48004,
1360 .hwcg_reg = 0x48004,
1363 .enable_reg = 0x52004,
1375 .halt_reg = 0x48008,
1378 .enable_reg = 0x48008,
1379 .enable_mask = BIT(0),
1388 .halt_reg = 0x71154,
1391 .enable_reg = 0x71154,
1392 .enable_mask = BIT(0),
1405 .halt_reg = 0xb00c,
1407 .hwcg_reg = 0xb00c,
1410 .enable_reg = 0xb00c,
1411 .enable_mask = BIT(0),
1421 .halt_reg = 0xb038,
1424 .enable_reg = 0xb038,
1425 .enable_mask = BIT(0),
1434 .halt_reg = 0xb03c,
1437 .enable_reg = 0xb03c,
1438 .enable_mask = BIT(0),
1448 .halt_reg = 0xb048,
1451 .enable_reg = 0xb048,
1452 .enable_mask = BIT(0),
1462 .halt_reg = 0x6010,
1465 .enable_reg = 0x6010,
1466 .enable_mask = BIT(0),
1475 .halt_reg = 0x6034,
1478 .enable_reg = 0x6034,
1479 .enable_mask = BIT(0),
1492 .halt_reg = 0x6018,
1495 .enable_reg = 0x6018,
1496 .enable_mask = BIT(0),
1509 .halt_reg = 0x6014,
1511 .hwcg_reg = 0x6014,
1514 .enable_reg = 0x6014,
1515 .enable_mask = BIT(0),
1524 .halt_reg = 0x64000,
1527 .enable_reg = 0x64000,
1528 .enable_mask = BIT(0),
1541 .halt_reg = 0x65000,
1544 .enable_reg = 0x65000,
1545 .enable_mask = BIT(0),
1558 .halt_reg = 0x66000,
1561 .enable_reg = 0x66000,
1562 .enable_mask = BIT(0),
1575 .halt_reg = 0x71004,
1577 .hwcg_reg = 0x71004,
1580 .enable_reg = 0x71004,
1581 .enable_mask = BIT(0),
1594 .enable_reg = 0x52004,
1610 .enable_reg = 0x52004,
1624 .halt_reg = 0x8c010,
1627 .enable_reg = 0x8c010,
1628 .enable_mask = BIT(0),
1637 .halt_reg = 0x7100c,
1640 .enable_reg = 0x7100c,
1641 .enable_mask = BIT(0),
1650 .halt_reg = 0x71018,
1653 .enable_reg = 0x71018,
1654 .enable_mask = BIT(0),
1663 .halt_reg = 0x4d010,
1666 .enable_reg = 0x4d010,
1667 .enable_mask = BIT(0),
1676 .halt_reg = 0x4d008,
1679 .enable_reg = 0x4d008,
1680 .enable_mask = BIT(0),
1689 .halt_reg = 0x4d004,
1691 .hwcg_reg = 0x4d004,
1694 .enable_reg = 0x4d004,
1695 .enable_mask = BIT(0),
1708 .enable_reg = 0x52004,
1724 .enable_reg = 0x52004,
1738 .halt_reg = 0x4d00c,
1741 .enable_reg = 0x4d00c,
1742 .enable_mask = BIT(0),
1751 .halt_reg = 0x6f02c,
1754 .enable_reg = 0x6f02c,
1755 .enable_mask = BIT(0),
1768 .halt_reg = 0x6f030,
1771 .enable_reg = 0x6f030,
1772 .enable_mask = BIT(0),
1785 .halt_reg = 0x6b020,
1788 .enable_reg = 0x5200c,
1802 .halt_reg = 0x6b01c,
1804 .hwcg_reg = 0x6b01c,
1807 .enable_reg = 0x5200c,
1817 .halt_reg = 0x8c00c,
1820 .enable_reg = 0x8c00c,
1821 .enable_mask = BIT(0),
1830 .halt_reg = 0x6b018,
1833 .enable_reg = 0x5200c,
1844 .halt_reg = 0x6b024,
1847 .enable_reg = 0x5200c,
1857 .halt_reg = 0x6b014,
1859 .hwcg_reg = 0x6b014,
1862 .enable_reg = 0x5200c,
1863 .enable_mask = BIT(0),
1872 .halt_reg = 0x6b010,
1875 .enable_reg = 0x5200c,
1885 .halt_reg = 0x8d020,
1888 .enable_reg = 0x52004,
1902 .halt_reg = 0x8d01c,
1904 .hwcg_reg = 0x8d01c,
1907 .enable_reg = 0x52004,
1917 .halt_reg = 0x8c02c,
1920 .enable_reg = 0x8c02c,
1921 .enable_mask = BIT(0),
1930 .halt_reg = 0x8d018,
1933 .enable_reg = 0x52004,
1944 .halt_reg = 0x8d024,
1947 .enable_reg = 0x52004,
1957 .halt_reg = 0x8d014,
1959 .hwcg_reg = 0x8d014,
1962 .enable_reg = 0x52004,
1972 .halt_reg = 0x8d010,
1975 .enable_reg = 0x52004,
1985 .halt_reg = 0x6f004,
1988 .enable_reg = 0x6f004,
1989 .enable_mask = BIT(0),
2002 .halt_reg = 0x3300c,
2005 .enable_reg = 0x3300c,
2006 .enable_mask = BIT(0),
2019 .halt_reg = 0x33004,
2021 .hwcg_reg = 0x33004,
2024 .enable_reg = 0x33004,
2025 .enable_mask = BIT(0),
2034 .halt_reg = 0x33008,
2037 .enable_reg = 0x33008,
2038 .enable_mask = BIT(0),
2047 .halt_reg = 0x34004,
2050 .enable_reg = 0x52004,
2060 .halt_reg = 0xb018,
2062 .hwcg_reg = 0xb018,
2065 .enable_reg = 0xb018,
2066 .enable_mask = BIT(0),
2075 .halt_reg = 0xb01c,
2077 .hwcg_reg = 0xb01c,
2080 .enable_reg = 0xb01c,
2081 .enable_mask = BIT(0),
2090 .halt_reg = 0xb020,
2092 .hwcg_reg = 0xb020,
2095 .enable_reg = 0xb020,
2096 .enable_mask = BIT(0),
2105 .halt_reg = 0xb010,
2107 .hwcg_reg = 0xb010,
2110 .enable_reg = 0xb010,
2111 .enable_mask = BIT(0),
2120 .halt_reg = 0xb014,
2122 .hwcg_reg = 0xb014,
2125 .enable_reg = 0xb014,
2126 .enable_mask = BIT(0),
2135 .halt_reg = 0x4b000,
2138 .enable_reg = 0x4b000,
2139 .enable_mask = BIT(0),
2148 .halt_reg = 0x4b004,
2151 .enable_reg = 0x4b004,
2152 .enable_mask = BIT(0),
2165 .halt_reg = 0x17144,
2168 .enable_reg = 0x5200c,
2182 .halt_reg = 0x17274,
2185 .enable_reg = 0x5200c,
2199 .halt_reg = 0x173a4,
2202 .enable_reg = 0x5200c,
2216 .halt_reg = 0x174d4,
2219 .enable_reg = 0x5200c,
2233 .halt_reg = 0x17604,
2236 .enable_reg = 0x5200c,
2250 .halt_reg = 0x17734,
2253 .enable_reg = 0x5200c,
2267 .halt_reg = 0x17864,
2270 .enable_reg = 0x5200c,
2284 .halt_reg = 0x17994,
2287 .enable_reg = 0x5200c,
2301 .halt_reg = 0x18144,
2304 .enable_reg = 0x5200c,
2318 .halt_reg = 0x18274,
2321 .enable_reg = 0x5200c,
2335 .halt_reg = 0x183a4,
2338 .enable_reg = 0x5200c,
2352 .halt_reg = 0x184d4,
2355 .enable_reg = 0x5200c,
2369 .halt_reg = 0x18604,
2372 .enable_reg = 0x5200c,
2386 .halt_reg = 0x18734,
2389 .enable_reg = 0x5200c,
2403 .halt_reg = 0x1e144,
2406 .enable_reg = 0x52014,
2420 .halt_reg = 0x1e274,
2423 .enable_reg = 0x52014,
2437 .halt_reg = 0x1e3a4,
2440 .enable_reg = 0x52014,
2454 .halt_reg = 0x1e4d4,
2457 .enable_reg = 0x52014,
2471 .halt_reg = 0x1e604,
2474 .enable_reg = 0x52014,
2488 .halt_reg = 0x1e734,
2491 .enable_reg = 0x52014,
2505 .halt_reg = 0x17004,
2508 .enable_reg = 0x5200c,
2518 .halt_reg = 0x17008,
2520 .hwcg_reg = 0x17008,
2523 .enable_reg = 0x5200c,
2533 .halt_reg = 0x18004,
2536 .enable_reg = 0x5200c,
2546 .halt_reg = 0x18008,
2548 .hwcg_reg = 0x18008,
2551 .enable_reg = 0x5200c,
2561 .halt_reg = 0x1e004,
2564 .enable_reg = 0x52014,
2574 .halt_reg = 0x1e008,
2576 .hwcg_reg = 0x1e008,
2579 .enable_reg = 0x52014,
2589 .halt_reg = 0x14008,
2592 .enable_reg = 0x14008,
2593 .enable_mask = BIT(0),
2602 .halt_reg = 0x14004,
2605 .enable_reg = 0x14004,
2606 .enable_mask = BIT(0),
2619 .halt_reg = 0x16008,
2622 .enable_reg = 0x16008,
2623 .enable_mask = BIT(0),
2632 .halt_reg = 0x16004,
2635 .enable_reg = 0x16004,
2636 .enable_mask = BIT(0),
2649 .halt_reg = 0x4819c,
2652 .enable_reg = 0x52004,
2653 .enable_mask = BIT(0),
2667 .halt_reg = 0x36004,
2670 .enable_reg = 0x36004,
2671 .enable_mask = BIT(0),
2680 .halt_reg = 0x3600c,
2683 .enable_reg = 0x3600c,
2684 .enable_mask = BIT(0),
2693 .halt_reg = 0x36008,
2696 .enable_reg = 0x36008,
2697 .enable_mask = BIT(0),
2710 .halt_reg = 0x75014,
2712 .hwcg_reg = 0x75014,
2715 .enable_reg = 0x75014,
2716 .enable_mask = BIT(0),
2725 .halt_reg = 0x75010,
2727 .hwcg_reg = 0x75010,
2730 .enable_reg = 0x75010,
2731 .enable_mask = BIT(0),
2744 .halt_reg = 0x75010,
2746 .hwcg_reg = 0x75010,
2749 .enable_reg = 0x75010,
2763 .halt_reg = 0x8c004,
2766 .enable_reg = 0x8c004,
2767 .enable_mask = BIT(0),
2776 .halt_reg = 0x7505c,
2778 .hwcg_reg = 0x7505c,
2781 .enable_reg = 0x7505c,
2782 .enable_mask = BIT(0),
2795 .halt_reg = 0x7505c,
2797 .hwcg_reg = 0x7505c,
2800 .enable_reg = 0x7505c,
2814 .halt_reg = 0x75090,
2816 .hwcg_reg = 0x75090,
2819 .enable_reg = 0x75090,
2820 .enable_mask = BIT(0),
2833 .halt_reg = 0x75090,
2835 .hwcg_reg = 0x75090,
2838 .enable_reg = 0x75090,
2855 .enable_reg = 0x7501c,
2856 .enable_mask = BIT(0),
2868 .enable_reg = 0x750ac,
2869 .enable_mask = BIT(0),
2881 .enable_reg = 0x75018,
2882 .enable_mask = BIT(0),
2891 .halt_reg = 0x75058,
2893 .hwcg_reg = 0x75058,
2896 .enable_reg = 0x75058,
2897 .enable_mask = BIT(0),
2910 .halt_reg = 0x75058,
2912 .hwcg_reg = 0x75058,
2915 .enable_reg = 0x75058,
2929 .halt_reg = 0x8c000,
2932 .enable_reg = 0x8c000,
2933 .enable_mask = BIT(0),
2942 .halt_reg = 0x77014,
2944 .hwcg_reg = 0x77014,
2947 .enable_reg = 0x77014,
2948 .enable_mask = BIT(0),
2957 .halt_reg = 0x77010,
2959 .hwcg_reg = 0x77010,
2962 .enable_reg = 0x77010,
2963 .enable_mask = BIT(0),
2976 .halt_reg = 0x77010,
2978 .hwcg_reg = 0x77010,
2981 .enable_reg = 0x77010,
2995 .halt_reg = 0x7705c,
2997 .hwcg_reg = 0x7705c,
3000 .enable_reg = 0x7705c,
3001 .enable_mask = BIT(0),
3014 .halt_reg = 0x7705c,
3016 .hwcg_reg = 0x7705c,
3019 .enable_reg = 0x7705c,
3033 .halt_reg = 0x77090,
3035 .hwcg_reg = 0x77090,
3038 .enable_reg = 0x77090,
3039 .enable_mask = BIT(0),
3052 .halt_reg = 0x77090,
3054 .hwcg_reg = 0x77090,
3057 .enable_reg = 0x77090,
3074 .enable_reg = 0x7701c,
3075 .enable_mask = BIT(0),
3087 .enable_reg = 0x770ac,
3088 .enable_mask = BIT(0),
3100 .enable_reg = 0x77018,
3101 .enable_mask = BIT(0),
3110 .halt_reg = 0x77058,
3112 .hwcg_reg = 0x77058,
3115 .enable_reg = 0x77058,
3116 .enable_mask = BIT(0),
3129 .halt_reg = 0x77058,
3131 .hwcg_reg = 0x77058,
3134 .enable_reg = 0x77058,
3148 .halt_reg = 0xf010,
3151 .enable_reg = 0xf010,
3152 .enable_mask = BIT(0),
3165 .halt_reg = 0xf018,
3168 .enable_reg = 0xf018,
3169 .enable_mask = BIT(0),
3182 .halt_reg = 0xf014,
3185 .enable_reg = 0xf014,
3186 .enable_mask = BIT(0),
3195 .halt_reg = 0x10010,
3198 .enable_reg = 0x10010,
3199 .enable_mask = BIT(0),
3212 .halt_reg = 0x10018,
3215 .enable_reg = 0x10018,
3216 .enable_mask = BIT(0),
3229 .halt_reg = 0x10014,
3232 .enable_reg = 0x10014,
3233 .enable_mask = BIT(0),
3242 .halt_reg = 0x8c008,
3245 .enable_reg = 0x8c008,
3246 .enable_mask = BIT(0),
3255 .halt_reg = 0xf050,
3258 .enable_reg = 0xf050,
3259 .enable_mask = BIT(0),
3272 .halt_reg = 0xf054,
3275 .enable_reg = 0xf054,
3276 .enable_mask = BIT(0),
3291 .enable_reg = 0xf058,
3292 .enable_mask = BIT(0),
3301 .halt_reg = 0x8c028,
3304 .enable_reg = 0x8c028,
3305 .enable_mask = BIT(0),
3314 .halt_reg = 0x10050,
3317 .enable_reg = 0x10050,
3318 .enable_mask = BIT(0),
3331 .halt_reg = 0x10054,
3334 .enable_reg = 0x10054,
3335 .enable_mask = BIT(0),
3350 .enable_reg = 0x10058,
3351 .enable_mask = BIT(0),
3364 .halt_reg = 0xb004,
3366 .hwcg_reg = 0xb004,
3369 .enable_reg = 0xb004,
3370 .enable_mask = BIT(0),
3380 .halt_reg = 0xb024,
3383 .enable_reg = 0xb024,
3384 .enable_mask = BIT(0),
3393 .halt_reg = 0xb028,
3396 .enable_reg = 0xb028,
3397 .enable_mask = BIT(0),
3406 .halt_reg = 0xb02c,
3409 .enable_reg = 0xb02c,
3410 .enable_mask = BIT(0),
3420 .halt_reg = 0xb040,
3423 .enable_reg = 0xb040,
3424 .enable_mask = BIT(0),
3434 .gdscr = 0x6b004,
3443 .gdscr = 0x8d004,
3452 .gdscr = 0x75004,
3461 .gdscr = 0x77004,
3470 .gdscr = 0x6004,
3479 .gdscr = 0xf004,
3488 .gdscr = 0x10004,
3712 [GCC_EMAC_BCR] = { 0x6000 },
3713 [GCC_GPU_BCR] = { 0x71000 },
3714 [GCC_MMSS_BCR] = { 0xb000 },
3715 [GCC_NPU_BCR] = { 0x4d000 },
3716 [GCC_PCIE_0_BCR] = { 0x6b000 },
3717 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3718 [GCC_PCIE_1_BCR] = { 0x8d000 },
3719 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3720 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3721 [GCC_PDM_BCR] = { 0x33000 },
3722 [GCC_PRNG_BCR] = { 0x34000 },
3723 [GCC_QSPI_BCR] = { 0x24008 },
3724 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3725 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3726 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3727 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3728 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3729 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3730 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3731 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3732 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3733 [GCC_SDCC2_BCR] = { 0x14000 },
3734 [GCC_SDCC4_BCR] = { 0x16000 },
3735 [GCC_TSIF_BCR] = { 0x36000 },
3736 [GCC_UFS_CARD_BCR] = { 0x75000 },
3737 [GCC_UFS_PHY_BCR] = { 0x77000 },
3738 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3739 [GCC_USB30_SEC_BCR] = { 0x10000 },
3740 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3757 .max_register = 0x9c040,
3786 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm8150_probe()
3787 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm8150_probe()