Lines Matching +full:reference +full:- +full:div2 +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
167 "ck_hse", "pll4_r", "clk-hse-div2"
393 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
396 cfg->name, in _clk_hw_register_gate()
397 cfg->parent_name, in _clk_hw_register_gate()
398 cfg->flags, in _clk_hw_register_gate()
399 gate_cfg->reg_off + base, in _clk_hw_register_gate()
400 gate_cfg->bit_idx, in _clk_hw_register_gate()
401 gate_cfg->gate_flags, in _clk_hw_register_gate()
411 struct fixed_factor_cfg *ff_cfg = cfg->cfg; in _clk_hw_register_fixed_factor()
413 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, in _clk_hw_register_fixed_factor()
414 cfg->flags, ff_cfg->mult, in _clk_hw_register_fixed_factor()
415 ff_cfg->div); in _clk_hw_register_fixed_factor()
424 struct div_cfg *div_cfg = cfg->cfg; in _clk_hw_register_divider_table()
427 cfg->name, in _clk_hw_register_divider_table()
428 cfg->parent_name, in _clk_hw_register_divider_table()
429 cfg->flags, in _clk_hw_register_divider_table()
430 div_cfg->reg_off + base, in _clk_hw_register_divider_table()
431 div_cfg->shift, in _clk_hw_register_divider_table()
432 div_cfg->width, in _clk_hw_register_divider_table()
433 div_cfg->div_flags, in _clk_hw_register_divider_table()
434 div_cfg->table, in _clk_hw_register_divider_table()
444 struct mux_cfg *mux_cfg = cfg->cfg; in _clk_hw_register_mux()
446 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, in _clk_hw_register_mux()
447 cfg->num_parents, cfg->flags, in _clk_hw_register_mux()
448 mux_cfg->reg_off + base, mux_cfg->shift, in _clk_hw_register_mux()
449 mux_cfg->width, mux_cfg->mux_flags, lock); in _clk_hw_register_mux()
457 clk_gate_ops.enable(hw); in mp1_gate_clk_enable()
468 spin_lock_irqsave(gate->lock, flags); in mp1_gate_clk_disable()
469 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR); in mp1_gate_clk_disable()
470 spin_unlock_irqrestore(gate->lock, flags); in mp1_gate_clk_disable()
475 .enable = mp1_gate_clk_enable,
488 if (cfg->mmux) { in _get_stm32_mux()
491 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
493 mmux->mux.reg = cfg->mux->reg_off + base; in _get_stm32_mux()
494 mmux->mux.shift = cfg->mux->shift; in _get_stm32_mux()
495 mmux->mux.mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
496 mmux->mux.flags = cfg->mux->mux_flags; in _get_stm32_mux()
497 mmux->mux.table = cfg->mux->table; in _get_stm32_mux()
498 mmux->mux.lock = lock; in _get_stm32_mux()
499 mmux->mmux = cfg->mmux; in _get_stm32_mux()
500 mux_hw = &mmux->mux.hw; in _get_stm32_mux()
501 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw; in _get_stm32_mux()
506 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
508 mux->reg = cfg->mux->reg_off + base; in _get_stm32_mux()
509 mux->shift = cfg->mux->shift; in _get_stm32_mux()
510 mux->mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
511 mux->flags = cfg->mux->mux_flags; in _get_stm32_mux()
512 mux->table = cfg->mux->table; in _get_stm32_mux()
513 mux->lock = lock; in _get_stm32_mux()
514 mux_hw = &mux->hw; in _get_stm32_mux()
529 return ERR_PTR(-ENOMEM); in _get_stm32_div()
531 div->reg = cfg->div->reg_off + base; in _get_stm32_div()
532 div->shift = cfg->div->shift; in _get_stm32_div()
533 div->width = cfg->div->width; in _get_stm32_div()
534 div->flags = cfg->div->div_flags; in _get_stm32_div()
535 div->table = cfg->div->table; in _get_stm32_div()
536 div->lock = lock; in _get_stm32_div()
538 return &div->hw; in _get_stm32_div()
549 if (cfg->mgate) { in _get_stm32_gate()
552 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
554 mgate->gate.reg = cfg->gate->reg_off + base; in _get_stm32_gate()
555 mgate->gate.bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
556 mgate->gate.flags = cfg->gate->gate_flags; in _get_stm32_gate()
557 mgate->gate.lock = lock; in _get_stm32_gate()
558 mgate->mask = BIT(cfg->mgate->nbr_clk++); in _get_stm32_gate()
560 mgate->mgate = cfg->mgate; in _get_stm32_gate()
562 gate_hw = &mgate->gate.hw; in _get_stm32_gate()
567 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
569 gate->reg = cfg->gate->reg_off + base; in _get_stm32_gate()
570 gate->bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
571 gate->flags = cfg->gate->gate_flags; in _get_stm32_gate()
572 gate->lock = lock; in _get_stm32_gate()
574 gate_hw = &gate->hw; in _get_stm32_gate()
604 if (cfg->ops) in clk_stm32_register_gate_ops()
605 init.ops = cfg->ops; in clk_stm32_register_gate_ops()
609 return ERR_PTR(-ENOMEM); in clk_stm32_register_gate_ops()
611 hw->init = &init; in clk_stm32_register_gate_ops()
638 if (cfg->mux) { in clk_stm32_register_composite()
639 mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock); in clk_stm32_register_composite()
644 if (cfg->mux->ops) in clk_stm32_register_composite()
645 mux_ops = cfg->mux->ops; in clk_stm32_register_composite()
649 if (cfg->div) { in clk_stm32_register_composite()
650 div_hw = _get_stm32_div(dev, base, cfg->div, lock); in clk_stm32_register_composite()
655 if (cfg->div->ops) in clk_stm32_register_composite()
656 div_ops = cfg->div->ops; in clk_stm32_register_composite()
660 if (cfg->gate) { in clk_stm32_register_composite()
661 gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock); in clk_stm32_register_composite()
666 if (cfg->gate->ops) in clk_stm32_register_composite()
667 gate_ops = cfg->gate->ops; in clk_stm32_register_composite()
683 clk_mgate->mgate->flag |= clk_mgate->mask; in mp1_mgate_clk_enable()
695 clk_mgate->mgate->flag &= ~clk_mgate->mask; in mp1_mgate_clk_disable()
697 if (clk_mgate->mgate->flag == 0) in mp1_mgate_clk_disable()
702 .enable = mp1_mgate_clk_enable,
728 for (n = 0; n < clk_mmux->mmux->nbr_clk; n++) in clk_mmux_set_parent()
729 if (clk_mmux->mmux->hws[n] != hw) in clk_mmux_set_parent()
730 clk_hw_reparent(clk_mmux->mmux->hws[n], hwp); in clk_mmux_set_parent()
743 /* lock pll enable/disable registers */
769 return readl_relaxed(clk_elem->reg) & PLL_ON; in __pll_is_enabled()
782 spin_lock_irqsave(clk_elem->lock, flags); in pll_enable()
787 reg = readl_relaxed(clk_elem->reg); in pll_enable()
789 writel_relaxed(reg, clk_elem->reg); in pll_enable()
794 * interruptions and enable op does not allow to be interrupted. in pll_enable()
797 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY); in pll_enable()
802 } while (bit_status && --timeout); in pll_enable()
805 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_enable()
816 spin_lock_irqsave(clk_elem->lock, flags); in pll_disable()
818 reg = readl_relaxed(clk_elem->reg); in pll_disable()
820 writel_relaxed(reg, clk_elem->reg); in pll_disable()
822 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_disable()
830 reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET); in pll_frac_val()
845 reg = readl_relaxed(clk_elem->reg + 4); in pll_recalc_rate()
868 spin_lock_irqsave(clk_elem->lock, flags); in pll_is_enabled()
870 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_is_enabled()
878 struct clk_hw *mux_hw = &clk_elem->mux.hw; in pll_get_parent()
886 .enable = pll_enable,
908 return ERR_PTR(-ENOMEM); in clk_register_pll()
916 element->mux.lock = lock; in clk_register_pll()
917 element->mux.reg = mux_reg; in clk_register_pll()
918 element->mux.shift = PLL_MUX_SHIFT; in clk_register_pll()
919 element->mux.mask = PLL_MUX_MASK; in clk_register_pll()
920 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
921 element->mux.reg = mux_reg; in clk_register_pll()
923 element->hw.init = &init; in clk_register_pll()
924 element->reg = reg; in clk_register_pll()
925 element->lock = lock; in clk_register_pll()
927 hw = &element->hw; in clk_register_pll()
957 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in __bestmult()
985 spin_lock_irqsave(tim_ker->lock, flags); in timer_ker_set_rate()
991 writel_relaxed(0, tim_ker->timpre); in timer_ker_set_rate()
994 writel_relaxed(1, tim_ker->timpre); in timer_ker_set_rate()
997 ret = -EINVAL; in timer_ker_set_rate()
999 spin_unlock_irqrestore(tim_ker->lock, flags); in timer_ker_set_rate()
1011 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in timer_ker_recalc_rate()
1013 timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK; in timer_ker_recalc_rate()
1044 return ERR_PTR(-ENOMEM); in clk_register_cktim()
1052 tim_ker->hw.init = &init; in clk_register_cktim()
1053 tim_ker->lock = lock; in clk_register_cktim()
1054 tim_ker->apbdiv = apbdiv; in clk_register_cktim()
1055 tim_ker->timpre = timpre; in clk_register_cktim()
1057 hw = &tim_ker->hw; in clk_register_cktim()
1089 if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) in clk_divider_rtc_determine_rate()
1092 req->rate = req->best_parent_rate; in clk_divider_rtc_determine_rate()
1113 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; in _clk_register_pll()
1115 return clk_register_pll(dev, cfg->name, cfg->parent_names, in _clk_register_pll()
1116 cfg->num_parents, in _clk_register_pll()
1117 base + stm_pll_cfg->offset, in _clk_register_pll()
1118 base + stm_pll_cfg->muxoff, in _clk_register_pll()
1119 cfg->flags, lock); in _clk_register_pll()
1132 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; in _clk_register_cktim()
1134 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, in _clk_register_cktim()
1135 cktim_cfg->offset_apbdiv + base, in _clk_register_cktim()
1136 cktim_cfg->offset_timpre + base, lock); in _clk_register_cktim()
1146 cfg->name, in _clk_stm32_register_gate()
1147 cfg->parent_name, in _clk_stm32_register_gate()
1148 cfg->parent_data, in _clk_stm32_register_gate()
1149 cfg->flags, in _clk_stm32_register_gate()
1151 cfg->cfg, in _clk_stm32_register_gate()
1161 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, in _clk_stm32_register_composite()
1162 cfg->parent_data, cfg->num_parents, in _clk_stm32_register_composite()
1163 base, cfg->cfg, cfg->flags, lock); in _clk_stm32_register_composite()
1758 GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1760 GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1762 COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1767 GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1768 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1770 FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
2131 if (cfg->id == stm32mp1_clock_secured[i]) in stm32_check_security()
2161 .compatible = "st,stm32mp1-rcc",
2165 .compatible = "st,stm32mp1-rcc-secure",
2178 struct clk_hw *hw = ERR_PTR(-ENOENT); in stm32_register_hw_clk()
2180 hws = clk_data->hws; in stm32_register_hw_clk()
2182 if (cfg->func) in stm32_register_hw_clk()
2183 hw = (*cfg->func)(dev, clk_data, base, lock, cfg); in stm32_register_hw_clk()
2186 pr_err("Unable to register %s\n", cfg->name); in stm32_register_hw_clk()
2190 if (cfg->id != NO_ID) in stm32_register_hw_clk()
2191 hws[cfg->id] = hw; in stm32_register_hw_clk()
2220 if (data->clear_offset) { in stm32_reset_update()
2223 addr = data->membase + (bank * reg_width); in stm32_reset_update()
2225 addr += data->clear_offset; in stm32_reset_update()
2233 spin_lock_irqsave(&data->lock, flags); in stm32_reset_update()
2235 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_update()
2242 writel(reg, data->membase + (bank * reg_width)); in stm32_reset_update()
2244 spin_unlock_irqrestore(&data->lock, flags); in stm32_reset_update()
2271 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_status()
2285 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_reset_init()
2290 return -ENOMEM; in stm32_rcc_reset_init()
2292 spin_lock_init(&reset_data->lock); in stm32_rcc_reset_init()
2293 reset_data->membase = base; in stm32_rcc_reset_init()
2294 reset_data->rcdev.owner = THIS_MODULE; in stm32_rcc_reset_init()
2295 reset_data->rcdev.ops = &stm32_reset_ops; in stm32_rcc_reset_init()
2296 reset_data->rcdev.of_node = dev_of_node(dev); in stm32_rcc_reset_init()
2297 reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK; in stm32_rcc_reset_init()
2298 reset_data->clear_offset = data->clear_offset; in stm32_rcc_reset_init()
2300 return reset_controller_register(&reset_data->rcdev); in stm32_rcc_reset_init()
2306 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
2311 max_binding = data->maxbinding; in stm32_rcc_clock_init()
2316 return -ENOMEM; in stm32_rcc_clock_init()
2318 clk_data->num = max_binding; in stm32_rcc_clock_init()
2320 hws = clk_data->hws; in stm32_rcc_clock_init()
2323 hws[n] = ERR_PTR(-ENOENT); in stm32_rcc_clock_init()
2325 for (n = 0; n < data->num; n++) { in stm32_rcc_clock_init()
2326 if (data->check_security && data->check_security(&data->cfg[n])) in stm32_rcc_clock_init()
2330 &data->cfg[n]); in stm32_rcc_clock_init()
2333 data->cfg[n].name, err); in stm32_rcc_clock_init()
2351 return -ENODEV; in stm32_rcc_init()
2379 ret = -ENOMEM; in stm32mp1_rcc_init()
2407 return -ENOMEM; in get_clock_deps()
2414 if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) in get_clock_deps()
2417 /* Device gets a reference count on the clock */ in get_clock_deps()
2428 struct device *dev = &pdev->dev; in stm32mp1_rcc_clocks_probe()
2439 struct device *dev = &pdev->dev; in stm32mp1_rcc_clocks_remove()