1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2012-2013 Analog Devices Inc.
6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
11 #include <linux/clk-provider.h>
60 	struct axi_clkgen_limits limits;  member
126 static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,  in axi_clkgen_calc_params()  argument
144 	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);  in axi_clkgen_calc_params()
145 	d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);  in axi_clkgen_calc_params()
148 	fvco_min_fract = limits->fvco_min << fract_shift;  in axi_clkgen_calc_params()
149 	fvco_max_fract = limits->fvco_max << fract_shift;  in axi_clkgen_calc_params()
164 			if (abs(f - fout) < abs(best_f - fout)) {  in axi_clkgen_calc_params()
167 				*best_m = m << (3 - fract_shift);  in axi_clkgen_calc_params()
168 				*best_dout = dout << (3 - fract_shift);  in axi_clkgen_calc_params()
201 		params->nocount = 1;  in axi_clkgen_calc_clk_params()
206 		params->high = divider / 2;  in axi_clkgen_calc_clk_params()
207 		params->edge = divider % 2;  in axi_clkgen_calc_clk_params()
208 		params->low = divider - params->high;  in axi_clkgen_calc_clk_params()
210 		params->frac_en = 1;  in axi_clkgen_calc_clk_params()
211 		params->frac = frac_divider;  in axi_clkgen_calc_clk_params()
213 		params->high = divider / 2;  in axi_clkgen_calc_clk_params()
214 		params->edge = divider % 2;  in axi_clkgen_calc_clk_params()
215 		params->low = params->high;  in axi_clkgen_calc_clk_params()
217 		if (params->edge == 0) {  in axi_clkgen_calc_clk_params()
218 			params->high--;  in axi_clkgen_calc_clk_params()
219 			params->frac_wf_r = 1;  in axi_clkgen_calc_clk_params()
222 		if (params->edge == 0 || frac_divider == 1)  in axi_clkgen_calc_clk_params()
223 			params->low--;  in axi_clkgen_calc_clk_params()
224 		if (((params->edge == 0) ^ (frac_divider == 1)) ||  in axi_clkgen_calc_clk_params()
226 			params->frac_wf_f = 1;  in axi_clkgen_calc_clk_params()
228 		params->frac_phase = params->edge * 4 + frac_divider / 2;  in axi_clkgen_calc_clk_params()
235 	writel(val, axi_clkgen->base + reg);  in axi_clkgen_write()
241 	*val = readl(axi_clkgen->base + reg);  in axi_clkgen_read()
251 	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);  in axi_clkgen_wait_non_busy()
254 		return -EIO;  in axi_clkgen_wait_non_busy()
326 		(params->high << 6) | params->low, 0xefff);  in axi_clkgen_set_div()
328 		(params->frac << 12) | (params->frac_en << 11) |  in axi_clkgen_set_div()
329 		(params->frac_wf_r << 10) | (params->edge << 7) |  in axi_clkgen_set_div()
330 		(params->nocount << 6), 0x7fff);  in axi_clkgen_set_div()
333 			(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);  in axi_clkgen_set_div()
341 	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;  in axi_clkgen_set_rate()  local
344 	uint32_t power = 0;  in axi_clkgen_set_rate()  local
349 		return -EINVAL;  in axi_clkgen_set_rate()
351 	axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);  in axi_clkgen_set_rate()
354 		return -EINVAL;  in axi_clkgen_set_rate()
357 		power |= 0x9800;  in axi_clkgen_set_rate()
359 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);  in axi_clkgen_set_rate()
361 	filter = axi_clkgen_lookup_filter(m - 1);  in axi_clkgen_set_rate()
362 	lock = axi_clkgen_lookup_lock(m - 1);  in axi_clkgen_set_rate()
392 	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;  in axi_clkgen_determine_rate()  local
396 	axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,  in axi_clkgen_determine_rate()
400 		return -EINVAL;  in axi_clkgen_determine_rate()
402 	tmp = (unsigned long long)req->best_parent_rate * m;  in axi_clkgen_determine_rate()
405 	req->rate = min_t(unsigned long long, tmp, LONG_MAX);  in axi_clkgen_determine_rate()
520 	dflt_limits = device_get_match_data(&pdev->dev);  in axi_clkgen_probe()
522 		return -ENODEV;  in axi_clkgen_probe()
524 	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);  in axi_clkgen_probe()
526 		return -ENOMEM;  in axi_clkgen_probe()
528 	axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);  in axi_clkgen_probe()
529 	if (IS_ERR(axi_clkgen->base))  in axi_clkgen_probe()
530 		return PTR_ERR(axi_clkgen->base);  in axi_clkgen_probe()
532 	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);  in axi_clkgen_probe()
534 	axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");  in axi_clkgen_probe()
537 			return -EINVAL;  in axi_clkgen_probe()
539 		init.num_parents -= 1;  in axi_clkgen_probe()
542 		 * Legacy... So that old DTs which do not have clock-names still  in axi_clkgen_probe()
546 		if (PTR_ERR(axi_clk) != -ENOENT)  in axi_clkgen_probe()
549 			return -EINVAL;  in axi_clkgen_probe()
553 		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);  in axi_clkgen_probe()
555 			return -EINVAL;  in axi_clkgen_probe()
558 	memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));  in axi_clkgen_probe()
560 	clk_name = pdev->dev.of_node->name;  in axi_clkgen_probe()
561 	of_property_read_string(pdev->dev.of_node, "clock-output-names",  in axi_clkgen_probe()
571 	axi_clkgen->clk_hw.init = &init;  in axi_clkgen_probe()
572 	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);  in axi_clkgen_probe()
576 	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,  in axi_clkgen_probe()
577 					   &axi_clkgen->clk_hw);  in axi_clkgen_probe()
582 		.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
586 		.compatible = "adi,axi-clkgen-2.00.a",
595 		.name = "adi-axi-clkgen",
603 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");