drivers/clk/clk-aspeed.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17  * struct aspeed_gate_data - Aspeed gated clocks
19  * @reset_idx: bit used to reset this IP in the reset register. -1 if no
20  *             reset is required when enabling the clock
21  * @name: the clock name
22  * @parent_name: the name of the parent clock
28 	const char	*name;  member
34  * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35  * @hw:		handle between common and hardware-specific interfaces
38  * @reset_idx:	bit used to reset this IP in the reset register. -1 if no
39  *		reset is required when enabling the clock
40  * @flags:	hardware-specific flags
43  * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
44  * This modified version of clk_gate allows an optional reset bit to be
59  * struct aspeed_reset - Aspeed reset controller
61  * @rcdev: reset controller device
71  * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
81 	struct clk_hw *(*calc_pll)(const char *name, u32 val);