Lines Matching +full:udma +full:- +full:p
1 // SPDX-License-Identifier: GPL-2.0-only
55 controller_kl_ata3, /* KeyLargo ATA-3 */
56 controller_kl_ata4, /* KeyLargo ATA-4 */
57 controller_un_ata6, /* UniNorth2 ATA-6 */
58 controller_k2_ata6, /* K2 ATA-6 */
59 controller_sh_ata6, /* Shasta ATA-6 */
65 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
66 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
67 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
68 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
69 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
73 * Extra registers, both 32-bit little-endian
88 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
89 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
107 * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
112 * though I use pre-calculated tables for UDMA as usual...
136 * - Write data setup, which appears to match the cycle time. They
138 * - Ready to pause time (from spec)
139 * - Address setup. That one is weird. I don't see where exactly
140 * it fits in UDMA cycles, I got it's name from an obscure piece
217 * the BSY bit (typically some combo drives slave on the UDMA
222 * from MacOS...) --BenH.
275 { -1, 0, 0 }
287 { -1, 0, 0 }
299 { -1, 0, 0 }
316 { -1, 0, 0 }
334 { -1, 0, 0 }
353 { -1, 0, 0 }
362 for (i = 0; priv->timings[i].mode > 0; i++) { in pata_macio_find_timing()
363 if (priv->timings[i].mode == mode) in pata_macio_find_timing()
364 return &priv->timings[i]; in pata_macio_find_timing()
372 struct pata_macio_priv *priv = ap->private_data; in pata_macio_apply_timings()
373 void __iomem *rbase = ap->ioaddr.cmd_addr; in pata_macio_apply_timings()
375 if (priv->kind == controller_sh_ata6 || in pata_macio_apply_timings()
376 priv->kind == controller_un_ata6 || in pata_macio_apply_timings()
377 priv->kind == controller_k2_ata6) { in pata_macio_apply_timings()
378 writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG); in pata_macio_apply_timings()
379 writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG); in pata_macio_apply_timings()
381 writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG); in pata_macio_apply_timings()
395 struct pata_macio_priv *priv = ap->private_data; in pata_macio_set_timings()
398 dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n", in pata_macio_set_timings()
399 adev->devno, in pata_macio_set_timings()
400 adev->pio_mode, in pata_macio_set_timings()
401 ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)), in pata_macio_set_timings()
402 adev->dma_mode, in pata_macio_set_timings()
403 ata_mode_string(ata_xfer_mode2mask(adev->dma_mode))); in pata_macio_set_timings()
406 priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0; in pata_macio_set_timings()
409 t = pata_macio_find_timing(priv, adev->pio_mode); in pata_macio_set_timings()
411 dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n", in pata_macio_set_timings()
412 adev->pio_mode); in pata_macio_set_timings()
418 priv->treg[adev->devno][0] |= t->reg1; in pata_macio_set_timings()
421 t = pata_macio_find_timing(priv, adev->dma_mode); in pata_macio_set_timings()
422 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { in pata_macio_set_timings()
423 dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n"); in pata_macio_set_timings()
429 priv->treg[adev->devno][0] |= t->reg1; in pata_macio_set_timings()
430 priv->treg[adev->devno][1] |= t->reg2; in pata_macio_set_timings()
432 dev_dbg(priv->dev, " -> %08x %08x\n", in pata_macio_set_timings()
433 priv->treg[adev->devno][0], in pata_macio_set_timings()
434 priv->treg[adev->devno][1]); in pata_macio_set_timings()
437 pata_macio_apply_timings(ap, adev->devno); in pata_macio_set_timings()
448 switch(priv->kind) { in pata_macio_default_timings()
470 priv->treg[0][0] = priv->treg[1][0] = value; in pata_macio_default_timings()
471 priv->treg[0][1] = priv->treg[1][1] = value2; in pata_macio_default_timings()
476 struct pata_macio_priv *priv = ap->private_data; in pata_macio_cable_detect()
478 /* Get cable type from device-tree */ in pata_macio_cable_detect()
479 if (priv->kind == controller_kl_ata4 || in pata_macio_cable_detect()
480 priv->kind == controller_un_ata6 || in pata_macio_cable_detect()
481 priv->kind == controller_k2_ata6 || in pata_macio_cable_detect()
482 priv->kind == controller_sh_ata6) { in pata_macio_cable_detect()
483 const char* cable = of_get_property(priv->node, "cable-type", in pata_macio_cable_detect()
490 if (cable && !strncmp(cable, "80-", 3)) { in pata_macio_cable_detect()
502 /* G5's seem to have incorrect cable type in device-tree. in pata_macio_cable_detect()
506 if (of_device_is_compatible(priv->node, "K2-UATA") || in pata_macio_cable_detect()
507 of_device_is_compatible(priv->node, "shasta-ata")) in pata_macio_cable_detect()
516 unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE); in pata_macio_qc_prep()
517 struct ata_port *ap = qc->ap; in pata_macio_qc_prep()
518 struct pata_macio_priv *priv = ap->private_data; in pata_macio_qc_prep()
523 dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n", in pata_macio_qc_prep()
524 __func__, qc, qc->flags, write, qc->dev->devno); in pata_macio_qc_prep()
526 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in pata_macio_qc_prep()
529 table = (struct dbdma_cmd *) priv->dma_table_cpu; in pata_macio_qc_prep()
532 for_each_sg(qc->sg, sg, qc->n_elem, si) { in pata_macio_qc_prep()
536 * Note h/w doesn't support 64-bit, so we unconditionally in pata_macio_qc_prep()
548 table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE); in pata_macio_qc_prep()
549 table->req_count = cpu_to_le16(len); in pata_macio_qc_prep()
550 table->phy_addr = cpu_to_le32(addr); in pata_macio_qc_prep()
551 table->cmd_dep = 0; in pata_macio_qc_prep()
552 table->xfer_status = 0; in pata_macio_qc_prep()
553 table->res_count = 0; in pata_macio_qc_prep()
555 sg_len -= len; in pata_macio_qc_prep()
566 table--; in pata_macio_qc_prep()
567 table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST); in pata_macio_qc_prep()
572 table->command = cpu_to_le16(DBDMA_STOP); in pata_macio_qc_prep()
574 dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi); in pata_macio_qc_prep()
582 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_freeze()
588 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); in pata_macio_freeze()
589 while (--timeout && (readl(&dma_regs->status) & RUN)) in pata_macio_freeze()
599 struct ata_port *ap = qc->ap; in pata_macio_bmdma_setup()
600 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_setup()
601 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_setup()
602 int dev = qc->dev->devno; in pata_macio_bmdma_setup()
604 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); in pata_macio_bmdma_setup()
607 writel(priv->dma_table_dma, &dma_regs->cmdptr); in pata_macio_bmdma_setup()
610 * UDMA reads in pata_macio_bmdma_setup()
612 if (priv->kind == controller_kl_ata4 && in pata_macio_bmdma_setup()
613 (priv->treg[dev][0] & TR_66_UDMA_EN)) { in pata_macio_bmdma_setup()
614 void __iomem *rbase = ap->ioaddr.cmd_addr; in pata_macio_bmdma_setup()
615 u32 reg = priv->treg[dev][0]; in pata_macio_bmdma_setup()
617 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) in pata_macio_bmdma_setup()
623 ap->ops->sff_exec_command(ap, &qc->tf); in pata_macio_bmdma_setup()
628 struct ata_port *ap = qc->ap; in pata_macio_bmdma_start()
629 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_start()
630 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_start()
632 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); in pata_macio_bmdma_start()
634 writel((RUN << 16) | RUN, &dma_regs->control); in pata_macio_bmdma_start()
636 (void)readl(&dma_regs->control); in pata_macio_bmdma_start()
641 struct ata_port *ap = qc->ap; in pata_macio_bmdma_stop()
642 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_stop()
643 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_stop()
646 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc); in pata_macio_bmdma_stop()
649 writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control); in pata_macio_bmdma_stop()
650 while (--timeout && (readl(&dma_regs->status) & RUN)) in pata_macio_bmdma_stop()
656 struct pata_macio_priv *priv = ap->private_data; in pata_macio_bmdma_status()
657 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr; in pata_macio_bmdma_status()
661 dstat = readl(&dma_regs->status); in pata_macio_bmdma_status()
663 dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat); in pata_macio_bmdma_status()
667 * - The dbdma won't stop if the command was started in pata_macio_bmdma_status()
670 * a multi-block transfer. in pata_macio_bmdma_status()
672 * - The dbdma fifo hasn't yet finished flushing to in pata_macio_bmdma_status()
687 dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__); in pata_macio_bmdma_status()
696 writel((FLUSH << 16) | FLUSH, &dma_regs->control); in pata_macio_bmdma_status()
699 dstat = readl(&dma_regs->status); in pata_macio_bmdma_status()
703 dev_warn(priv->dev, "timeout flushing DMA\n"); in pata_macio_bmdma_status()
714 struct pata_macio_priv *priv = ap->private_data; in pata_macio_port_start()
716 if (ap->ioaddr.bmdma_addr == NULL) in pata_macio_port_start()
724 priv->dma_table_cpu = in pata_macio_port_start()
725 dmam_alloc_coherent(priv->dev, in pata_macio_port_start()
727 &priv->dma_table_dma, GFP_KERNEL); in pata_macio_port_start()
728 if (priv->dma_table_cpu == NULL) { in pata_macio_port_start()
729 dev_err(priv->dev, "Unable to allocate DMA command list\n"); in pata_macio_port_start()
730 ap->ioaddr.bmdma_addr = NULL; in pata_macio_port_start()
731 ap->mwdma_mask = 0; in pata_macio_port_start()
732 ap->udma_mask = 0; in pata_macio_port_start()
739 struct pata_macio_priv *priv = ap->private_data; in pata_macio_irq_clear()
743 dev_dbgdma(priv->dev, "%s\n", __func__); in pata_macio_irq_clear()
748 dev_dbg(priv->dev, "Enabling & resetting... \n"); in pata_macio_reset_hw()
750 if (priv->mediabay) in pata_macio_reset_hw()
753 if (priv->kind == controller_ohare && !resume) { in pata_macio_reset_hw()
758 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1); in pata_macio_reset_hw()
764 priv->node, priv->aapl_bus_id, 1); in pata_macio_reset_hw()
766 priv->node, priv->aapl_bus_id, 1); in pata_macio_reset_hw()
771 priv->node, priv->aapl_bus_id, 0); in pata_macio_reset_hw()
777 if (priv->pdev && resume) { in pata_macio_reset_hw()
780 pci_restore_state(priv->pdev); in pata_macio_reset_hw()
781 rc = pcim_enable_device(priv->pdev); in pata_macio_reset_hw()
783 dev_err(&priv->pdev->dev, in pata_macio_reset_hw()
787 pci_set_master(priv->pdev); in pata_macio_reset_hw()
793 if (priv->kauai_fcr) in pata_macio_reset_hw()
796 KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr); in pata_macio_reset_hw()
804 struct ata_port *ap = ata_shost_to_port(sdev->host); in pata_macio_slave_config()
805 struct pata_macio_priv *priv = ap->private_data; in pata_macio_slave_config()
816 dev = &ap->link.device[sdev->id]; in pata_macio_slave_config()
819 if (priv->kind == controller_ohare) { in pata_macio_slave_config()
820 blk_queue_update_dma_alignment(sdev->request_queue, 31); in pata_macio_slave_config()
821 blk_queue_update_dma_pad(sdev->request_queue, 31); in pata_macio_slave_config()
829 if (dev->class != ATA_DEV_ATAPI) in pata_macio_slave_config()
833 if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) { in pata_macio_slave_config()
835 blk_queue_update_dma_alignment(sdev->request_queue, 15); in pata_macio_slave_config()
836 blk_queue_update_dma_pad(sdev->request_queue, 15); in pata_macio_slave_config()
841 * to do the same Apple does and pray they did not get it wrong :-) in pata_macio_slave_config()
843 BUG_ON(!priv->pdev); in pata_macio_slave_config()
844 pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08); in pata_macio_slave_config()
845 pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd); in pata_macio_slave_config()
846 pci_write_config_word(priv->pdev, PCI_COMMAND, in pata_macio_slave_config()
860 ata_host_suspend(priv->host, mesg); in pata_macio_do_suspend()
867 disable_irq(priv->irq); in pata_macio_do_suspend()
870 if (priv->mediabay) in pata_macio_do_suspend()
874 if (priv->kauai_fcr) { in pata_macio_do_suspend()
875 u32 fcr = readl(priv->kauai_fcr); in pata_macio_do_suspend()
877 writel(fcr, priv->kauai_fcr); in pata_macio_do_suspend()
885 if (priv->pdev) { in pata_macio_do_suspend()
886 pci_save_state(priv->pdev); in pata_macio_do_suspend()
887 pci_disable_device(priv->pdev); in pata_macio_do_suspend()
891 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, in pata_macio_do_suspend()
892 priv->aapl_bus_id, 0); in pata_macio_do_suspend()
899 /* Reset and re-enable the HW */ in pata_macio_do_resume()
903 pata_macio_apply_timings(priv->host->ports[0], 0); in pata_macio_do_resume()
906 enable_irq(priv->irq); in pata_macio_do_resume()
909 ata_host_resume(priv->host); in pata_macio_do_resume()
952 if (of_device_is_compatible(priv->node, "shasta-ata")) { in pata_macio_invariants()
953 priv->kind = controller_sh_ata6; in pata_macio_invariants()
954 priv->timings = pata_macio_shasta_timings; in pata_macio_invariants()
955 } else if (of_device_is_compatible(priv->node, "kauai-ata")) { in pata_macio_invariants()
956 priv->kind = controller_un_ata6; in pata_macio_invariants()
957 priv->timings = pata_macio_kauai_timings; in pata_macio_invariants()
958 } else if (of_device_is_compatible(priv->node, "K2-UATA")) { in pata_macio_invariants()
959 priv->kind = controller_k2_ata6; in pata_macio_invariants()
960 priv->timings = pata_macio_kauai_timings; in pata_macio_invariants()
961 } else if (of_device_is_compatible(priv->node, "keylargo-ata")) { in pata_macio_invariants()
962 if (of_node_name_eq(priv->node, "ata-4")) { in pata_macio_invariants()
963 priv->kind = controller_kl_ata4; in pata_macio_invariants()
964 priv->timings = pata_macio_kl66_timings; in pata_macio_invariants()
966 priv->kind = controller_kl_ata3; in pata_macio_invariants()
967 priv->timings = pata_macio_kl33_timings; in pata_macio_invariants()
969 } else if (of_device_is_compatible(priv->node, "heathrow-ata")) { in pata_macio_invariants()
970 priv->kind = controller_heathrow; in pata_macio_invariants()
971 priv->timings = pata_macio_heathrow_timings; in pata_macio_invariants()
973 priv->kind = controller_ohare; in pata_macio_invariants()
974 priv->timings = pata_macio_ohare_timings; in pata_macio_invariants()
977 /* XXX FIXME --- setup priv->mediabay here */ in pata_macio_invariants()
980 bidp = of_get_property(priv->node, "AAPL,bus-id", NULL); in pata_macio_invariants()
981 priv->aapl_bus_id = bidp ? *bidp : 0; in pata_macio_invariants()
983 /* Fixup missing Apple bus ID in case of media-bay */ in pata_macio_invariants()
984 if (priv->mediabay && !bidp) in pata_macio_invariants()
985 priv->aapl_bus_id = 1; in pata_macio_invariants()
992 ioaddr->cmd_addr = base; in pata_macio_setup_ios()
995 ioaddr->data_addr = base + (ATA_REG_DATA << 4); in pata_macio_setup_ios()
996 ioaddr->error_addr = base + (ATA_REG_ERR << 4); in pata_macio_setup_ios()
997 ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4); in pata_macio_setup_ios()
998 ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4); in pata_macio_setup_ios()
999 ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4); in pata_macio_setup_ios()
1000 ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4); in pata_macio_setup_ios()
1001 ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4); in pata_macio_setup_ios()
1002 ioaddr->device_addr = base + (ATA_REG_DEVICE << 4); in pata_macio_setup_ios()
1003 ioaddr->status_addr = base + (ATA_REG_STATUS << 4); in pata_macio_setup_ios()
1004 ioaddr->command_addr = base + (ATA_REG_CMD << 4); in pata_macio_setup_ios()
1005 ioaddr->altstatus_addr = base + 0x160; in pata_macio_setup_ios()
1006 ioaddr->ctl_addr = base + 0x160; in pata_macio_setup_ios()
1007 ioaddr->bmdma_addr = dma; in pata_macio_setup_ios()
1015 pinfo->pio_mask = 0; in pmac_macio_calc_timing_masks()
1016 pinfo->mwdma_mask = 0; in pmac_macio_calc_timing_masks()
1017 pinfo->udma_mask = 0; in pmac_macio_calc_timing_masks()
1019 while (priv->timings[i].mode > 0) { in pmac_macio_calc_timing_masks()
1020 unsigned int mask = 1U << (priv->timings[i].mode & 0x0f); in pmac_macio_calc_timing_masks()
1021 switch(priv->timings[i].mode & 0xf0) { in pmac_macio_calc_timing_masks()
1023 pinfo->pio_mask |= (mask >> 8); in pmac_macio_calc_timing_masks()
1026 pinfo->mwdma_mask |= mask; in pmac_macio_calc_timing_masks()
1028 case 0x40: /* UDMA */ in pmac_macio_calc_timing_masks()
1029 pinfo->udma_mask |= mask; in pmac_macio_calc_timing_masks()
1034 dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n", in pmac_macio_calc_timing_masks()
1035 pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask); in pmac_macio_calc_timing_masks()
1049 * device-tree in pata_macio_common_init()
1063 priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1); in pata_macio_common_init()
1064 if (priv->host == NULL) { in pata_macio_common_init()
1065 dev_err(priv->dev, "Failed to allocate ATA port structure\n"); in pata_macio_common_init()
1066 return -ENOMEM; in pata_macio_common_init()
1070 priv->host->private_data = priv; in pata_macio_common_init()
1073 priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100); in pata_macio_common_init()
1074 if (priv->tfregs == NULL) { in pata_macio_common_init()
1075 dev_err(priv->dev, "Failed to map ATA ports\n"); in pata_macio_common_init()
1076 return -ENOMEM; in pata_macio_common_init()
1078 priv->host->iomap = &priv->tfregs; in pata_macio_common_init()
1082 dma_regs = devm_ioremap(priv->dev, dmaregs, in pata_macio_common_init()
1085 dev_warn(priv->dev, "Failed to map ATA DMA registers\n"); in pata_macio_common_init()
1090 priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4); in pata_macio_common_init()
1091 if (priv->kauai_fcr == NULL) { in pata_macio_common_init()
1092 dev_err(priv->dev, "Failed to map ATA FCR register\n"); in pata_macio_common_init()
1093 return -ENOMEM; in pata_macio_common_init()
1098 pata_macio_setup_ios(&priv->host->ports[0]->ioaddr, in pata_macio_common_init()
1099 priv->tfregs, dma_regs); in pata_macio_common_init()
1100 priv->host->ports[0]->private_data = priv; in pata_macio_common_init()
1102 /* hard-reset the controller */ in pata_macio_common_init()
1104 pata_macio_apply_timings(priv->host->ports[0], 0); in pata_macio_common_init()
1107 if (priv->pdev && dma_regs) in pata_macio_common_init()
1108 pci_set_master(priv->pdev); in pata_macio_common_init()
1110 dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n", in pata_macio_common_init()
1111 macio_ata_names[priv->kind], priv->aapl_bus_id); in pata_macio_common_init()
1114 priv->irq = irq; in pata_macio_common_init()
1115 return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0, in pata_macio_common_init()
1127 /* Check for broken device-trees */ in pata_macio_attach()
1129 dev_err(&mdev->ofdev.dev, in pata_macio_attach()
1131 return -ENXIO; in pata_macio_attach()
1138 priv = devm_kzalloc(&mdev->ofdev.dev, in pata_macio_attach()
1141 return -ENOMEM; in pata_macio_attach()
1143 priv->node = of_node_get(mdev->ofdev.dev.of_node); in pata_macio_attach()
1144 priv->mdev = mdev; in pata_macio_attach()
1145 priv->dev = &mdev->ofdev.dev; in pata_macio_attach()
1148 if (macio_request_resource(mdev, 0, "pata-macio")) { in pata_macio_attach()
1149 dev_err(&mdev->ofdev.dev, in pata_macio_attach()
1151 return -EBUSY; in pata_macio_attach()
1157 if (macio_request_resource(mdev, 1, "pata-macio-dma")) in pata_macio_attach()
1158 dev_err(&mdev->ofdev.dev, in pata_macio_attach()
1166 * device-trees. in pata_macio_attach()
1168 * This is a bit bogus, it should be fixed in the device-tree itself, in pata_macio_attach()
1174 dev_warn(&mdev->ofdev.dev, in pata_macio_attach()
1181 lock_media_bay(priv->mdev->media_bay); in pata_macio_attach()
1189 unlock_media_bay(priv->mdev->media_bay); in pata_macio_attach()
1197 struct pata_macio_priv *priv = host->private_data; in pata_macio_detach()
1199 lock_media_bay(priv->mdev->media_bay); in pata_macio_detach()
1204 priv->host->private_data = NULL; in pata_macio_detach()
1208 unlock_media_bay(priv->mdev->media_bay); in pata_macio_detach()
1218 return pata_macio_do_suspend(host->private_data, mesg); in pata_macio_suspend()
1225 return pata_macio_do_resume(host->private_data); in pata_macio_resume()
1238 if (!host || !host->private_data) in pata_macio_mb_event()
1240 ap = host->ports[0]; in pata_macio_mb_event()
1241 spin_lock_irqsave(ap->lock, flags); in pata_macio_mb_event()
1242 ehi = &ap->link.eh_info; in pata_macio_mb_event()
1249 ata_for_each_dev(dev, &ap->link, ALL) in pata_macio_mb_event()
1250 dev->flags |= ATA_DFLAG_DETACH; in pata_macio_mb_event()
1253 spin_unlock_irqrestore(ap->lock, flags); in pata_macio_mb_event()
1269 dev_err(&pdev->dev, in pata_macio_pci_attach()
1271 return -ENODEV; in pata_macio_pci_attach()
1276 dev_err(&pdev->dev, in pata_macio_pci_attach()
1278 return -ENXIO; in pata_macio_pci_attach()
1282 priv = devm_kzalloc(&pdev->dev, in pata_macio_pci_attach()
1285 return -ENOMEM; in pata_macio_pci_attach()
1287 priv->node = of_node_get(np); in pata_macio_pci_attach()
1288 priv->pdev = pdev; in pata_macio_pci_attach()
1289 priv->dev = &pdev->dev; in pata_macio_pci_attach()
1292 if (pci_request_regions(pdev, "pata-macio")) { in pata_macio_pci_attach()
1293 dev_err(&pdev->dev, in pata_macio_pci_attach()
1295 return -EBUSY; in pata_macio_pci_attach()
1304 pdev->irq)) in pata_macio_pci_attach()
1305 return -ENXIO; in pata_macio_pci_attach()
1322 return pata_macio_do_suspend(host->private_data, mesg); in pata_macio_pci_suspend()
1329 return pata_macio_do_resume(host->private_data); in pata_macio_pci_resume()
1346 .name = "pata-macio",
1371 .name = "pata-pci-macio",
1391 return -ENODEV; in pata_macio_init()