Lines Matching +full:reserved +full:- +full:cpu +full:- +full:vectors
1 # SPDX-License-Identifier: GPL-2.0
58 Xtensa processors are 32-bit RISC machines designed by Tensilica
63 a home page at <http://www.linux-xtensa.org/>.
102 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
108 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
117 bool "fsf - default (not generic) configuration"
121 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
128 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
164 ie: it supports a TLB with auto-loading, page protection.
221 byte and 2-byte access to memory attached to instruction bus.
228 This option is used to indicate that the system-on-a-chip (SOC)
230 the CPU core definition and currently needs to be selected manually.
242 bool "Enable Symmetric multi-processing support"
246 Enabled SMP Software; allows more than one CPU/CORE
251 int "Maximum number of CPUs (2-32)"
256 bool "Enable CPU hotplug support"
260 controlled through /sys/devices/system/cpu.
262 Say N if you want to disable CPU hotplug.
384 On some platforms (XT2000, for example), the CPU clock rate can
410 XT2000 is the name of Tensilica's feature-rich emulation platform.
432 int "CPU clock rate [MHz]"
439 The BogoMIPS value can easily be derived from the CPU frequency.
451 architectures, you should supply some command-line options at build
498 tristate "Host file-based simulated block device support"
507 int "Number of host file-based simulated block devices"
530 Another simulated disk in a host file for a buildroot-independent
555 bool "Use 8-bit access to XTFPGA LCD"
559 LCD may be connected with 4- or 8-bit interface, 8-bit access may
560 only be used with 8-bit interface. Please consult prototyping user
576 This unfortunately won't work for U-Boot and likely also won't
582 xt-gdb can't place a Software Breakpoint in the 0XD region prior
590 Selecting this will cause U-Boot to set the KERNEL Load and Entry
596 bool "Kernel Execute-In-Place from ROM"
599 Execute-In-Place allows the kernel to run from non-volatile storage
600 directly addressable by the CPU, such as NOR flash. This saves RAM
602 to RAM. Read-write sections, such as the data section and stack,
623 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
624 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
639 3: special (c and e are illegal, f is reserved).
643 2: WB, no-write-allocate cache,
654 Unpacked kernel image (including vectors) must be located completely
683 prompt "Relocatable vectors location"
686 Choose whether relocatable vectors are merged into the kernel .text
688 configurations without VECBASE register where vectors are always
689 placed at their hardware-defined locations.
692 bool "Merge relocatable vectors into kernel text"
695 This option puts relocatable vectors into the kernel .text section
700 bool "Put relocatable vectors at fixed address"
702 This option puts relocatable vectors at specific virtual address.
703 Vectors are merged with the .init data in the kernel image and
705 Use it to put vectors into IRAM or out of FLASH on kernels with
706 XIP-aware MTD support.
711 hex "Kernel vectors virtual address"
715 This is the virtual address of the (relocatable) vectors base.