1 // SPDX-License-Identifier: GPL-2.0
3  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
19 	 * i450NX -- Find and scan all secondary buses on all PXB's.  in pci_fixup_i450nx()
24 	dev_warn(&d->dev, "Searching for i450NX host bridges\n");  in pci_fixup_i450nx()
30 		dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,  in pci_fixup_i450nx()
37 	pcibios_last_bus = -1;  in pci_fixup_i450nx()
44 	 * i450GX and i450KX -- Find and scan all secondary buses.  in pci_fixup_i450gx()
49 	dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);  in pci_fixup_i450gx()
51 	pcibios_last_bus = -1;  in pci_fixup_i450gx()
63 	dev_warn(&d->dev, "Fixing base address flags\n");  in pci_fixup_umc_ide()
65 		d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;  in pci_fixup_umc_ide()
75 	dev_dbg(&d->dev, "Setting max latency to 32\n");  in pci_fixup_latency()
86 	d->irq = 9;  in pci_fixup_piix4_acpi()
100  *  - bits  5, 6, 7 at offset 0x55 need to be turned off
102  *  - bits  5, 6, 7 at offset 0x95 need to be turned off
104  *  - bits     6, 7 at offset 0x55 need to be turned off
116 	if (d->device == PCI_DEVICE_ID_VIA_8367_0) {  in pci_fixup_via_northbridge_bug()
124 	} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&  in pci_fixup_via_northbridge_bug()
125 			(d->revision == VIA_8363_KL133_REVISION_ID ||  in pci_fixup_via_northbridge_bug()
126 			d->revision == VIA_8363_KM133_REVISION_ID)) {  in pci_fixup_via_northbridge_bug()
133 …dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x ->…  in pci_fixup_via_northbridge_bug()
134 			d->device, d->revision, where, v, mask, v & mask);  in pci_fixup_via_northbridge_bug()
150  * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
152  * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
159 	if ((dev->device & 0xff00) == 0x2400)  in pci_fixup_transparent_bridge()
160 		dev->transparent = 1;  in pci_fixup_transparent_bridge()
172  * This allows the state-machine and timer to return to a proper state within
195 		dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");  in pci_fixup_nforce2()
206 #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
210 	return raw_pci_read(pci_domain_nr(bus), bus->number,  in quirk_pcie_aspm_read()
222 	offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];  in quirk_pcie_aspm_write()
227 	return raw_pci_write(pci_domain_nr(bus), bus->number,  in quirk_pcie_aspm_write()
250 	if ((pbus = pdev->subordinate) == NULL)  in pcie_rootport_aspm_quirk()
256 	 * hot-plug driver.  in pcie_rootport_aspm_quirk()
258 	if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||  in pcie_rootport_aspm_quirk()
259 	    (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))  in pcie_rootport_aspm_quirk()
262 	if (list_empty(&pbus->devices)) {  in pcie_rootport_aspm_quirk()
264 		 * If no device is attached to the root port at power-up or  in pcie_rootport_aspm_quirk()
265 		 * after hot-remove, the pbus->devices is empty and this code  in pcie_rootport_aspm_quirk()
269 		for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)  in pcie_rootport_aspm_quirk()
272 		pci_bus_set_ops(pbus, pbus->parent->ops);  in pcie_rootport_aspm_quirk()
275 		 * If devices are attached to the root port at power-up or  in pcie_rootport_aspm_quirk()
276 		 * after hot-add, the code loops through the device list of  in pcie_rootport_aspm_quirk()
280 		list_for_each_entry(dev, &pbus->devices, bus_list)  in pcie_rootport_aspm_quirk()
282 			quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =  in pcie_rootport_aspm_quirk()
283 				dev->pcie_cap + PCI_EXP_LNKCTL;  in pcie_rootport_aspm_quirk()
286 		dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");  in pcie_rootport_aspm_quirk()
310  * by either arch code or vga-arbitration; if so only apply the fixup to this
311  * already-determined primary video card.
322 	bus = pdev->bus;  in pci_fixup_video()
324 		bridge = bus->self;  in pci_fixup_video()
339 		bus = bus->parent;  in pci_fixup_video()
344 			res = &pdev->resource[PCI_ROM_RESOURCE];  in pci_fixup_video()
347 			if (res->parent)  in pci_fixup_video()
350 			res->start = 0xC0000;  in pci_fixup_video()
351 			res->end = res->start + 0x20000 - 1;  in pci_fixup_video()
352 			res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |  in pci_fixup_video()
354 			dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",  in pci_fixup_video()
365 		.ident = "MSI-K8T-Neo2Fir",
368 			DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
375  * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
376  * card if a PCI-soundcard is added.
379  * the corresponding register-value to enable the soundcard.
382  * via DMI-tables and the soundcard is detected to be off.
388 		return; /* only applies to MSI K8T Neo2-FIR */  in pci_fixup_msi_k8t_onboard_sound()
397 			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "  in pci_fixup_msi_k8t_onboard_sound()
400 			dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "  in pci_fixup_msi_k8t_onboard_sound()
450 	dev->current_state = PCI_D3cold;  in pci_pre_fixup_toshiba_ohci1394()
463 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);  in pci_post_fixup_toshiba_ohci1394()
496 	dev->resource[0].flags |= IORESOURCE_PCI_FIXED;  in pci_siemens_interrupt_controller()
532 	struct resource *r = &dev->resource[1];  in sb600_hpet_quirk()
534 	if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {  in sb600_hpet_quirk()
535 		r->flags |= IORESOURCE_PCI_FIXED;  in sb600_hpet_quirk()
536 		dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");  in sb600_hpet_quirk()
544  * there and any access kills the box.
552         if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {  in twinhead_reserve_killing_zone()
563  * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
567  * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
568  * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
572 	dev->non_compliant_bars = 1;  in pci_invalid_bar()
592 	dev_info(&dev->dev, "PME# does not work under D3, disabling it\n");  in pci_fixup_amd_ehci_pme()
593 	dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold)  in pci_fixup_amd_ehci_pme()
604 	dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");  in pci_fixup_amd_fch_xhci_pme()
605 	dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);  in pci_fixup_amd_fch_xhci_pme()
610  * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
612  * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
614  * for soft poweroff and suspend-to-RAM.
617  * Port itself.  Attaching the quirk to the Root Port is a convenience, but
618  * it could probably also be a standalone DMI quirk.
624 	struct device *dev = &pdev->dev;  in quirk_apple_mbp_poweroff()
629 	    pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0))  in quirk_apple_mbp_poweroff()
635 		dev_info(dev, "claimed %s %pR\n", res->name, res);  in quirk_apple_mbp_poweroff()
642  * VMD-enabled root ports will change the source ID for all messages
650 	if (is_vmd(pdev->bus) && pci_is_root_bus(pdev->bus))  in quirk_no_aersid()
651 		pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;  in quirk_no_aersid()
658 	struct resource *r = &dev->resource[4];  in quirk_intel_th_dnv()
664 	if (r->end == r->start + 0x7ff) {  in quirk_intel_th_dnv()
665 		r->start = 0;  in quirk_intel_th_dnv()
666 		r->end   = 0x3fffff;  in quirk_intel_th_dnv()
667 		r->flags |= IORESOURCE_UNSET;  in quirk_intel_th_dnv()
692  * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
707 	other = pci_get_device(dev->vendor, dev->device, NULL);  in pci_amd_enable_64bit_bar()
709 	    (other = pci_get_device(dev->vendor, dev->device, other))) {  in pci_amd_enable_64bit_bar()
710 		/* This is a multi-socket system, don't touch it for now */  in pci_amd_enable_64bit_bar()
740 	 * limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6).  in pci_amd_enable_64bit_bar()
742 	res->name = name;  in pci_amd_enable_64bit_bar()
743 	res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |  in pci_amd_enable_64bit_bar()
745 	res->start = 0xbd00000000ull;  in pci_amd_enable_64bit_bar()
746 	res->end = 0xfd00000000ull - 1;  in pci_amd_enable_64bit_bar()
751 		if (conflict->name != name)  in pci_amd_enable_64bit_bar()
757 		dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",  in pci_amd_enable_64bit_bar()
760 		pci_bus_add_resource(dev->bus, res, 0);  in pci_amd_enable_64bit_bar()
763 	base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |  in pci_amd_enable_64bit_bar()
765 	limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;  in pci_amd_enable_64bit_bar()
766 	high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |  in pci_amd_enable_64bit_bar()
767 		((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)  in pci_amd_enable_64bit_bar()
798  * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57)
804 	phys_addr_t top_of_dram = __pa(high_memory - 1) + 1;  in rs690_fix_64bit_dma()
816 	pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram);  in rs690_fix_64bit_dma()
857  * Save those values at enumeration-time and restore them at resume.
911  * Disable D3cold on Asus B1400 PCI-NVMe bridge
961  * if the SoC is put into a hardware sleep state by the amd-pmc driver, the
974 	 * amd-pmc will not be involved so PMEs during D3 work as advertised.  in amd_rp_pme_suspend()
976 	 * The PMEs *do* work if amd-pmc doesn't put the SoC in the hardware  in amd_rp_pme_suspend()
977 	 * sleep state, but we assume amd-pmc is always present.  in amd_rp_pme_suspend()
983 	if (!rp || !rp->pm_cap)  in amd_rp_pme_suspend()
986 	rp->pme_support &= ~((PCI_PM_CAP_PME_D3hot|PCI_PM_CAP_PME_D3cold) >>  in amd_rp_pme_suspend()
988 	dev_info_once(&rp->dev, "quirk: disabling D3cold for suspend\n");  in amd_rp_pme_suspend()
997 	if (!rp || !rp->pm_cap)  in amd_rp_pme_resume()
1000 	pci_read_config_word(rp, rp->pm_cap + PCI_PM_PMC, &pmc);  in amd_rp_pme_resume()
1001 	rp->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc);  in amd_rp_pme_resume()
1039 			root_pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;  in quirk_tuxeo_rp_d3()