Lines Matching refs:dst_hi
168 #define dst_hi dst[1] macro
263 emit_ia32_mov_r(dst_hi, src_hi, dstk, sstk, pprog); in emit_ia32_mov_r64()
266 emit_ia32_mov_i(dst_hi, 0, dstk, pprog); in emit_ia32_mov_r64()
278 emit_ia32_mov_i(dst_hi, hi, dstk, pprog); in emit_ia32_mov_i64()
324 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_to_le_r64()
330 STACK_VAR(dst_hi)); in emit_ia32_to_le_r64()
360 STACK_VAR(dst_hi)); in emit_ia32_to_le_r64()
372 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_to_be_r64()
378 STACK_VAR(dst_hi)); in emit_ia32_to_be_r64()
426 STACK_VAR(dst_hi)); in emit_ia32_to_be_r64()
586 emit_ia32_alu_r(is64, true, op, dst_hi, src_hi, dstk, sstk, in emit_ia32_alu_r64()
589 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in emit_ia32_alu_r64()
690 emit_ia32_alu_i(is64, true, op, dst_hi, hi, dstk, &prog); in emit_ia32_alu_i64()
692 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in emit_ia32_alu_i64()
703 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_neg64()
709 STACK_VAR(dst_hi)); in emit_ia32_neg64()
725 STACK_VAR(dst_hi)); in emit_ia32_neg64()
737 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_lsh_r64()
743 STACK_VAR(dst_hi)); in emit_ia32_lsh_r64()
777 STACK_VAR(dst_hi)); in emit_ia32_lsh_r64()
790 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_arsh_r64()
796 STACK_VAR(dst_hi)); in emit_ia32_arsh_r64()
830 STACK_VAR(dst_hi)); in emit_ia32_arsh_r64()
843 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_rsh_r64()
849 STACK_VAR(dst_hi)); in emit_ia32_rsh_r64()
883 STACK_VAR(dst_hi)); in emit_ia32_rsh_r64()
896 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_lsh_i64()
902 STACK_VAR(dst_hi)); in emit_ia32_lsh_i64()
932 STACK_VAR(dst_hi)); in emit_ia32_lsh_i64()
944 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_rsh_i64()
950 STACK_VAR(dst_hi)); in emit_ia32_rsh_i64()
981 STACK_VAR(dst_hi)); in emit_ia32_rsh_i64()
993 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in emit_ia32_arsh_i64()
999 STACK_VAR(dst_hi)); in emit_ia32_arsh_i64()
1030 STACK_VAR(dst_hi)); in emit_ia32_arsh_i64()
1044 STACK_VAR(dst_hi)); in emit_ia32_mul_r64()
1047 EMIT2(0x8B, add_2reg(0xC0, dst_hi, IA32_EAX)); in emit_ia32_mul_r64()
1101 STACK_VAR(dst_hi)); in emit_ia32_mul_r64()
1106 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX)); in emit_ia32_mul_r64()
1124 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi)); in emit_ia32_mul_i64()
1127 EMIT2(0xF7, add_1reg(0xE0, dst_hi)); in emit_ia32_mul_i64()
1161 STACK_VAR(dst_hi)); in emit_ia32_mul_i64()
1166 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX)); in emit_ia32_mul_i64()
1697 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1767 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1788 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1811 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1829 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1866 emit_ia32_mov_i(dst_hi, 0, dstk, &prog); in do_jit()
1900 emit_ia32_mov_i(dst_hi, hi, dstk, &prog); in do_jit()
2057 STACK_VAR(dst_hi)); in do_jit()
2062 add_2reg(0xC0, dst_hi, dst_hi)); in do_jit()
2073 STACK_VAR(dst_hi)); in do_jit()
2076 add_2reg(0xC0, dst_hi, IA32_EDX)); in do_jit()
2163 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2174 STACK_VAR(dst_hi)); in do_jit()
2201 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2211 STACK_VAR(dst_hi)); in do_jit()
2245 STACK_VAR(dst_hi)); in do_jit()
2252 add_2reg(0xC0, dreg_hi, dst_hi)); in do_jit()
2290 STACK_VAR(dst_hi)); in do_jit()
2297 add_2reg(0xC0, dreg_hi, dst_hi)); in do_jit()
2334 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2346 STACK_VAR(dst_hi)); in do_jit()
2381 u8 dreg_hi = dstk ? IA32_EDX : dst_hi; in do_jit()
2392 STACK_VAR(dst_hi)); in do_jit()