Lines Matching +full:0 +full:x8000000a
132 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18,
134 * intercept the MSR 0x832, and do not setup direct_access_msr.
259 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
270 for (i = 0; i < NUM_MSR_MAPS; i++) { in svm_msrpm_offset()
346 return 0; in svm_set_efer()
352 u32 ret = 0; in svm_get_interrupt_shadow()
363 if (mask == 0) in svm_set_interrupt_shadow()
385 if (nrips && svm->vmcb->control.next_rip != 0) { in __svm_skip_emulated_instruction()
396 if (!svm_can_emulate_instruction(vcpu, EMULTYPE_SKIP, NULL, 0)) in __svm_skip_emulated_instruction()
397 return 0; in __svm_skip_emulated_instruction()
403 return 0; in __svm_skip_emulated_instruction()
413 svm_set_interrupt_shadow(vcpu, 0); in __svm_skip_emulated_instruction()
465 return 0; in svm_update_soft_interrupt_rip()
481 | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0) in svm_inject_exception()
521 * all osvw.status bits inside that length, including bit 0 (which is in svm_init_osvw()
523 * osvw_len is 0 then osvw_status[0] carries no information. We need to in svm_init_osvw()
527 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10) in svm_init_osvw()
579 return 0; in svm_check_processor_compat()
595 wrmsrl(MSR_VM_HSAVE_PA, 0); in kvm_cpu_svm_disable()
665 uint64_t len, status = 0; in svm_hardware_enable()
674 osvw_status = osvw_len = 0; in svm_hardware_enable()
682 osvw_status = osvw_len = 0; in svm_hardware_enable()
698 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); in svm_hardware_enable()
703 return 0; in svm_hardware_enable()
715 sd->save_area_pa = 0; in svm_cpu_uninit()
724 memset(sd, 0, sizeof(struct svm_cpu_data)); in svm_cpu_init()
734 return 0; in svm_cpu_init()
771 vmcb->control.intercepts[INTERCEPT_DR] = 0; in clr_dr_intercepts()
780 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) in direct_access_msr_slot()
833 bit_write = 2 * (msr & 0x0f) + 1; in msr_write_intercepted()
857 read = 0; in set_msr_interception_bitmap()
860 write = 0; in set_msr_interception_bitmap()
863 bit_read = 2 * (msr & 0x0f); in set_msr_interception_bitmap()
864 bit_write = 2 * (msr & 0x0f) + 1; in set_msr_interception_bitmap()
895 memset(msrpm, 0xff, PAGE_SIZE * (1 << order)); in svm_vcpu_alloc_msrpm()
904 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { in svm_vcpu_init_msrpm()
921 for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) { in svm_set_x2apic_msr_interception()
925 (index > APIC_BASE_MSR + 0xff)) in svm_set_x2apic_msr_interception()
949 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { in svm_msr_filter_changed()
962 for (i = 0; i < MSRPM_OFFSETS; ++i) { in add_msr_offset()
989 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets)); in init_msrpm_offsets()
991 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) { in init_msrpm_offsets()
1037 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); in svm_disable_lbrv()
1038 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); in svm_disable_lbrv()
1039 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); in svm_disable_lbrv()
1040 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0); in svm_disable_lbrv()
1144 iopm_base = 0; in svm_hardware_unsetup()
1149 seg->selector = 0; in init_seg()
1152 seg->limit = 0xffff; in init_seg()
1153 seg->base = 0; in init_seg()
1158 seg->selector = 0; in init_sys_seg()
1160 seg->limit = 0xffff; in init_sys_seg()
1161 seg->base = 0; in init_sys_seg()
1233 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0); in init_vmcb_after_set_cpuid()
1234 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0); in init_vmcb_after_set_cpuid()
1329 save->cs.selector = 0xf000; in init_vmcb()
1330 save->cs.base = 0xffff0000; in init_vmcb()
1334 save->cs.limit = 0xffff; in init_vmcb()
1336 save->gdtr.base = 0; in init_vmcb()
1337 save->gdtr.limit = 0xffff; in init_vmcb()
1338 save->idtr.base = 0; in init_vmcb()
1339 save->idtr.limit = 0xffff; in init_vmcb()
1352 save->cr3 = 0; in init_vmcb()
1354 svm->current_vmcb->asid_generation = 0; in init_vmcb()
1355 svm->asid = 0; in init_vmcb()
1408 vcpu->arch.microcode_version = 0x01000065; in __svm_vcpu_reset()
1422 svm->spec_ctrl = 0; in svm_vcpu_reset()
1423 svm->virt_spec_ctrl = 0; in svm_vcpu_reset()
1444 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0); in svm_vcpu_create()
1491 return 0; in svm_vcpu_create()
1548 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); in svm_prepare_switch_to_guest()
1562 if (likely(tsc_aux_uret_slot >= 0) && in svm_prepare_switch_to_guest()
1669 * Requesting an interrupt window if save.RFLAGS.IF=0 is pointless as in svm_set_vintr()
1680 control->int_vector = 0x0; in svm_set_vintr()
1683 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); in svm_set_vintr()
1758 var->g = s->limit > 0xfffff; in svm_get_segment()
1772 var->type |= 0x2; in svm_get_segment()
1786 var->type |= 0x1; in svm_get_segment()
1796 var->db = 0; in svm_get_segment()
2037 get_debugreg(vcpu->arch.db[0], 0); in svm_sync_dirty_debug_regs()
2116 return 0; in db_interception()
2130 return 0; in bp_interception()
2140 kvm_queue_exception_e(vcpu, AC_VECTOR, 0); in ac_interception()
2159 if (value != 0xb600000000010015ULL) in is_erratum_383()
2163 for (i = 0; i < 6; ++i) in is_erratum_383()
2164 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0); in is_erratum_383()
2233 return 0; in shutdown_interception()
2244 string = (io_info & SVM_IOIO_STR_MASK) != 0; in io_interception()
2245 in = (io_info & SVM_IOIO_TYPE_MASK) != 0; in io_interception()
2253 return kvm_emulate_instruction(vcpu, 0); in io_interception()
2290 kvm_inject_gp(vcpu, 0); in vmload_vmsave_interception()
2300 svm->sysenter_eip_hi = 0; in vmload_vmsave_interception()
2301 svm->sysenter_esp_hi = 0; in vmload_vmsave_interception()
2341 if (ctxt->b != 0x1 || ctxt->opcode_len != 2) in svm_instr_opcode()
2345 case 0xd8: /* VMRUN */ in svm_instr_opcode()
2347 case 0xda: /* VMLOAD */ in svm_instr_opcode()
2349 case 0xdb: /* VMSAVE */ in svm_instr_opcode()
2374 /* Returns '1' or -errno on failure, '0' on success. */ in emulate_svm_instr()
2402 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK) in gp_interception()
2526 u32 error_code = 0; in task_switch_interception()
2569 return 0; in task_switch_interception()
2610 return kvm_emulate_instruction(vcpu, 0); in invlpg_interception()
2618 return kvm_emulate_instruction(vcpu, 0); in emulate_on_interception()
2660 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0)) in cr_interception()
2669 err = 0; in cr_interception()
2675 case 0: in cr_interception()
2698 case 0: in cr_interception()
2729 int ret = 0; in cr_trap()
2735 case 0: in cr_trap()
2764 int err = 0; in dr_interception()
2773 if (vcpu->guest_debug == 0) { in dr_interception()
2813 return 0; in cr8_write_interception()
2837 msr->data = 0; in svm_get_msr_feature()
2848 return 0; in svm_get_msr_feature()
2946 if (family < 0 || model < 0) in svm_get_msr()
2949 msr_info->data = 0; in svm_get_msr()
2951 if (family == 0x15 && in svm_get_msr()
2952 (model >= 0x2 && model < 0x20)) in svm_get_msr()
2953 msr_info->data = 0x1E; in svm_get_msr()
2962 return 0; in svm_get_msr()
3001 return 0; in svm_set_vm_cr()
3007 int ret = 0; in svm_set_msr()
3022 * Due to bug in qemu 6.2.0, it would try to set in svm_set_msr()
3023 * this msr to 0 if tsc scaling is not enabled. in svm_set_msr()
3026 if (data != 0 && data != svm->tsc_ratio_msr) in svm_set_msr()
3124 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0; in svm_set_msr()
3128 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0; in svm_set_msr()
3266 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0; in pause_interception()
3385 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff); in dump_vmcb()
3387 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff); in dump_vmcb()
3501 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code); in svm_handle_invalid_exit()
3506 vcpu->run->internal.data[0] = exit_code; in svm_handle_invalid_exit()
3508 return 0; in svm_handle_invalid_exit()
3545 *error_code = 0; in svm_get_exit_info()
3582 return 0; in svm_handle_exit()
3602 svm->current_vmcb->asid_generation = 0; in pre_svm_run()
3810 return 0; in svm_nmi_allowed()
3852 return 0; in svm_interrupt_allowed()
3869 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes in svm_enable_irq_window()
3910 * if the vCPU is in an STI shadow or if GIF=0, KVM can't immediately in svm_enable_nmi_window()
4146 control->event_inj = 0; in svm_cancel_injection()
4253 vcpu->arch.regs_dirty = 0; in svm_vcpu_run()
4268 svm->next_rip = 0; in svm_vcpu_run()
4277 svm->nested.nested_run_pending = 0; in svm_vcpu_run()
4339 hypercall[0] = 0x0f; in svm_patch_hypercall()
4340 hypercall[1] = 0x01; in svm_patch_hypercall()
4341 hypercall[2] = 0xd9; in svm_patch_hypercall()
4407 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, in svm_vcpu_after_set_cpuid()
4411 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_FLUSH_CMD, 0, in svm_vcpu_after_set_cpuid()
4530 cr0 &= 0xfUL; in svm_check_intercept()
4531 val &= 0xfUL; in svm_check_intercept()
4550 vmcb->control.exit_info_1 = 0; in svm_check_intercept()
4566 exit_info = ((info->src_val & 0xffff) << 16) | in svm_check_intercept()
4570 exit_info = (info->dst_val & 0xffff) << 16; in svm_check_intercept()
4624 vcpu->arch.mcg_cap &= 0x1ff; in svm_setup_mce()
4646 return 0; in svm_smi_allowed()
4662 return 0; in svm_enter_smm()
4689 * by 0x400 (matches the offset of 'struct vmcb_save_area' in svm_enter_smm()
4698 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400); in svm_enter_smm()
4700 svm_copy_vmrun_state(map_save.hva + 0x400, in svm_enter_smm()
4704 return 0; in svm_enter_smm()
4717 return 0; in svm_leave_smm()
4721 return 0; in svm_leave_smm()
4744 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400); in svm_leave_smm()
4858 * be '0'. This happens because microcode reads CS:RIP using a _data_ in svm_can_emulate_instruction()
4859 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode in svm_can_emulate_instruction()
4864 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the in svm_can_emulate_instruction()
4874 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot in svm_can_emulate_instruction()
4904 kvm_inject_gp(vcpu, 0); in svm_can_emulate_instruction()
4913 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to in svm_can_emulate_instruction()
4959 return 0; in svm_vm_init()
5109 if (cpuid_eax(0x80000000) < 0x8000001f) in svm_adjust_mmio_mask()
5117 enc_bit = cpuid_ebx(0x8000001f) & 0x3f; in svm_adjust_mmio_mask()
5133 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0; in svm_adjust_mmio_mask()
5142 kvm_caps.supported_perf_cap = 0; in svm_set_cpu_caps()
5143 kvm_caps.supported_xss = 0; in svm_set_cpu_caps()
5145 /* CPUID 0x80000001 and 0x8000000A (SVM features) */ in svm_set_cpu_caps()
5180 /* CPUID 0x80000008 */ in svm_set_cpu_caps()
5202 /* CPUID 0x8000001F (SME/SEV features) */ in svm_set_cpu_caps()
5233 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order)); in svm_hardware_setup()
5262 pause_filter_count = 0; in svm_hardware_setup()
5263 pause_filter_thresh = 0; in svm_hardware_setup()
5265 pause_filter_thresh = 0; in svm_hardware_setup()
5375 return 0; in svm_hardware_setup()
5421 return 0; in svm_init()