Lines Matching +full:reserved +full:- +full:ipi +full:- +full:vectors
1 // SPDX-License-Identifier: GPL-2.0-only
50 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
67 /* step-by-step approximation to mitigate fluctuation */
79 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
90 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
102 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
112 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi()
114 return apic_test_vector(vector, apic->regs + APIC_ISR) || in kvm_apic_pending_eoi()
115 apic_test_vector(vector, apic->regs + APIC_IRR); in kvm_apic_pending_eoi()
145 return apic->vcpu->vcpu_id; in kvm_x2apic_id()
151 (kvm_mwait_in_guest(vcpu->kvm) || kvm_hlt_in_guest(vcpu->kvm)); in kvm_can_post_timer_interrupt()
157 && !(kvm_mwait_in_guest(vcpu->kvm) || in kvm_can_use_hv_timer()
163 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE; in kvm_use_posted_timer_interrupt()
173 switch (map->logical_mode) { in kvm_apic_map_get_logical_dest()
176 *cluster = map->xapic_flat_map; in kvm_apic_map_get_logical_dest()
181 u32 max_apic_id = map->max_apic_id; in kvm_apic_map_get_logical_dest()
184 u8 cluster_size = min(max_apic_id - offset + 1, 16U); in kvm_apic_map_get_logical_dest()
186 offset = array_index_nospec(offset, map->max_apic_id + 1); in kvm_apic_map_get_logical_dest()
187 *cluster = &map->phys_map[offset]; in kvm_apic_map_get_logical_dest()
188 *mask = dest_id & (0xffff >> (16 - cluster_size)); in kvm_apic_map_get_logical_dest()
196 *cluster = map->xapic_flat_map; in kvm_apic_map_get_logical_dest()
200 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf]; in kvm_apic_map_get_logical_dest()
222 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_phys_map()
232 if (WARN_ON_ONCE(xapic_id > new->max_apic_id)) in kvm_recalculate_phys_map()
233 return -EINVAL; in kvm_recalculate_phys_map()
241 if (x2apic_id > new->max_apic_id) in kvm_recalculate_phys_map()
242 return -E2BIG; in kvm_recalculate_phys_map()
247 * 32-bit value. Any unwanted aliasing due to truncation results will in kvm_recalculate_phys_map()
250 if (!apic_x2apic_mode(apic) && xapic_id != (u8)vcpu->vcpu_id) in kvm_recalculate_phys_map()
254 * Apply KVM's hotplug hack if userspace has enable 32-bit APIC IDs. in kvm_recalculate_phys_map()
260 * Honor the architectural (and KVM's non-optimized) behavior if in kvm_recalculate_phys_map()
261 * userspace has not enabled 32-bit x2APIC IDs. Each APIC is supposed in kvm_recalculate_phys_map()
267 if (vcpu->kvm->arch.x2apic_format) { in kvm_recalculate_phys_map()
270 new->phys_map[x2apic_id] = apic; in kvm_recalculate_phys_map()
272 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) in kvm_recalculate_phys_map()
273 new->phys_map[xapic_id] = apic; in kvm_recalculate_phys_map()
285 if (new->phys_map[physical_id]) in kvm_recalculate_phys_map()
286 return -EINVAL; in kvm_recalculate_phys_map()
288 new->phys_map[physical_id] = apic; in kvm_recalculate_phys_map()
297 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_logical_map()
303 if (new->logical_mode == KVM_APIC_MODE_MAP_DISABLED) in kvm_recalculate_logical_map()
324 * To optimize logical mode delivery, all software-enabled APICs must in kvm_recalculate_logical_map()
327 if (new->logical_mode == KVM_APIC_MODE_SW_DISABLED) { in kvm_recalculate_logical_map()
328 new->logical_mode = logical_mode; in kvm_recalculate_logical_map()
329 } else if (new->logical_mode != logical_mode) { in kvm_recalculate_logical_map()
330 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED; in kvm_recalculate_logical_map()
335 * In x2APIC mode, the LDR is read-only and derived directly from the in kvm_recalculate_logical_map()
346 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED; in kvm_recalculate_logical_map()
353 ldr = ffs(mask) - 1; in kvm_recalculate_logical_map()
355 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED; in kvm_recalculate_logical_map()
361 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
363 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
381 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */ in kvm_recalculate_apic_map()
382 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN) in kvm_recalculate_apic_map()
386 "Dirty APIC map without an in-kernel local APIC"); in kvm_recalculate_apic_map()
388 mutex_lock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
392 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map (if clean) in kvm_recalculate_apic_map()
395 * ID, i.e. the map may still show up as in-progress. In that case in kvm_recalculate_apic_map()
398 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty, in kvm_recalculate_apic_map()
401 mutex_unlock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
416 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); in kvm_recalculate_apic_map()
425 new->max_apic_id = max_id; in kvm_recalculate_apic_map()
426 new->logical_mode = KVM_APIC_MODE_SW_DISABLED; in kvm_recalculate_apic_map()
436 if (r == -E2BIG) { in kvm_recalculate_apic_map()
457 if (!new || new->logical_mode == KVM_APIC_MODE_MAP_DISABLED) in kvm_recalculate_apic_map()
467 old = rcu_dereference_protected(kvm->arch.apic_map, in kvm_recalculate_apic_map()
468 lockdep_is_held(&kvm->arch.apic_map_lock)); in kvm_recalculate_apic_map()
469 rcu_assign_pointer(kvm->arch.apic_map, new); in kvm_recalculate_apic_map()
471 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. in kvm_recalculate_apic_map()
474 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty, in kvm_recalculate_apic_map()
476 mutex_unlock(&kvm->arch.apic_map_lock); in kvm_recalculate_apic_map()
479 call_rcu(&old->rcu, kvm_apic_map_free); in kvm_recalculate_apic_map()
490 if (enabled != apic->sw_enabled) { in apic_set_spiv()
491 apic->sw_enabled = enabled; in apic_set_spiv()
497 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in apic_set_spiv()
502 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu); in apic_set_spiv()
503 kvm_xen_sw_enable_lapic(apic->vcpu); in apic_set_spiv()
510 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_xapic_id()
516 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_ldr()
522 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_dfr()
529 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); in kvm_apic_set_x2apic_id()
533 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_x2apic_id()
543 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; in apic_lvtt_oneshot()
548 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; in apic_lvtt_period()
553 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; in apic_lvtt_tscdeadline()
563 return apic->nr_lvt_entries > lvt_index; in kvm_lapic_lvt_supported()
568 return KVM_APIC_MAX_NR_LVT_ENTRIES - !(vcpu->arch.mcg_cap & MCG_CMCI_P); in kvm_apic_calc_nr_lvt_entries()
573 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_version()
579 v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16); in kvm_apic_set_version()
582 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation) in kvm_apic_set_version()
584 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC in kvm_apic_set_version()
585 * version first and level-triggered interrupts never get EOIed in in kvm_apic_set_version()
589 !ioapic_in_kernel(vcpu->kvm)) in kvm_apic_set_version()
597 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_after_set_mcg_cap()
600 if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries) in kvm_apic_after_set_mcg_cap()
604 for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++) in kvm_apic_after_set_mcg_cap()
607 apic->nr_lvt_entries = nr_lvt_entries; in kvm_apic_after_set_mcg_cap()
628 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; in find_highest_vector()
629 vec >= 0; vec -= APIC_VECTORS_PER_REG) { in find_highest_vector()
635 return -1; in find_highest_vector()
658 max_updated_irr = -1; in __kvm_apic_update_irr()
659 *max_irr = -1; in __kvm_apic_update_irr()
683 return ((max_updated_irr != -1) && in __kvm_apic_update_irr()
690 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_irr()
691 bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr); in kvm_apic_update_irr()
693 if (unlikely(!apic->apicv_active && irr_updated)) in kvm_apic_update_irr()
694 apic->irr_pending = true; in kvm_apic_update_irr()
701 return find_highest_vector(apic->regs + APIC_IRR); in apic_search_irr()
712 if (!apic->irr_pending) in apic_find_highest_irr()
713 return -1; in apic_find_highest_irr()
716 ASSERT(result == -1 || result >= 16); in apic_find_highest_irr()
723 if (unlikely(apic->apicv_active)) { in apic_clear_irr()
725 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
726 static_call_cond(kvm_x86_hwapic_irr_update)(apic->vcpu, in apic_clear_irr()
729 apic->irr_pending = false; in apic_clear_irr()
730 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
731 if (apic_search_irr(apic) != -1) in apic_clear_irr()
732 apic->irr_pending = true; in apic_clear_irr()
738 apic_clear_irr(vec, vcpu->arch.apic); in kvm_apic_clear_irr()
744 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) in apic_set_isr()
752 if (unlikely(apic->apicv_active)) in apic_set_isr()
755 ++apic->isr_count; in apic_set_isr()
756 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); in apic_set_isr()
762 apic->highest_isr_cache = vec; in apic_set_isr()
772 * is always -1, with APIC virtualization enabled. in apic_find_highest_isr()
774 if (!apic->isr_count) in apic_find_highest_isr()
775 return -1; in apic_find_highest_isr()
776 if (likely(apic->highest_isr_cache != -1)) in apic_find_highest_isr()
777 return apic->highest_isr_cache; in apic_find_highest_isr()
779 result = find_highest_vector(apic->regs + APIC_ISR); in apic_find_highest_isr()
780 ASSERT(result == -1 || result >= 16); in apic_find_highest_isr()
787 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) in apic_clear_isr()
792 * uses the Hyper-V APIC enlightenment. In this case we may need in apic_clear_isr()
797 if (unlikely(apic->apicv_active)) in apic_clear_isr()
800 --apic->isr_count; in apic_clear_isr()
801 BUG_ON(apic->isr_count < 0); in apic_clear_isr()
802 apic->highest_isr_cache = -1; in apic_clear_isr()
813 return apic_find_highest_irr(vcpu->arch.apic); in kvm_lapic_find_highest_irr()
824 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_irq()
826 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, in kvm_apic_set_irq()
827 irq->level, irq->trig_mode, dest_map); in kvm_apic_set_irq()
836 if (min > map->max_apic_id) in __pv_send_ipi()
840 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) { in __pv_send_ipi()
841 if (map->phys_map[min + i]) { in __pv_send_ipi()
842 vcpu = map->phys_map[min + i]->vcpu; in __pv_send_ipi()
860 return -KVM_EINVAL; in kvm_pv_send_ipi()
868 map = rcu_dereference(kvm->arch.apic_map); in kvm_pv_send_ipi()
870 count = -EOPNOTSUPP; in kvm_pv_send_ipi()
884 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, in pv_eoi_put_user()
891 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, in pv_eoi_get_user()
897 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; in pv_eoi_enabled()
905 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); in pv_eoi_set_pending()
925 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); in pv_eoi_test_and_clr_pending()
934 highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); in apic_has_interrupt_for_ppr()
937 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr) in apic_has_interrupt_for_ppr()
938 return -1; in apic_has_interrupt_for_ppr()
950 isrv = (isr != -1) ? isr : 0; in __apic_update_ppr()
969 apic_has_interrupt_for_ppr(apic, ppr) != -1) in apic_update_ppr()
970 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_update_ppr()
975 apic_update_ppr(vcpu->arch.apic); in kvm_apic_update_ppr()
1039 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
1043 * - in-kernel IOAPIC messages have to be delivered directly to
1046 * rewrites the destination of non-IPI messages from APIC_BROADCAST
1050 * important when userspace wants to use x2APIC-format MSIs, because
1051 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
1056 bool ipi = source != NULL; in kvm_apic_mda() local
1058 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled && in kvm_apic_mda()
1059 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target)) in kvm_apic_mda()
1068 struct kvm_lapic *target = vcpu->arch.apic; in kvm_apic_match_dest()
1094 int i, idx = -1; in kvm_vector_to_index()
1108 if (!kvm->arch.disabled_lapic_found) { in kvm_apic_disabled_lapic_found()
1109 kvm->arch.disabled_lapic_found = true; in kvm_apic_disabled_lapic_found()
1117 if (kvm->arch.x2apic_broadcast_quirk_disabled) { in kvm_apic_is_broadcast_dest()
1118 if ((irq->dest_id == APIC_BROADCAST && in kvm_apic_is_broadcast_dest()
1119 map->logical_mode != KVM_APIC_MODE_X2APIC)) in kvm_apic_is_broadcast_dest()
1121 if (irq->dest_id == X2APIC_BROADCAST) in kvm_apic_is_broadcast_dest()
1125 if (irq->dest_id == (x2apic_ipi ? in kvm_apic_is_broadcast_dest()
1147 if (irq->shorthand == APIC_DEST_SELF && src) { in kvm_apic_map_get_dest_lapic()
1151 } else if (irq->shorthand) in kvm_apic_map_get_dest_lapic()
1157 if (irq->dest_mode == APIC_DEST_PHYSICAL) { in kvm_apic_map_get_dest_lapic()
1158 if (irq->dest_id > map->max_apic_id) { in kvm_apic_map_get_dest_lapic()
1161 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1); in kvm_apic_map_get_dest_lapic()
1162 *dst = &map->phys_map[dest_id]; in kvm_apic_map_get_dest_lapic()
1169 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, in kvm_apic_map_get_dest_lapic()
1177 lowest = -1; in kvm_apic_map_get_dest_lapic()
1183 else if (kvm_apic_compare_prio((*dst)[i]->vcpu, in kvm_apic_map_get_dest_lapic()
1184 (*dst)[lowest]->vcpu) < 0) in kvm_apic_map_get_dest_lapic()
1191 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), in kvm_apic_map_get_dest_lapic()
1215 *r = -1; in kvm_irq_delivery_to_apic_fast()
1217 if (irq->shorthand == APIC_DEST_SELF) { in kvm_irq_delivery_to_apic_fast()
1222 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); in kvm_irq_delivery_to_apic_fast()
1227 map = rcu_dereference(kvm->arch.apic_map); in kvm_irq_delivery_to_apic_fast()
1235 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); in kvm_irq_delivery_to_apic_fast()
1246 * - For single-destination interrupts, handle it in posted mode
1247 * - Else if vector hashing is enabled and it is a lowest-priority
1250 * 1. For lowest-priority interrupts, store all the possible
1253 * the right destination vCPU in the array for the lowest-priority
1255 * - Otherwise, use remapped mode to inject the interrupt.
1265 if (irq->shorthand) in kvm_intr_is_single_vcpu_fast()
1269 map = rcu_dereference(kvm->arch.apic_map); in kvm_intr_is_single_vcpu_fast()
1276 *dest_vcpu = dst[i]->vcpu; in kvm_intr_is_single_vcpu_fast()
1294 struct kvm_vcpu *vcpu = apic->vcpu; in __apic_accept_irq()
1296 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, in __apic_accept_irq()
1300 vcpu->arch.apic_arb_prio++; in __apic_accept_irq()
1313 __set_bit(vcpu->vcpu_id, dest_map->map); in __apic_accept_irq()
1314 dest_map->vectors[vcpu->vcpu_id] = vector; in __apic_accept_irq()
1317 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { in __apic_accept_irq()
1320 apic->regs + APIC_TMR); in __apic_accept_irq()
1323 apic->regs + APIC_TMR); in __apic_accept_irq()
1332 vcpu->arch.pv.pv_unhalted = 1; in __apic_accept_irq()
1354 apic->pending_events = (1UL << KVM_APIC_INIT); in __apic_accept_irq()
1362 apic->sipi_vector = vector; in __apic_accept_irq()
1365 set_bit(KVM_APIC_SIPI, &apic->pending_events); in __apic_accept_irq()
1404 map = rcu_dereference(kvm->arch.apic_map); in kvm_bitmap_or_dest_vcpus()
1412 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx; in kvm_bitmap_or_dest_vcpus()
1420 irq->shorthand, in kvm_bitmap_or_dest_vcpus()
1421 irq->dest_id, in kvm_bitmap_or_dest_vcpus()
1422 irq->dest_mode)) in kvm_bitmap_or_dest_vcpus()
1432 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; in kvm_apic_compare_prio()
1437 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); in kvm_ioapic_handles_vector()
1449 if (irqchip_split(apic->vcpu->kvm)) { in kvm_ioapic_send_eoi()
1450 apic->vcpu->arch.pending_ioapic_eoi = vector; in kvm_ioapic_send_eoi()
1451 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); in kvm_ioapic_send_eoi()
1455 if (apic_test_vector(vector, apic->regs + APIC_TMR)) in kvm_ioapic_send_eoi()
1460 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); in kvm_ioapic_send_eoi()
1473 if (vector == -1) in apic_set_eoi()
1479 if (to_hv_vcpu(apic->vcpu) && in apic_set_eoi()
1480 test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap)) in apic_set_eoi()
1481 kvm_hv_synic_send_eoi(apic->vcpu, vector); in apic_set_eoi()
1484 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_set_eoi()
1489 * this interface assumes a trap-like exit, which has already finished
1494 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_eoi_accelerated()
1499 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in kvm_apic_set_eoi_accelerated()
1524 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); in kvm_apic_send_ipi()
1537 apic->lapic_timer.period == 0) in apic_get_tmcct()
1541 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in apic_get_tmcct()
1545 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); in apic_get_tmcct()
1546 return div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->divide_count)); in apic_get_tmcct()
1551 struct kvm_vcpu *vcpu = apic->vcpu; in __report_tpr_access()
1552 struct kvm_run *run = vcpu->run; in __report_tpr_access()
1555 run->tpr_access.rip = kvm_rip_read(vcpu); in __report_tpr_access()
1556 run->tpr_access.is_write = write; in __report_tpr_access()
1561 if (apic->vcpu->arch.tpr_access_reporting) in report_tpr_access()
1604 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1608 /* Leave bits '0' for reserved and write-only registers. */ in kvm_lapic_readable_reg_mask()
1651 * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in in kvm_lapic_reg_read()
1683 return addr >= apic->base_address && in apic_mmio_in_range()
1684 addr < apic->base_address + LAPIC_MMIO_LENGTH; in apic_mmio_in_range()
1691 u32 offset = address - apic->base_address; in apic_mmio_read()
1694 return -EOPNOTSUPP; in apic_mmio_read()
1697 if (!kvm_check_has_quirk(vcpu->kvm, in apic_mmio_read()
1699 return -EOPNOTSUPP; in apic_mmio_read()
1717 apic->divide_count = 0x1 << (tmp2 & 0x7); in update_divide_count()
1727 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in limit_periodic_timer_frequency()
1730 if (apic->lapic_timer.period < min_period) { in limit_periodic_timer_frequency()
1734 apic->vcpu->vcpu_id, in limit_periodic_timer_frequency()
1735 apic->lapic_timer.period, min_period); in limit_periodic_timer_frequency()
1736 apic->lapic_timer.period = min_period; in limit_periodic_timer_frequency()
1745 hrtimer_cancel(&apic->lapic_timer.timer); in cancel_apic_timer()
1747 if (apic->lapic_timer.hv_timer_in_use) in cancel_apic_timer()
1750 atomic_set(&apic->lapic_timer.pending, 0); in cancel_apic_timer()
1756 apic->lapic_timer.timer_mode_mask; in apic_update_lvtt()
1758 if (apic->lapic_timer.timer_mode != timer_mode) { in apic_update_lvtt()
1763 apic->lapic_timer.period = 0; in apic_update_lvtt()
1764 apic->lapic_timer.tscdeadline = 0; in apic_update_lvtt()
1766 apic->lapic_timer.timer_mode = timer_mode; in apic_update_lvtt()
1773 * during a higher-priority task.
1778 struct kvm_lapic *apic = vcpu->arch.apic; in lapic_timer_int_injected()
1783 void *bitmap = apic->regs + APIC_ISR; in lapic_timer_int_injected()
1785 if (apic->apicv_active) in lapic_timer_int_injected()
1786 bitmap = apic->regs + APIC_IRR; in lapic_timer_int_injected()
1796 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; in __wait_lapic_expire()
1804 if (vcpu->arch.tsc_scaling_ratio == kvm_caps.default_tsc_scaling_ratio) { in __wait_lapic_expire()
1809 do_div(delay_ns, vcpu->arch.virtual_tsc_khz); in __wait_lapic_expire()
1817 struct kvm_lapic *apic = vcpu->arch.apic; in adjust_lapic_timer_advance()
1818 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; in adjust_lapic_timer_advance()
1828 ns = -advance_expire_delta * 1000000ULL; in adjust_lapic_timer_advance()
1829 do_div(ns, vcpu->arch.virtual_tsc_khz); in adjust_lapic_timer_advance()
1830 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP; in adjust_lapic_timer_advance()
1834 do_div(ns, vcpu->arch.virtual_tsc_khz); in adjust_lapic_timer_advance()
1840 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in adjust_lapic_timer_advance()
1845 struct kvm_lapic *apic = vcpu->arch.apic; in __kvm_wait_lapic_expire()
1848 tsc_deadline = apic->lapic_timer.expired_tscdeadline; in __kvm_wait_lapic_expire()
1849 apic->lapic_timer.expired_tscdeadline = 0; in __kvm_wait_lapic_expire()
1851 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); in __kvm_wait_lapic_expire()
1854 adjust_lapic_timer_advance(vcpu, guest_tsc - tsc_deadline); in __kvm_wait_lapic_expire()
1865 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc); in __kvm_wait_lapic_expire()
1871 vcpu->arch.apic->lapic_timer.expired_tscdeadline && in kvm_wait_lapic_expire()
1872 vcpu->arch.apic->lapic_timer.timer_advance_ns && in kvm_wait_lapic_expire()
1880 struct kvm_timer *ktimer = &apic->lapic_timer; in kvm_apic_inject_pending_timer_irqs()
1884 ktimer->tscdeadline = 0; in kvm_apic_inject_pending_timer_irqs()
1886 ktimer->tscdeadline = 0; in kvm_apic_inject_pending_timer_irqs()
1887 ktimer->target_expiration = 0; in kvm_apic_inject_pending_timer_irqs()
1893 struct kvm_vcpu *vcpu = apic->vcpu; in apic_timer_expired()
1894 struct kvm_timer *ktimer = &apic->lapic_timer; in apic_timer_expired()
1896 if (atomic_read(&apic->lapic_timer.pending)) in apic_timer_expired()
1899 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) in apic_timer_expired()
1900 ktimer->expired_tscdeadline = ktimer->tscdeadline; in apic_timer_expired()
1902 if (!from_timer_fn && apic->apicv_active) { in apic_timer_expired()
1908 if (kvm_use_posted_timer_interrupt(apic->vcpu)) { in apic_timer_expired()
1916 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && in apic_timer_expired()
1917 vcpu->arch.apic->lapic_timer.timer_advance_ns) in apic_timer_expired()
1923 atomic_inc(&apic->lapic_timer.pending); in apic_timer_expired()
1931 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_tscdeadline()
1932 u64 guest_tsc, tscdeadline = ktimer->tscdeadline; in start_sw_tscdeadline()
1935 struct kvm_vcpu *vcpu = apic->vcpu; in start_sw_tscdeadline()
1936 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; in start_sw_tscdeadline()
1948 ns = (tscdeadline - guest_tsc) * 1000000ULL; in start_sw_tscdeadline()
1952 likely(ns > apic->lapic_timer.timer_advance_ns)) { in start_sw_tscdeadline()
1954 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns); in start_sw_tscdeadline()
1955 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD); in start_sw_tscdeadline()
1964 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; in tmict_to_ns()
1972 apic->lapic_timer.period = in update_target_expiration()
1977 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in update_target_expiration()
1983 apic->divide_count, old_divisor); in update_target_expiration()
1985 apic->lapic_timer.tscdeadline += in update_target_expiration()
1986 nsec_to_cycles(apic->vcpu, ns_remaining_new) - in update_target_expiration()
1987 nsec_to_cycles(apic->vcpu, ns_remaining_old); in update_target_expiration()
1988 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); in update_target_expiration()
1998 apic->lapic_timer.period = in set_target_expiration()
2001 if (!apic->lapic_timer.period) { in set_target_expiration()
2002 apic->lapic_timer.tscdeadline = 0; in set_target_expiration()
2007 deadline = apic->lapic_timer.period; in set_target_expiration()
2015 deadline = apic->lapic_timer.period; in set_target_expiration()
2019 else if (unlikely(deadline > apic->lapic_timer.period)) { in set_target_expiration()
2024 apic->vcpu->vcpu_id, in set_target_expiration()
2027 deadline, apic->lapic_timer.period); in set_target_expiration()
2029 deadline = apic->lapic_timer.period; in set_target_expiration()
2034 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in set_target_expiration()
2035 nsec_to_cycles(apic->vcpu, deadline); in set_target_expiration()
2036 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); in set_target_expiration()
2054 apic->lapic_timer.target_expiration = in advance_periodic_target_expiration()
2055 ktime_add_ns(apic->lapic_timer.target_expiration, in advance_periodic_target_expiration()
2056 apic->lapic_timer.period); in advance_periodic_target_expiration()
2057 delta = ktime_sub(apic->lapic_timer.target_expiration, now); in advance_periodic_target_expiration()
2058 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in advance_periodic_target_expiration()
2059 nsec_to_cycles(apic->vcpu, delta); in advance_periodic_target_expiration()
2064 if (!apic->lapic_timer.period) in start_sw_period()
2068 apic->lapic_timer.target_expiration)) { in start_sw_period()
2077 hrtimer_start(&apic->lapic_timer.timer, in start_sw_period()
2078 apic->lapic_timer.target_expiration, in start_sw_period()
2087 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; in kvm_lapic_hv_timer_in_use()
2093 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in cancel_hv_timer()
2094 static_call(kvm_x86_cancel_hv_timer)(apic->vcpu); in cancel_hv_timer()
2095 apic->lapic_timer.hv_timer_in_use = false; in cancel_hv_timer()
2100 struct kvm_timer *ktimer = &apic->lapic_timer; in start_hv_timer()
2101 struct kvm_vcpu *vcpu = apic->vcpu; in start_hv_timer()
2108 if (!ktimer->tscdeadline) in start_hv_timer()
2111 if (static_call(kvm_x86_set_hv_timer)(vcpu, ktimer->tscdeadline, &expired)) in start_hv_timer()
2114 ktimer->hv_timer_in_use = true; in start_hv_timer()
2115 hrtimer_cancel(&ktimer->timer); in start_hv_timer()
2120 * VM-Exit to recompute the periodic timer's target expiration. in start_hv_timer()
2127 if (atomic_read(&ktimer->pending)) { in start_hv_timer()
2135 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use); in start_hv_timer()
2142 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_timer()
2145 if (apic->lapic_timer.hv_timer_in_use) in start_sw_timer()
2147 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) in start_sw_timer()
2154 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); in start_sw_timer()
2161 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) in restart_apic_timer()
2172 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_expired_hv_timer()
2176 if (!apic->lapic_timer.hv_timer_in_use) in kvm_lapic_expired_hv_timer()
2182 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in kvm_lapic_expired_hv_timer()
2193 restart_apic_timer(vcpu->arch.apic); in kvm_lapic_switch_to_hv_timer()
2198 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_switch_to_sw_timer()
2202 if (apic->lapic_timer.hv_timer_in_use) in kvm_lapic_switch_to_sw_timer()
2209 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_restart_hv_timer()
2211 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in kvm_lapic_restart_hv_timer()
2217 atomic_set(&apic->lapic_timer.pending, 0); in __start_apic_timer()
2235 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { in apic_manage_nmi_watchdog()
2236 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; in apic_manage_nmi_watchdog()
2238 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2240 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2249 return -1; in get_lvt_index()
2251 (reg - APIC_LVTT) >> 4, KVM_APIC_MAX_NR_LVT_ENTRIES); in get_lvt_index()
2300 for (i = 0; i < apic->nr_lvt_entries; i++) { in kvm_lapic_reg_write()
2305 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reg_write()
2348 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); in kvm_lapic_reg_write()
2363 uint32_t old_divisor = apic->divide_count; in kvm_lapic_reg_write()
2367 if (apic->divide_count != old_divisor && in kvm_lapic_reg_write()
2368 apic->lapic_timer.period) { in kvm_lapic_reg_write()
2369 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2382 * Self-IPI exists only when x2APIC is enabled. Bits 7:0 hold in kvm_lapic_reg_write()
2383 * the vector, everything else is reserved. in kvm_lapic_reg_write()
2400 kvm_recalculate_apic_map(apic->vcpu->kvm); in kvm_lapic_reg_write()
2409 unsigned int offset = address - apic->base_address; in apic_mmio_write()
2413 return -EOPNOTSUPP; in apic_mmio_write()
2416 if (!kvm_check_has_quirk(vcpu->kvm, in apic_mmio_write()
2418 return -EOPNOTSUPP; in apic_mmio_write()
2424 * APIC register must be aligned on 128-bits boundary. in apic_mmio_write()
2440 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); in kvm_lapic_set_eoi()
2452 * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but in kvm_x2apic_icr_write()
2454 * bit. And if IPI virtualization (Intel) or x2AVIC (AMD) is enabled, in kvm_x2apic_icr_write()
2455 * the CPU performs the reserved bits checks, i.e. the underlying CPU in kvm_x2apic_icr_write()
2484 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_write_nodecode()
2487 * ICR is a single 64-bit register when x2APIC is enabled, all others in kvm_apic_write_nodecode()
2488 * registers hold 32-bit values. For legacy xAPIC, ICR writes need to in kvm_apic_write_nodecode()
2495 * maybe-unecessary write, and both are in the noise anyways. in kvm_apic_write_nodecode()
2506 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_free_lapic()
2508 if (!vcpu->arch.apic) in kvm_free_lapic()
2511 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_free_lapic()
2513 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) in kvm_free_lapic()
2516 if (!apic->sw_enabled) in kvm_free_lapic()
2519 if (apic->regs) in kvm_free_lapic()
2520 free_page((unsigned long)apic->regs); in kvm_free_lapic()
2526 *----------------------------------------------------------------------
2528 *----------------------------------------------------------------------
2532 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_lapic_tscdeadline_msr()
2537 return apic->lapic_timer.tscdeadline; in kvm_get_lapic_tscdeadline_msr()
2542 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_set_lapic_tscdeadline_msr()
2547 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_set_lapic_tscdeadline_msr()
2548 apic->lapic_timer.tscdeadline = data; in kvm_set_lapic_tscdeadline_msr()
2554 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); in kvm_lapic_set_tpr()
2561 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); in kvm_lapic_get_cr8()
2568 u64 old_value = vcpu->arch.apic_base; in kvm_lapic_set_base()
2569 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_set_base()
2571 vcpu->arch.apic_base = value; in kvm_lapic_set_base()
2582 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2588 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_lapic_set_base()
2594 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2596 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2604 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()
2608 apic->base_address != APIC_DEFAULT_PHYS_BASE) { in kvm_lapic_set_base()
2609 kvm_set_apicv_inhibit(apic->vcpu->kvm, in kvm_lapic_set_base()
2616 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_apicv()
2631 apic->irr_pending = true; in kvm_apic_update_apicv()
2633 if (apic->apicv_active) in kvm_apic_update_apicv()
2634 apic->isr_count = 1; in kvm_apic_update_apicv()
2636 apic->isr_count = count_vectors(apic->regs + APIC_ISR); in kvm_apic_update_apicv()
2638 apic->highest_isr_cache = -1; in kvm_apic_update_apicv()
2647 mutex_lock(&kvm->slots_lock); in kvm_alloc_apic_access_page()
2648 if (kvm->arch.apic_access_memslot_enabled || in kvm_alloc_apic_access_page()
2649 kvm->arch.apic_access_memslot_inhibited) in kvm_alloc_apic_access_page()
2661 ret = -EFAULT; in kvm_alloc_apic_access_page()
2666 * Do not pin the page in memory, so that memory hot-unplug in kvm_alloc_apic_access_page()
2670 kvm->arch.apic_access_memslot_enabled = true; in kvm_alloc_apic_access_page()
2672 mutex_unlock(&kvm->slots_lock); in kvm_alloc_apic_access_page()
2679 struct kvm *kvm = vcpu->kvm; in kvm_inhibit_apic_access_page()
2681 if (!kvm->arch.apic_access_memslot_enabled) in kvm_inhibit_apic_access_page()
2686 mutex_lock(&kvm->slots_lock); in kvm_inhibit_apic_access_page()
2688 if (kvm->arch.apic_access_memslot_enabled) { in kvm_inhibit_apic_access_page()
2698 kvm->arch.apic_access_memslot_enabled = false; in kvm_inhibit_apic_access_page()
2704 kvm->arch.apic_access_memslot_inhibited = true; in kvm_inhibit_apic_access_page()
2707 mutex_unlock(&kvm->slots_lock); in kvm_inhibit_apic_access_page()
2714 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_reset()
2731 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reset()
2735 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_reset()
2736 kvm_apic_set_version(apic->vcpu); in kvm_lapic_reset()
2738 for (i = 0; i < apic->nr_lvt_entries; i++) in kvm_lapic_reset()
2742 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) in kvm_lapic_reset()
2768 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reset()
2770 vcpu->arch.pv_eoi.msr_val = 0; in kvm_lapic_reset()
2772 if (apic->apicv_active) { in kvm_lapic_reset()
2774 static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, -1); in kvm_lapic_reset()
2775 static_call_cond(kvm_x86_hwapic_isr_update)(-1); in kvm_lapic_reset()
2778 vcpu->arch.apic_arb_prio = 0; in kvm_lapic_reset()
2779 vcpu->arch.apic_attention = 0; in kvm_lapic_reset()
2781 kvm_recalculate_apic_map(vcpu->kvm); in kvm_lapic_reset()
2785 *----------------------------------------------------------------------
2787 *----------------------------------------------------------------------
2797 struct kvm_lapic *apic = vcpu->arch.apic; in apic_has_pending_timer()
2800 return atomic_read(&apic->lapic_timer.pending); in apic_has_pending_timer()
2818 guest_cpuid_is_intel_compatible(apic->vcpu)) in kvm_apic_local_deliver()
2827 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_nmi_wd_deliver()
2847 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); in apic_timer_fn()
2863 vcpu->arch.apic = apic; in kvm_create_lapic()
2865 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2866 if (!apic->regs) { in kvm_create_lapic()
2868 vcpu->vcpu_id); in kvm_create_lapic()
2871 apic->vcpu = vcpu; in kvm_create_lapic()
2873 apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu); in kvm_create_lapic()
2875 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, in kvm_create_lapic()
2877 apic->lapic_timer.timer.function = apic_timer_fn; in kvm_create_lapic()
2878 if (timer_advance_ns == -1) { in kvm_create_lapic()
2879 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; in kvm_create_lapic()
2882 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in kvm_create_lapic()
2890 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; in kvm_create_lapic()
2892 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); in kvm_create_lapic()
2897 vcpu->arch.apic = NULL; in kvm_create_lapic()
2899 return -ENOMEM; in kvm_create_lapic()
2904 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_has_interrupt()
2908 return -1; in kvm_apic_has_interrupt()
2917 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); in kvm_apic_accept_pic_intr()
2919 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) in kvm_apic_accept_pic_intr()
2929 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_inject_apic_timer_irqs()
2931 if (atomic_read(&apic->lapic_timer.pending) > 0) { in kvm_inject_apic_timer_irqs()
2933 atomic_set(&apic->lapic_timer.pending, 0); in kvm_inject_apic_timer_irqs()
2940 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_apic_interrupt()
2943 if (vector == -1) in kvm_get_apic_interrupt()
2944 return -1; in kvm_get_apic_interrupt()
2954 if (to_hv_vcpu(vcpu) && test_bit(vector, to_hv_synic(vcpu)->auto_eoi_bitmap)) { in kvm_get_apic_interrupt()
2956 * For auto-EOI interrupts, there might be another pending in kvm_get_apic_interrupt()
2964 * be a higher-priority pending interrupt---except if there was in kvm_get_apic_interrupt()
2978 if (apic_x2apic_mode(vcpu->arch.apic)) { in kvm_apic_state_fixup()
2979 u32 x2apic_id = kvm_x2apic_id(vcpu->arch.apic); in kvm_apic_state_fixup()
2980 u32 *id = (u32 *)(s->regs + APIC_ID); in kvm_apic_state_fixup()
2981 u32 *ldr = (u32 *)(s->regs + APIC_LDR); in kvm_apic_state_fixup()
2984 if (vcpu->kvm->arch.x2apic_format) { in kvm_apic_state_fixup()
2986 return -EINVAL; in kvm_apic_state_fixup()
3005 * if the ICR is _not_ split, ICR is internally a single 64-bit in kvm_apic_state_fixup()
3014 icr = __kvm_lapic_get_reg(s->regs, APIC_ICR) | in kvm_apic_state_fixup()
3015 (u64)__kvm_lapic_get_reg(s->regs, APIC_ICR2) << 32; in kvm_apic_state_fixup()
3016 __kvm_lapic_set_reg64(s->regs, APIC_ICR, icr); in kvm_apic_state_fixup()
3018 icr = __kvm_lapic_get_reg64(s->regs, APIC_ICR); in kvm_apic_state_fixup()
3019 __kvm_lapic_set_reg(s->regs, APIC_ICR2, icr >> 32); in kvm_apic_state_fixup()
3029 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); in kvm_apic_get_state()
3035 __kvm_lapic_set_reg(s->regs, APIC_TMCCT, in kvm_apic_get_state()
3036 __apic_read(vcpu->arch.apic, APIC_TMCCT)); in kvm_apic_get_state()
3043 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_state()
3048 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); in kvm_apic_set_state()
3050 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); in kvm_apic_set_state()
3054 kvm_recalculate_apic_map(vcpu->kvm); in kvm_apic_set_state()
3057 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); in kvm_apic_set_state()
3059 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_state()
3060 kvm_recalculate_apic_map(vcpu->kvm); in kvm_apic_set_state()
3065 apic->lapic_timer.expired_tscdeadline = 0; in kvm_apic_set_state()
3072 if (apic->apicv_active) { in kvm_apic_set_state()
3078 if (ioapic_in_kernel(vcpu->kvm)) in kvm_apic_set_state()
3081 vcpu->arch.apic_arb_prio = 0; in kvm_apic_set_state()
3094 timer = &vcpu->arch.apic->lapic_timer.timer; in __kvm_migrate_apic_timer()
3100 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
3115 * -> host disabled PV EOI. in apic_sync_pv_eoi_from_guest()
3117 * -> host enabled PV EOI, guest did not execute EOI yet. in apic_sync_pv_eoi_from_guest()
3119 * -> host enabled PV EOI, guest executed EOI. in apic_sync_pv_eoi_from_guest()
3133 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) in kvm_lapic_sync_from_vapic()
3134 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); in kvm_lapic_sync_from_vapic()
3136 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) in kvm_lapic_sync_from_vapic()
3139 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_from_vapic()
3143 apic_set_tpr(vcpu->arch.apic, data & 0xff); in kvm_lapic_sync_from_vapic()
3147 * apic_sync_pv_eoi_to_guest - called before vmentry
3157 apic->irr_pending || in apic_sync_pv_eoi_to_guest()
3159 apic->highest_isr_cache == -1 || in apic_sync_pv_eoi_to_guest()
3161 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { in apic_sync_pv_eoi_to_guest()
3169 pv_eoi_set_pending(apic->vcpu); in apic_sync_pv_eoi_to_guest()
3176 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_sync_to_vapic()
3180 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) in kvm_lapic_sync_to_vapic()
3192 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_to_vapic()
3199 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, in kvm_lapic_set_vapic_addr()
3200 &vcpu->arch.apic->vapic_cache, in kvm_lapic_set_vapic_addr()
3202 return -EINVAL; in kvm_lapic_set_vapic_addr()
3203 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); in kvm_lapic_set_vapic_addr()
3205 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); in kvm_lapic_set_vapic_addr()
3208 vcpu->arch.apic->vapic_addr = vapic_addr; in kvm_lapic_set_vapic_addr()
3232 * ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and in kvm_lapic_msr_write()
3234 * through 32-bit reads/writes. in kvm_lapic_msr_write()
3239 /* Bits 63:32 are reserved in all other registers. */ in kvm_lapic_msr_write()
3248 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_write()
3249 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_write()
3259 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_read()
3260 u32 reg = (msr - APIC_BASE_MSR) << 4; in kvm_x2apic_msr_read()
3273 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_write()
3281 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_read()
3287 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data; in kvm_lapic_set_pv_eoi()
3295 if (addr == ghc->gpa && len <= ghc->len) in kvm_lapic_set_pv_eoi()
3296 new_len = ghc->len; in kvm_lapic_set_pv_eoi()
3300 ret = kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len); in kvm_lapic_set_pv_eoi()
3305 vcpu->arch.pv_eoi.msr_val = data; in kvm_lapic_set_pv_eoi()
3312 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_accept_events()
3322 return r == -EBUSY ? 0 : r; in kvm_apic_accept_events()
3324 * Continue processing INIT/SIPI even if a nested VM-Exit in kvm_apic_accept_events()
3333 * wait-for-SIPI (WFS). in kvm_apic_accept_events()
3336 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); in kvm_apic_accept_events()
3337 clear_bit(KVM_APIC_SIPI, &apic->pending_events); in kvm_apic_accept_events()
3341 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { in kvm_apic_accept_events()
3343 if (kvm_vcpu_is_bsp(apic->vcpu)) in kvm_apic_accept_events()
3344 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; in kvm_apic_accept_events()
3346 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; in kvm_apic_accept_events()
3348 if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) { in kvm_apic_accept_events()
3349 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { in kvm_apic_accept_events()
3352 sipi_vector = apic->sipi_vector; in kvm_apic_accept_events()
3354 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; in kvm_apic_accept_events()